FR2927463A1 - Access control device i.e. memory controller, for double data rate type dynamic RAM in personal computer, has refresh control generator to maintain data in memory slots and selectively refresh memory locations indicated by register - Google Patents

Abstract

The device has an access control generator (482) for organizing requests for accessing volatile memory slots of an electronic memory i.e. double data rate (DDR) type dynamic RAM. A refresh control generator (486) maintains data in the memory slots. An allocated zone register (484) i.e. table, stores data indicating memory locations to be refreshed permanently. The refresh control generator selectively refreshes the memory locations indicated by the register.

Description

BULL5.FRD Enhanced electronic memory access control device

The invention relates to a device for controlling access to an electronic memory. The field of direct access electronic storage has grown dramatically in recent decades, from a few kilobytes to several gigabytes nowadays.

This has been made possible by DRAM technology, which allows large amounts of data to be stored with very fast access at a lower cost.

This type of memory is nevertheless limited by the volatile nature of the data it stores. Indeed, these technologies make use of micro-capacities that store the information but are unloaded alone in a few microseconds.

Therefore, considerable amounts of software and hardware efforts are deployed to maintain the data of these memories. When we know the size of the current memories and their actual average use, it is also a significant amount of electricity that is wasted to maintain portions of memory that contain no information.

The invention improves the situation.

For this purpose, the invention proposes a device for controlling access to an electronic memory, comprising, an access controller for organizing requests for access to volatile memory banks, and a cooler for maintaining the data of the memory. bench of volatile memories. This device further comprises a register for designating ranges of memory, and the cooler is arranged to selectively refresh memory ranges designated by said register.

Thus, the maintenance of the data is carried out only for the memory ranges containing data of interest, which is economical in terms of material and energy resources.

Other characteristics and advantages of the invention will appear better on reading the description which follows, taken from examples given by way of non-limiting illustration from the drawings in which:

FIG. 1 represents a basic pattern of a memory of the DRAM type;

FIG. 2 represents a diagram of an architecture comprising a memory controller according to the invention associated with a DRAM memory with four memory banks; and

FIG. 3 represents an element of the controller of FIG.

The drawings and the description below contain, for the most part, elements of a certain character. They can therefore not only serve to better understand the present invention, but also contribute to its definition, if any.

FIG. 1 shows a basic pattern 2 of a DRAM type memory bank. The term matrix can also be used to refer to the DRAM, as it is usually seen as a set of columns and rows of capabilities accessed.

Pattern 2 includes row selection lines 4, bit lines 6, and an output line 8. Row select lines 6 provide access to a set of capacitors 10 by means of solid state transistors. access 12.

The bit lines 6 are in fact doubled into lines of bits "+" and "-" not shown, and the access transistors 12 are organized in such a way that the potential of the capacitance 10 can be read differentially on the two lines of bits "+" and "".

The lines 6 are selected by means of a row selector 14 which activates a row to be read on the basis of read addresses a0 and al which it receives.

The bit lines "~" and "-" are preloaded and pre-equalized to half the potential of the power supply, and one serves as a reference to the other.

On activation of a row, the differential reading of bit lines "+" and "" of a bit line 6 is done in a differential amplifier 16, also called Sense Amplifier.

In addition to reading the bit lines 6, the differential amplifier 16 has two other roles:

regenerate a correct potential on the bit lines "+" and "-" and in the capacitance 10 accessed, as the potential of the latter has been altered during reading, a charge pump mechanism to reach the level 25 the power supply behind the access transistor 12, if applicable;

- act as a memory point as long as the information in row 4 is to be used.

The output lines 8 are connected to a data selector 18. The data selector 16 allows access to the value of a memory point at the intersection of the activated row and a given column by a selector column 20 which receives as input addresses a2 and a3. The output of the data selector 18 is connected to the data bus 22.

The whole of the differential amplifier 16 with the data selector 20 constitutes a matrix of SRAM type standard memory points. Access of a row of the DRAM initializes the values of this SRAM. The column access is only the exploitation of said SRAM.

As the access time of a row is very long (several tens of ns) a large number of bits at a time will be read at a time, the size of a row up to 16 Kbits for a DRAM of 1 Gbit. The goal is to find among the bits of the row a maximum access column to operate, these accesses being much faster than the access of a row.

Another peculiarity of this memory is the degradation of information over time due to various leaks, hence the name of dynamic memory. To compensate for this degradation a periodic refresh of the matrix is necessary, as will appear below.

For this purpose, the memory also comprises a set of latches 24 synchronized by a RAS row access signal, via a multiplexer 26. These elements make it possible to perform the failovers required for the write, refresh and read operations in the data. bit lines 6.

Figure 2 shows a simplified diagram of a conventional DRAM architecture 30 to four banks 32 of memory.

For access to the banks, the banks 32 are connected to a decoder 34 which receives the addresses to be read, and carries out the demultiplexing, the decoding and the switches for accessing the bank and the corresponding row address in this box. bank.

For access to the columns 36, the banks 32 are connected to a decoder 36 which receives the addresses to be read, and performs the decoding and switching to the bank access and the corresponding column address in this bank.

Typically, the number of memory banks in the DRAMs is currently limited to a maximum of eight.

This representation is simplified. Physical implementations generally involve: - a row demultiplexer, connected to a buffer row address register, decoders and row latch sets for each memory bank; A buffer column address register, decoders and sets of column latches for each memory bank.

Depending on the characteristics sought for the DRAM, the four banks 32 are more or less operable independently. Thus, to obtain the best performing DRAM, the banks 32 will be fully decoupled. On the other hand, as is the case here, it is common for operations on banks 32 to be coupled more or less loosely, for reasons of distribution of consumption peaks. The DRAM 30 is controlled by an interface that includes an address bus 38, a control bus 39 and a data bus 40. The signals transmitted by these buses are processed by a memory controller 42. The memory controller 42 comprises a control decoder 44, a mode register 46, and a logic controller 48. The control decoder 44 receives control signals CS #, WE #, CAS # and RAS # from the control bus 39. The combination of the signals CS #, WE #, CAS # and RAS # at the sampling time of the clock allows the decoder 44 to determine the command to be performed.

Among the most common commands are: rest; the cycle without operation; pre-charge; activation, that is, staged access, also called "activate"; reading or writing a column; writing burst termination, also called "burst terminate" self refresh; and loading the mode register 46.

The mode register 46 makes it possible to configure various modes of operation. It serves for example to define the data burst length, also called burst length, the data frame, also called wrap mode or the electrical configuration of the data bus 40. The logic controller 48 receives signals from the control decoder 44 and the mode register 46, on the basis of which it determines the operations to be performed in terms of reading and writing in the banks 32.

The logic controller 48 includes a set of filter-like logic functions, which designate a row address to access to refresh the row in question, or read or write to a specific row address.

The logic controller 48 is connected to a cooler 50. The cooler 50 is a counter that refreshes a row received from the logic controller 48 after a given number of cycles. In other embodiments, the cooler 50 may to be integrated in the memory controller 42 so that it communicates directly with the banks 32. The cooler 50 can then board some or all of the logic of the logic controller 48 refresh logic.

In still other embodiments, a mixed embodiment may be envisaged, in which the logic controller 48 and the cooler 50 each share part of the refresh logic. The interface of the DRAM is synchronized by means of a fast clock CLK, which makes it possible to express each of the operations in a number of cycles of this clock. A CKE signal is also received to control the activation of the DRAM.

The operations associated with these commands may further require the presence of a specific address or code on the address bus.

The durations of the operations vary according to the sequence of the orders. This makes it possible to ensure proper electrical operation both at the level of the cell matrices and for the proper use of the data bus.

Some durations may arise from needs related to consumption considerations. This is for example the case with the tRRD, which imposes the duration between two "activate" commands, including on separate banks, or even with the tFAW, which imposes a total duration for 4 consecutive activation commands.

The result of these operations is managed at the data bus 40 by a multiplexer / demultiplexer 52. The multiplexer / demultiplexer 52 stores the values of the read memory addresses based on the rows designated by the decoders 34, and columns designated by the decoder 36. The data exchanges on the data bus 40 are managed by an input / output register 54 for communication with the outside.

It is on the data bus 40, which is bidirectional, that the data coming from or destined for all memory banks 32 is found. The user must himself manage the occupation of the bus at the close cycle.

With DRAM type DDR interfaces, there are two data per clock cycle, one for each clock edge. Most of the constraints are borne by the user since he must provide the DRAM, in addition to the data, with a data byte sampling signal called the DQS, each DQS edge serving to sample said data. in the DRAM.

This means that, in the presence of data, the DQS signals are identical to the quarter-cycle clock signal. On the other hand, at the output, when the DRAM returns the DQS at the same time as the read data, the edges of the DQS are synchronous with the return clock.

It is then again for the user to generate the sampling signals from the received DQS using a delay-locked loop, also called DLL or Delay Lock Loop.

When the direction of the data bus 40 is returned, a few cycles are lost during which the bus is held in high impedance, in order to avoid a short circuit of the elements that write on the bus, and taking into account the delays. transfer and synchronization. It is therefore necessary to avoid returning the data bus 40 too often.

Because writes are less latency sensitive than reads, DRAM controllers typically delay writes in order to aggregate them to increase DRAM efficiency.

Fig. 3 shows an embodiment of the logic controller 48.

The logic controller 48 has three main elements: an access control generator 482; a register of allocated areas 484; and

a refresh command generator 486.

When the logic controller 48 receives the signals from the control decoder 44 and the mode register 46, it directs them either to the access control generator 482 or to the refresh command generator 486. The command generator 48 The access 482 uses the received signals to determine the operations to be performed in terms of reading and writing in the banks 32.

The allocated area register 484 stores data that indicates ranges or address areas of the memory that contain data that is useful to the system that operates the memory. The role of this registry will appear better with the following.

The refresh manager 486 cooperates with the allocated area register 484 to send refresh commands to the cooler 50.

In a conventional setting, the DRAM constructor imposes the refresh time for the entire merge, typically 64ms, and gives the number of rows to refresh, for example 8K, ie one row to refresh every 7.8ps or so. It is then up to the user to determine the insertion times of the most suitable self-refresh commands in order not to penalize his own access too much.

For this, it must be taken into account that this command will have to close all rows still open on all banks to refresh the row identified by the refresh counter. The duration of an auto refresh command is typically about 10 60 ns, and the refresh takes between 1% and 2% of the total memory bandwidth. In the context of the invention, the allocated area register 484 allows the controller 42 to optimize the management of the memory. Indeed, the allocated area register 484 is accessible by the system that exploits the memory.

This access makes it possible to allocate new memory addresses only in the zones in which memory addresses have already been allocated, and to require that these zones be filled before "opening" a new zone.

Thus, the refresh manager 486 may only perform refresh for those areas of the memory that contain data of interest.

Since the data are evanescent in nature, this amounts to not feeding the memory areas that are not designated in the allocated area register. Therefore, significant consumption gains can be made, especially during a standby mode. Typically, the areas of the allocated area register are memory address ranges that are determined in advance.

A given area will thus contain a selected number of contiguous lines in the memory banks, and is defined by index and size.

As the size of the banks is known, the size and index of each zone unambiguously define the range of corresponding addresses.

However, for reasons of cost and performance, the size of the allocated area register 484 should not be too large. Nevertheless, the larger the size of the zones, the smaller the gains will be.

It is therefore necessary to make a compromise between the granularity of the areas and the desired gains.

The allocated area register can be implemented in several ways. Thus, it can be realized in the form of a stack which contains only the indices of the allocated memory areas. In another form, it can be realized by a table of indices accompanied each time by an indicator, a "1" indicating that the zone is allocated, and a "0" indicating conversely that the zone is free .

It is important that the memory allocation device on the system side that operates the memory be synchronized with the allocated area register 484. This ensures the proper operation of the invention.

Thus, when a memory address is released from the system side, it must be determined on the system side if this memory address was the last activated of a given allocated area, to allow to reflect in the allocated address register 484 that this zone is no longer allocated. As part of an application to a PC-type computer, which uses as a Linux operating system (registered trademark), a known operating system memory allocator is Slab_alloc. A higher level allocator, which we will call Chunkalloc, can be integrated into the existing structure. The blocks available for Slab_alloc will no longer be chosen from the memory in its entirety, but from the areas of the memory that are managed by ChunkAlloc.

This allocator must therefore maintain a correspondence table of the addresses it has allocated and corresponding memory areas.

For reasons of data consistency at startup, the operating system must boot while keeping the refresh active on all areas of the memory. Then, once ChunkAlloc started and initialized, it will have the task of turning off the inactive areas and can at this time perform its role of allocator.

The correspondence maintained by the allocator is here described in the form of a table, but it can be done in any other form suitable for maintaining a coherent view of the memory occupancy on the allocator side.

As part of this application, it has been determined that for a 4GB memory, a set of 4096 memory areas represents an interesting compromise. Each allocated memory area then contains a range of 1 MB.

For more appropriate management, the allocator can allocate the memory addresses in batch of 64kB, and the correspondence to be maintained is then based on the allocation of these batches and not on the basis of the individual allocated memory addresses. a memory access is requested for a memory address in a zone not yet allocated, the allocator sends two requests.

The first request is addressed to the access control generator 482 for the access itself.

The second request is addressed to the allocated area register 484 to modify it and reflect the allocation of the memory area concerned. This request therefore forms a request to turn on the memory range in question.

Conversely, when the last set of memory addresses of a given allocated area is released by the system, the allocator issues a request to the allocated area register 484 to modify it and reflect the deallocation of the area of memory concerned. . This request therefore forms a request to turn off the memory range in question.

Alternatively, the allocator can issue particular refresh requests. These requests are interpreted by the refresh command generator 20 not as conventional refresh requests, but as requests to modify the allocated zone register 484.

The refresh of the memory banks can thus be managed by the allocator directly, or internally by the refresh control manager 486 in cooperation with the refresher 50, the latter being able to filter the unallocated areas so as not to refresh them.

From a hardware point of view, the invention has been presented with reference to functionally grouped registers and elements. This grouping was presented for explanation purposes.

These registers and elements can be implemented in various ways, without being grouped as shown for example or by being implemented together in a single block.

In addition, in the foregoing, it will be appreciated that all variants can be combined together to the extent of their compatibility. Although preferred modes have been presented, it goes without saying that the invention encompasses all of these variants and their combination.

Claims (5)

claims An electronic memory access control device, comprising, an access controller (482) for organizing access requests to volatile memory banks (32), and a refresher (486) for maintaining the data. of the volatile memory bank (32), characterized in that it further comprises a register (484) for designating memory ranges and in that the cooler (486) is arranged to selectively refresh memory ranges designated by said memory bank register (484). 2. Device according to claim 1, characterized in that the register (484) is a table comprising memory range indices each associated with a refresh indicator. 3. Device according to claim 2, characterized in that the register (484) is arranged to receive a request to extinguish a range of memory, and to modify the refresh indicator associated with the index of the range of memory concerned so that it is not refreshed. 4. Device according to claim 2 or 3, characterized in that the register (484) is arranged to receive a request to extinguish a range of memory, and to modify the refresh indicator associated with the index of the range. of memory concerned so that it is refreshed. 5. Device according to one of the preceding claims, characterized in that the register (484) comprises data designating memory ranges to be refreshed permanently. 15