FR2923080A1 - Forming vias in semiconductor wafer, by making wafer having closed perimeter on its front side, filling wafer with dielectric material, thinning wafer by abrasion and/or etching, and removing semiconductor extending inside perimeter - Google Patents

Abstract

The process for forming vias (20) in a semiconductor wafer, comprises making a wafer that has a closed perimeter on its front side, filling the wafer with a dielectric material, thinning the wafer by abrasion and/or by dry etching on its backside of until a bottom of the wafer is reached, removing the semiconductor that extends inside the closed perimeter to provide a cavity whose wall is coated with a dielectric material, forming an electrically conductive plate extending above the perimeter on front side of the wafer, and etching a first dielectric layer (202) at the bottom of the cavity. The process for forming vias (20) in a semiconductor wafer, comprises making a wafer that has a closed perimeter on its front side, filling the wafer with a dielectric material, thinning the wafer by abrasion and/or by dry etching on its backside of until a bottom of the wafer is reached, removing the semiconductor that extends inside the closed perimeter to provide a cavity whose wall is coated with a dielectric material, forming an electrically conductive plate extending above the perimeter on front side of the wafer, etching a first dielectric layer (202) at the bottom of the cavity, and placing a second dielectric layer (207) on backside of the wafer and then etching the layer to create a window in the layer. The wafer is present in the form of a ring. The semiconductor extending at the inner side of the perimeter is removed by dry and/or selective wet etching. The cavity is totally or partially filled with an electrically conductive material (203). The semiconductor material is placed on a support (206) such as a glass plate before thinning the wafer. Independent claims are included for: (1) a process for the fabrication of integrated circuits on a semiconductor wafer; and (2) a micromodule for capturing an image.

Description

1

METHOD OF FORMING A VIA IN A SEMICONDUCTOR WAFER

The present invention relates to the manufacture of integrated circuits on a semiconductor wafer and more particularly the formation of conductive orifices passing through a semiconductor wafer, called vias. Making electrical connections between a semiconductor chip and an interconnect carrier has always been a delicate problem for the technologist. For years, "chip and wire" and "flip-chip" type connections have been used mostly in the industry. A "chip and wire" type connection consists of electrically connecting the contact pads of a chip and the contact pads of an interconnection support by means of ultrasonic wire bonding son ("ultrasonic wire bonding"). . The "chip and wire" connections have the disadvantage of being bulky both in height (height of the loops formed by the wires) and in terms of the area occupied, since the contact pads of the interconnection support must be substantially face of the contact pads of the chip. A "flip-chip" type connection consists in directly applying contact pads of a chip to contact pads of an interconnection support, by means of a fusible material (solder) or a conductive glue. A "flip-chip" connection thus requires flipping the chip so that its front face is oriented downwards and that its contact pads are found in front of the contact pads of the interconnection support. However, some integrated circuits 2 such as CMOS ("Complementary Metal Oxide Semiconductor") imagers can not be mounted upside down on an interconnection support because their front face has sensitive optical zones that must receive light through a lens. . The idea of making vias through a semiconductor wafer, or vias "TWV" ("Through-Wafer Via"), is known for a long time but its implementation on an industrial scale ran up for years the excessive thickness of the semiconductor wafers, which prevented through holes from forming and metallize them with production rates and satisfactory manufacturing yields.

TWV vias forming techniques can today be exploited industrially thanks to the progress made in the thinning of the semiconductor wafers by abrasion of their back face. These methods make it possible to reduce to a few tens of micrometers the thickness of a semiconductor wafer with an initial thickness of a few hundred micrometers. The techniques of training vias are experiencing a significant growth, especially in applications where a high level of integration is sought. One advantage of making vias in a semiconductor material is that it becomes possible to have on the back of a chip a set of contacts connected to an integrated circuit region implanted on the front face of the chip. . Such rear-panel contacts make it possible to stack chips one above the other and to create "built-in" 3D integrated circuit architectures, or more simply to directly connect a chip to an interconnection support without 3

use wire and without having to turn the chip upside down. For the sake of clarity, FIG. 1 shows the front face of a silicon wafer 1 comprising integrated circuit regions 2. These will be further individualized by cutting the wafer 1 along cutting lines 3 represented in dotted lines. Figure 2A shows an area of the front face of the wafer including an integrated circuit region 2 and Figure 2B shows a corresponding area of the back face of the wafer. At the periphery of the integrated circuit region 2 are provided conductive pads 4 (FIG 2A) connected to the inputs / outputs of the region 2 via conductive tracks 4 '. The plates 4 are connected to contact pads 5 located on the rear face of the wafer 1 (FIG 2B) via vias 1.0 and conductive tracks 11. The contact pads 5 can be coated with conductive beads 6 ("bumps") formed with a fusible alloy or conductive glue. Figure 3 is a sectional view of the wafer 1 in a region comprising a via 10 and schematically shows the structure of via. The via 10 comprises an orifice 101 which passes through the wafer 1. The orifice 101 is filled with a conductive material 102 and its wall is covered with a dielectric material 103 which electrically isolates the conductive material 102 relative to the silicon forming the wafer. The conductive material 102 is electrically connected to a conductive track 104 which extends on the rear face of the wafer and one end of which forms a conductive pad 105. The pad 7.05 is covered by a conductive material forming the contact pad 5 shown in FIG. 2B, which receives the conductive bead 6. The conductive material 4

1.02 is also electrically connected to a conductive track 106 which extends on the front face of the wafer, one end of which is electrically connected to the integrated circuit region 2. Thus, the contact area 5 on the rear face is connected to the integrated circuit region 2 on the front face through the track 104, the conductive material 102 and the track 106. A via of the type shown in Figure 3 can be formed at different times relative to the manufacturing process of the regions of integrated circuits. Two solutions are generally distinguished, each with its advantages and disadvantages: - to realize the via before the beginning of the manufacturing process of the integrated circuit regions (so-called "pre-process" technique) or during the manufacturing process (so-called " mid-process "), or - achieve the via at the end of the manufacturing process of integrated circuit regions (technique called" post-process ").

In "pre-process" or "mid-process", the formation of via may reveal defects on the surface of the silicon wafer 1 that may have an impact on the quality of the integrated circuits made. Moreover, the conductive material 102 undergoes thermal cycles of large amplitude and can generate cracks or insulation defects in the via by expansion and contraction effect. In "post-process", the via is realized after manufacturing integrated circuit regions. As a result, it may happen that the silicon wafer can no longer be brought to a desired temperature to deposit the dielectric material 103. This gives a via coated with a dielectric of poor quality. The present invention is directed to a method of forming a via whose wall is coated with a dielectric material having good insulating properties, while offering the possibility of forming the via after the manufacture of integrated circuit regions. More particularly, an embodiment of the invention relates to a method of forming a via in a semiconductor wafer, comprising the steps of i) trenching a front face of the wafer, the trench defining a closed perimeter, ii) filling the trench with a dielectric material, iii) thinning the plate by abrasion and / or etching of its back face, until it reaches at least the bottom of the trench, and iv) removing the semiconductor extending inside the closed perimeter defined by the trench, so as to reveal a cavity whose wall is coated with the dielectric material. According to one embodiment, the method comprises, before step iv), a step of forming on the front face of the wafer an electrically conductive range extending above the perimeter delimited by the trench and isolated from the semiconductor. conductive by at least a first dielectric layer. According to one embodiment, the method comprises, after step iv), a step of etching the first dielectric layer at the bottom of the cavity. According to one embodiment, the method comprises, before step iv), the steps of depositing at least a second dielectric layer on the rear face of the wafer, and etching the dielectric layer so as to create a window in the layer. view of the perimeter delimited by the trench. According to one embodiment, the trench is made by dry etching of the semiconductor. According to one embodiment, the trench is filled with a subatmospheric vapor deposited TEOS oxide. According to one embodiment, the trench is substantially ring-shaped. According to one embodiment, the semiconductor extending inside the perimeter delimited by the trench is removed by dry etching. According to one embodiment, the semiconductor 10 extending inside the perimeter delimited by the trench is removed by selective wet etching. According to one embodiment, the method comprises, after step iv), a step of completely filling the cavity with an electrically conductive material. According to one embodiment, the method comprises, after step iv), a step of partially filling the cavity by means of a layer of an electrically conductive material. According to one embodiment, the method comprises a step of placing the semiconductor wafer on a carrier prior to thinning the wafer. According to one embodiment, the support is a glass plate. An embodiment of the invention also relates to a method of manufacturing semiconductor wafer integrated circuits, including vias forming steps according to the method described above. According to one embodiment, steps i) and ii) of the via formation process are conducted before or during the implementation of integrated circuit regions on the semiconductor wafer. According to one embodiment, steps iii) and iv) of the via formation method are conducted after 7

implementation of integrated circuit regions on the semiconductor wafer. According to one embodiment, the method comprises a step of depositing and etching at least one layer of conductive material to form conductive tracks and contact pads, the tracks providing the electrical connection between the contact pads and the vias. . According to one embodiment, the method comprises a step of cutting the wafer to form individual chips. According to one embodiment, the integrated circuits are CMOS imagers. An embodiment of the invention also relates to an image capture micromodule comprising a CMOS imager wafer having an integrated circuit region connected to an interconnect carrier via vias made in accordance with the method described herein. -above. According to one embodiment, the vias of the CMOS imager wafer have an inner wall having stacked "C" shaped corrugations, the convex portion of which is oriented towards the interior of the vias. Methods of forming vias across a semiconductor wafer will be described in the following with reference to, but not limited to, the accompanying figures, in which: FIG. 1 previously described depicts the front face of a semiconductor wafer; 2, 2B previously described represent the front face and the rear face of a region of the semiconductor wafer of FIG. 1; FIG. 3 previously described is a sectional view of a via the semiconductor wafer of FIG. Figures 4A to 4G are sectional views of a semiconductor wafer illustrating steps of forming a via according to a first method, -. FIGS. 5A to 5E are cross-sectional views of a semiconductor wafer illustrating steps of forming a via according to a second method; FIG. 6 illustrates a variant of a step shown in FIG. 5D; -. Figs. 7A1, 7A2, 7B1, 7B2, 7C to 7J are cross-sectional views of a silicon wafer illustrating steps of forming a via according to a third method, -. Figures 8A and 8B illustrate alternative steps illustrated in Figures 7B1 and 7J, -. Figs. 9A, 9B illustrate a feature of a via formed according to the third method, and -. Figure 10 illustrates an application of the invention for the manufacture of an image capture micromodule. Methods of formation of via designated "Method 1", "Method 2" and "Method 3" are described below. Method 3 is an embodiment of the method of forming via according to the invention. Processes 1 and 2 do not have the essential features of the invention as set forth in the claims and are only set forth herein to facilitate understanding of the invention and especially to enable those skilled in the art to better understand the process. and the benefits it can offer. Methods 1 and 2 are not known to the public and, unless proven otherwise, are therefore not considered part of the state of the art. Process 1 Figs. 4A to 4G are cross-sectional views of a silicon wafer 1 illustrating steps of forming a via via 20 "pre-process" or "mid-process" conduits, either at the beginning or in the middle of an integrated circuit manufacturing process. For the sake of 9

simplicity alone is represented the portion of the wafer 1 where the via 20 must be formed. A corresponding integrated circuit region, not shown, is made in the vicinity of the via as it appears in Figure 3 previously described. Method 1 firstly comprises forming a blind hole 201 in the silicon on the front face of the silicon wafer (Figure 4A) via a resin mask M1. The front face of the wafer 1, the bottom and the wall of the blind hole 201 are then coated with a dielectric layer 202 (FIG 4B). The blind hole 201 is then filled with a conductive material 203. The material 203 may be polysilicon (polycrystalline silicon) if the process is carried out at the beginning of the process or a metal such as tungsten if the process is carried out in a medium of processes, after polysilicon layers (including transistor gates) have been formed in the integrated circuit region. A conductive material 204 connecting the material 203 to the integrated circuit region is then deposited and etched (Fig. 4D) and then covered by an insulating or passivating layer 205. When the manufacturing process of the integrated circuit regions is completed, the wafer 1 is turned over and is placed on a support 206, for example a polymer strip or a glass plate, and is then subjected to a thinning step (FIG 4E) by abrasion and / or etching of its rear face. The thinning step is conducted until the bottom of the blind hole 201 is reached and the conductive material 203 opens on the back side, the insulating layer 202 at the bottom of the blind hole being removed by abrasion. The via 20 passing through the wafer 1 is then formed. Subsequent steps illustrated (Fig. 4F, 4G) form ranges 10

of contact and routing of via to these contact areas. The rear face of the wafer is for example coated with a dielectric layer 207 (FIG 4F) which is etched via a mask M2 to create a window in front of via 20. A conductive material 208 is then deposited and etched on the back side of the wafer (Fig. 4G) to form a conductive track which routes the contact via to a contact pad on the rear face (not shown).

In summary, the method 1 makes it possible to deposit the dielectric material 202 (FIG 4B) at a temperature of between 400 and 500 ° C., in order to obtain good electrical insulation properties of the via wall 20, since the silicon wafer in the pre-process or mid-process phase can be subjected to high temperatures. The deposition of dielectric at such temperatures also makes it possible to obtain a good ratio between the thickness deposited on the front face of the wafer and the thickness deposited on the walls of the blind hole 201, for example of the order of 90.degree. %. However, as mentioned above, the realization of the blind hole 201 may show on the front face of the wafer defects in surface uniformity harmful to the manufacturing process of integrated circuit regions, especially with the recent techniques of photolithography having a very fine pitch pitch of 0.18 micrometers or less. In addition, the silicon wafer is subjected to thermal cycles of large amplitude during the manufacture of integrated circuit regions (which may include temperatures above 1000 ° C). During these thermal cycles, the conductive material 203 generates expansion and contraction forces which can cause cracks or insulation failures in the via. 11

Method 2 Figs. 5A to 5E are cross-sectional views of a silicon wafer 1 'illustrating steps of forming a via 30 in "post-process", ie after the fabrication of integrated circuit regions. As before, only the part of the silicon wafer where the via 30 is to be formed is represented. During the manufacturing steps of the integrated circuit regions, a conductive layer 302 connected to an integrated circuit region has been formed on the front face of the wafer 1 ', opposite the location of the via 30 to achieve. The conductive layer 302 is isolated from the silicon forming the wafer 1 'by a dielectric layer 303 and is covered by an insulating or passivating layer 304. The wafer 1' is then inverted and placed on a support 305 (FIG. subjected to a step of thinning by abrasion and / or etching of its rear face. The support 305 is for example a polymer strip or a glass plate.

A cavity 306 is then etched in the wafer 1 '(FIG 5B), from its rear face and through an etching mask M3, until reaching the dielectric layer 303. The rear face of the plate 1 ', the wall and the bottom of the cavity 306 are then coated with a dielectric layer 307 (Figure 5C). An etching step is then applied to the rear face of the wafer (FIG 5D) via an etching mask M4 having a window at the bottom of the cavity 306, so as to remove the insulating layers 307 and 303 at the bottom of the cavity 306 until reaching the conductive layer 302. The cavity 306 whose bottom is thus "open" is then filled with a conductive material 308 (FIG.5E), which can also be used to form a conductive track 309 and a contact pad (not shown). An insulating layer 12

or passivation (not shown) can then be deposited on the material 308 and the track 309. FIG. 6 shows a variant of the step of FIG. 5D which is different from the latter in that the cavity 306 is of frustoconical shape. The formation of a via after completion of the integrated circuit regions, in accordance with method 2, may be more convenient than the formation of a via at the beginning or middle of the integrated circuit region manufacturing process, in accordance with FIG. Method 1. In particular, electrical test sequences of the integrated circuits can be conducted before formation of the via, so that the electrical test after formation of the via will be limited to the test of the via itself (continuity test and isolation) . A disadvantage of the method 2 is that the wall of the cavity 306 must be protected by the mask M4 during the etching of the insulating layers 307 and 303 at the bottom of the cavity 306, as shown in FIGS. 5D or 6. Indeed, even using an anisotropic etching agent favoring etching in the vertical direction, the risk exists that the etching agent attacks the layer 307 on the wall of the cavity, and this risk is greater in the embodiment of Figure 6 where the wall of the cavity is inclined and is thus exposed to the vertical component of the etching agent. However, the production of an etching mask on a vertical or inclined wall complicates the process of forming the via. The high temperatures may furthermore be prohibited in post-process, for example if thinned silicon wafer is placed on a polymeric support 305 which is not resistant to high temperatures, or if the silicon wafer includes elements which do not support high temperatures, like a matrix 13

microlenses in CMOS imager resin. In this case, the method 2 does not make it possible to deposit the dielectric material 307 under an ideal temperature of stabilization of its dielectric properties and one obtains a via coated with a porous dielectric, having a dielectric constant that is poor and weakly resistant to breakdown. . In addition, the deposition of the dielectric 307 at low temperature does not make it possible to obtain a good ratio between the thickness deposited on the walls of the cavity 306 and the thickness deposited on the front face of the wafer, this ratio being for example about 25%. In this case, and although it does not appear in FIG. 5C which is not to scale for the sake of simplification of the drawing, it is necessary to deposit a dielectric excess thickness 307 on the front face of the wafer in order to to obtain the desired dielectric thickness on the walls of the cavity 306. Method 3 Figs. 7A1, 7B1, 7C to 7J are sectional views of a silicon wafer 1 "illustrating steps of forming a via 40 according to method 3. As above, only the part of the silicon wafer where the via 40 is made is shown in FIGURE 7A2, a sectional view of the via 40 in formation as shown in section in FIG. 7B2 is a cross-section of the via 40 in formation as shown in section in Figure 7B1 In a step illustrated in Figures 7A1, 7A2, a trench 401 is etched on the front face of the silicon wafer 1 " . The trench delimits a closed perimeter and is for example in the form of a ring. Although such a circular shape is the most practical to achieve in microelectronics, the trench could be of different shape, namely rectangular or polygonal. 14

As an exemplary embodiment, the trench 401 has for example a width L of 1 to 3 micrometers, a depth P of 70 to 100 micrometers, less than the thickness of the wafer 1 "(typically of the order of 500 700 micrometers before thinning), and a small diameter D of the order of 60 microns Trench 401 is for example formed by dry etching by means of the DRIE ("Deep Reactive Ion Etching" or "deep reactive ion etching") method. , machines specifically allowing this type of etching being currently available on the market for equipment for microelectronics During a step illustrated in Figures 7B1, 7B2, the trench 401 is filled with a dielectric material 402. The dielectric 402 is for example a TEOS (tetraethylorthosilicate) oxide deposited by means of a SACVD ("subatmospheric chemical vapor deposition" or "subatmospheric vapor phase deposition") process. The dielectric 402 is first formed on the walls of the trench 401 and the deposition process of these layers is preferably continued until the layers join to completely fill the trench. The front face of the wafer 1 "is simultaneously covered by the dielectric 402.

The step of filling the trench 401 can advantageously be conducted in "pre-process" or "half-process", in order to be able to deposit the dielectric 402 without temperature limitation, the ideal temperature for depositing a TEOS oxide being typically of the order of 460 to 480 ° C at present. The dielectric material 402 made in this manner has a satisfactory dielectric constant and thickness, and it is easy to fill the trench 401. If the dielectric 402 is deposited in "pre-process", the dielectric layer 402 deposited on the The front face of the wafer 1 "is then removed, for example by means of a process CMP (" Chemical Mechanical Polishing ", a mechanical and chemical polishing combining mechanical abrasion and chemical etching).

If the dielectric 402 is deposited in "mid-process", the dielectric layer 402 deposited on the front face of the wafer may advantageously be a dielectric layer involved in the manufacture of the integrated circuit regions, for example an IMD dielectric layer (inter dielectric metallic). In this case, it is not necessary to remove it. It is assumed in the following that this solution has been retained here, so that the layer 402 will continue to appear in the following figures.

After forming the trench 401 and depositing the dielectric 402, the normal process of manufacturing integrated circuit regions can be conducted or continued (forming transistors, forming and etching the metal layers on the front face of the wafer 1 ", etc. Thus, in the step shown in Figure 7C, the integrated circuit regions have been implanted in the wafer 1 ", although not shown in the figure. During the manufacture of these integrated circuit regions, a conductive layer 403 connected to an integrated circuit region corresponding to the via 40 to be made was formed on the front face of the wafer 1 ", opposite the location of the future via 40 The conductive layer 403 is isolated from the wafer by the dielectric layer 402 and is covered by an insulating or passivating layer 405. Conventional materials can be used, namely polysilicon, metal or alloy for the layer 403, oxide SiO2 or polymer passivation for layer 405. 16

In the step shown in FIG. 7D, the wafer 1 "has been turned over and placed on a support 406. As previously the support 406 may be a polymer tape (" tape ") or a glass plate if the wafer 1" comprises for example CMOS imagers. The wafer 1 "is then subjected to a step of thinning by abrasion and / or etching of its rear face until it reaches at least the trench 401 filled with the dielectric material 402. This thinning stage, generally called" backlap "or "backgrinding" is conducted by mechanical abrasion or chemical etching of its back face, or by mechanical abrasion followed by chemical etching.This thinning step may be continued beyond the point where the trench 401 filled with dielectric material 402 is reached, if the via 40 to be made must be a depth less than the initial depth of the trench 401 or to ensure that the bottom of the trench is reached on the entire periphery of the trench.

During a step shown in FIG. 7E, a layer of dielectric material 407, for example silicon oxide SiO 2, is deposited on the rear face of the wafer 1 ". During a step illustrated in FIG. FIG. 7F, the dielectric layer 407 is etched via a mask M5 to create in the dielectric 407 a window lying opposite the silicon extending in the middle of the closed perimeter delimited by the trench 401, the window being here During a step illustrated in FIG. 7G, the silicon extending in the aforementioned perimeter is etched to reveal a cavity 408 whose wall is formed or covered by the dielectric material 402. The etching is conducted until reaching the dielectric layer 402. In a step illustrated in FIG. 7H, the dielectric layer 402 appearing at 17

The bottom of the cavity 408 is etched to the conductive layer 403, which is electrically connected to the integrated circuit region. This gives a beginning of via which will further receive a conductive material to form the via 40 itself. The step of etching the via 40 in three sub-steps, namely etching of the dielectric layer 407 (FIG 7F), etching of the silicon to form the cavity 408 (FIG 7G) and etching of the dielectric layer 402 at the bottom of the cavity 408, is an optional feature which, however, has the advantage of being able to use different and selective etching processes. For example, the dielectric layers 402, 407 may be etched using a conventional plasma etching process if they are silicon oxide, and the cavity 408 may be formed using the DRIE dry etching method. The cavity 408 can also be formed by selective wet etching of the silicon, using the dielectric materials 402, 402, 407 which extend all around the region to be etched and are not attacked by the wet etching agent. During a step shown in Figure 7I, a layer of a conductive material 409 is deposited within the cavity 408 and comes into contact with the conductive layer 403 at the bottom of the cavity. The layer 409 can also be deposited and then etched on the rear face of the wafer 1 "to obtain a conductive track 410 ending in a contact pad (not shown, see for example FIG. 3, range 105) which can then be covered by another conductive layer and a conductive bead (see Fig. 3, range 5 and bead 6) During a step shown in Fig. 7J, an insulating or passivating material 411 is deposited over the entire rear face of the wafer 18

1 "with the exception of the contact pads, the material 411 also covering the via 40. The conductive layer 409 may be a metal layer, for example aluminum, and the layer 411 may be a dielectric layer, for example SiO 2 oxide, or a layer of a passivation material such as a BCB polymer (Benzocyclobuthene) The conductive layer 409 may also be a copper layer formed by electroplating in a bath containing metal ions. could also be completely filled with a conductive material Figure 8A illustrates a variant of the step shown in Figure 7B1, during which a trench 401 'having inclined walls is etched, the via 40' obtained at the end of the process is illustrated in FIG EB (which is equivalent to Figure 7J) and has a substantially frustoconical shape.In summary, the method according to the invention provides for implanting the dielectric 402 which covers the wall of the via before having achieved the via itself, that is to say before having practiced the cavity 408 in the semiconductor. Moreover, the embodiment which has just been described as "method 3" is similar to both a "pre-process" or "mid-process" type process with respect to trench formation. 401 or 401 ', and a process of the "post-process" type with respect to the other steps, in particular the production of the cavity in the silicon. As already indicated, it follows that the dielectric material 402 which covers the wall of the via can be made in good conditions and in particular be deposited at an optimum temperature to obtain a high ratio between the thickness of the layer deposited on the walls of the trench 401 and the thickness of the layer deposited on the front face of the wafer 19

The dielectric material 402 also has good insulating properties and resistance to breakdown.The dielectric material 402 also has a satisfactory thickness that can be controlled at will by changing the width of the trench 401, and resists well to step of etching the dielectric layer 402 at the bottom of the cavity 408 (Fig. 7H) including whether an isotropic etching agent is used, if necessary, the width of the trench 401 may be chosen greater than what is necessary to hold The etching agent 402 is etched by etching agent 9A and 9B illustrate very schematically a technological characteristic of the trench 401 or 401 'when it is made by DRIE etching. of the trench a specific shape that looks, in section, to a stack of letters "C" forming a ripple, each "C" having its concave face e oriented towards the inside of the trench. As a result, when the trench is filled with the dielectric material 402 and the silicon has been removed in the closed perimeter delimited by the trench, the dielectric 402 which covers the wall of the via also has these specific undulations. As these undulations are seen from the inside of the via (sense of observation materialized by arrows in Figures 9A, 9B), the convex face these "C" is oriented towards the inside of the via. This specificity makes it possible to recognize a via made according to method 3 when the trench is made with a DRIE engraving machine. For example, in an electron microscope, in a via of a depth of 60 microns made in silicon, there are a hundred stacked "C" each having a width of the order of one tenth of a micrometer.

The method 3 which has just been described is only one example of implementation of the method according to the invention, the steps described and shown in the figures being capable of various alternative embodiments depending on the techniques, instruments and equipment used. by those skilled in the art wishing to implement the invention. Moreover, this method is applicable to various types of semiconductor wafers.

Furthermore, the process just described is essentially a collective realization of vias on the same chip or a collective realization vias of several chips on the same silicon wafer, before cutting the wafer and individualization of the chips. This operation of cutting the wafer in "dice" is called "singulation" and is generally performed with a diamond saw, following cutting lines 3 shown in dashed lines in Figure 1, forming a grid on the surface of the wafer. An application of the invention relates to the production of imagers on silicon whose rear face comprises conductive pads of the type shown in Figure 2B (ranges 5). By way of example, FIG. 10 represents an example of a CMOS imager 60 integrated in an image capture and / or video capture micromodule 50, intended for example to be mounted in a portable device such as a mobile phone, an camera or video camera. The module 50 comprises a frame 51, an optical block or lens holder block 52, an objective here comprising two lenses 53 mounted in the block 52 with a diaphragm 54, a protective transparent plate 55 in which is made for example an infrared filter, and a printed circuit board 56. The imager 60 is in the form of 21

chip or chip of silicon and is fixed with the transparent plate 55 in a cavity of the frame 51 having an opening, so as to receive the light passing through the lenses 53, the diaphragm 54 and the transparent plate 55. The rear face of the The imaging chip 60 has melt-soldered connection beads on conductive pads of the printed circuit board 56. The connection beads are electrically connected to an integrated circuit of the imager 60 via TSW vias made according to the method of the invention.

Claims (21)

A method of forming a via in a semiconductor wafer (1 "), characterized in that it comprises the steps of: i) trenching (401, 401 ') on a front face 5 of the wafer, the trench delimiting a closed perimeter, ii) filling the trench with a dielectric material (402), iii) thinning the wafer by abrasion and / or etching of its back face, until reaching at least the bottom of the trench, and iv) removing the semiconductor extending inside the closed perimeter delimited by the trench, so as to reveal a cavity (408) whose wall is coated with the dielectric material (402). 2. A method according to claim 1, comprising, prior to step iv), a step of forming on the front face of the wafer an electrically conductive pad (403) extending over the perimeter delimited by the trench and isolated from the semiconductor by at least a first dielectric layer (402). 25 The method of claim 2 comprising, after step iv), a step of etching the first dielectric layer (402) at the bottom of the cavity (408). 30 4. Method according to one of claims 1 to 3, comprising before step iv) the steps of: - depositing at least a second dielectric layer (407) on the rear face of the wafer, and 22 - etching the layer dielectric so as to create a window in the layer opposite the perimeter delimited by the trench. 5. Method according to one of claims 1 to 4, wherein the trench is made by dry etching of the semiconductor. 6. Method according to one of claims 1 to 5, wherein the trench is filled with a TEOS oxide deposited in the vapor phase subatmosphérique. 7. Method according to one of claims 1 to 6, wherein the trench is substantially ring-shaped. 8. A method according to one of claims 1 to 7, wherein the semiconductor extending within the perimeter defined by the trench is removed by dry etching. The method of one of claims 1 to 7, wherein the semiconductor extending within the perimeter defined by the trench is removed by selective wet etching. The method according to one of claims 1 to 9, comprising, after step iv), a step of completely filling the cavity (408) with an electrically conductive material. 11. The method according to one of claims 1 to 9, comprising, after step iv), a step of partially filling the cavity (408) by means of a layer (409) of an electrically conductive material. The method of one of claims 1 to 11, including a step of placing the semiconductor wafer (1 ") on a carrier (406) prior to thinning the wafer. 13. The method of claim 12, wherein the support is a glass plate. 14. A method of manufacturing integrated circuits on a semiconductor wafer, characterized in that it includes vias forming steps according to the method according to one of claims 1 to 13. The method of claim 14, wherein steps i) and ii) of the via forming method are conducted prior to or during the implementation of integrated circuit regions on the semiconductor wafer. 16. The method according to one of claims 14 and 15, wherein steps iii) and iv) of the method of formation of via are conducted after implantation of integrated circuit regions on the semiconductor wafer. 17. The method of claim 16, comprising a step of deposition and etching of at least one layer of conductive material (409) to form conductive tracks (410) and contact pads, the tracks ensuring the electrical connection between them. contact pads and vias. 18. The method according to one of claims 16 and 17, comprising a step of cutting the wafer to form individual chips. 19. Method according to one of claims 14 to 18, wherein the integrated circuits are CMOS imagers. An image capture micromodule (50) comprising a CMOS imager wafer (60) having an integrated circuit region connected to an interconnect medium (56) via vias made in accordance with the method of the present invention. one of claims 1 to 13. 21. Micromodule according to claim 20, wherein the vias of the CMOS imager wafer have an inner wall having stacked "C" shaped corrugations (412) whose convex portion is oriented towards the inside of the vias.