FR2920894B1 - Architecture de registre memoire a detection d'erreur integre et procede de detection d'erreur associe - Google Patents

Architecture de registre memoire a detection d'erreur integre et procede de detection d'erreur associe

Info

Publication number
FR2920894B1
FR2920894B1 FR0706355A FR0706355A FR2920894B1 FR 2920894 B1 FR2920894 B1 FR 2920894B1 FR 0706355 A FR0706355 A FR 0706355A FR 0706355 A FR0706355 A FR 0706355A FR 2920894 B1 FR2920894 B1 FR 2920894B1
Authority
FR
France
Prior art keywords
therefor
memory register
register architecture
error detection
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0706355A
Other languages
English (en)
Other versions
FR2920894A1 (fr
Inventor
Patrick Dervin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales SA
Original Assignee
Thales SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales SA filed Critical Thales SA
Priority to FR0706355A priority Critical patent/FR2920894B1/fr
Publication of FR2920894A1 publication Critical patent/FR2920894A1/fr
Application granted granted Critical
Publication of FR2920894B1 publication Critical patent/FR2920894B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
FR0706355A 2007-09-11 2007-09-11 Architecture de registre memoire a detection d'erreur integre et procede de detection d'erreur associe Active FR2920894B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR0706355A FR2920894B1 (fr) 2007-09-11 2007-09-11 Architecture de registre memoire a detection d'erreur integre et procede de detection d'erreur associe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0706355A FR2920894B1 (fr) 2007-09-11 2007-09-11 Architecture de registre memoire a detection d'erreur integre et procede de detection d'erreur associe

Publications (2)

Publication Number Publication Date
FR2920894A1 FR2920894A1 (fr) 2009-03-13
FR2920894B1 true FR2920894B1 (fr) 2011-09-09

Family

ID=39135136

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0706355A Active FR2920894B1 (fr) 2007-09-11 2007-09-11 Architecture de registre memoire a detection d'erreur integre et procede de detection d'erreur associe

Country Status (1)

Country Link
FR (1) FR2920894B1 (fr)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371963A (en) * 1980-12-24 1983-02-01 Ncr Corporation Method and apparatus for detecting and correcting errors in a memory
US5200962A (en) * 1988-11-03 1993-04-06 Racal-Datacom, Inc. Data compression with error correction
US5455939A (en) * 1992-06-17 1995-10-03 Intel Corporation Method and apparatus for error detection and correction of data transferred between a CPU and system memory
US6216251B1 (en) * 1999-04-30 2001-04-10 Motorola Inc On-chip error detection and correction system for an embedded non-volatile memory array and method of operation

Also Published As

Publication number Publication date
FR2920894A1 (fr) 2009-03-13

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