FR2916110A1 - Electronic multimode data shifting device for e.g. channel coding device, has control unit controlling multiplexers to deliver R input data on R number of predetermined outputs regardless of total value of desired shifting smaller than R - Google Patents

Abstract

The device (DDC) has multiplexers with elemental inputs respectively coupled to two inputs taken among n number of inputs (E1-EN) in a manner not shifting multimode data (W1-WN) presented on elemental inputs of a shifting elemental value depending on altitude of a shifting stage, and a shifting direction is identical for the multiplexers of a configurable shifting circuit. A control unit (MCI) controls the different multiplexers to deliver R input data on R number of predetermined outputs (S1-SN) regardless of total value of desired shifting smaller than R.

Description

, 13L, ... j CASE ALONGA & JOSSE Paris - Munich - Alicante - Grenoble

  INDUSTRIAL PROPERTY ADVICE EUROPEAN PATENT AND TRADEMARK ATTORNEYS 8, avenue Percier ù F 75008 PARIS Tel. : 33 (0) 1 45 61 94 64 Fax: 33 (0) 1 45 63 94 21 e-mail: paris@casalonga.com B06-3185EN ù FZ / EVH 06-GR1-134

  The so-called STMicroelectronics SA is an electronic multi-mode data offset device, in particular for coding / decoding with LDPC code. Invention of: Laurent PAUMIER Vincent HEINRICH Electronic multimode data offset device, in particular for coding / decoding with an LDPC code. The invention relates to data shifters which are in particular used for performing a cyclic permutation of the input data. Such devices are for example used in a non-limiting manner in channel coding devices including encoders using block-based codes whose parity matrix has a low density and more known to those skilled in the art under the name code LDPC (Low Density Parity Check), or in channel decoding devices including LDPC decoders, or in devices using turbo codes to perform part of the data interleaving.

  Such codes are proposed for many standards (802.11n, 802.16e, DVB-S2, ...). The emergence of these many standards requires hardware flexibility and reconfigurability of these data shifting devices.

  Conventional data offset devices are known to those skilled in the art under the name of barrel shifters (barrel shifters according to an English name commonly used by those skilled in the art). These barrel shift circuits are based on a logarithmic architecture of multiplexers and, when of size N (i.e. having N inputs and N outputs) they provide a simple solution for cyclic shifting of N data delivered at the input of the circuit by a bus of size N. On the other hand, when only a portion of the data bus is used, that is to say that when the barrel shift circuit is fed with a number of data less than N, the outputs of the barrel shift circuit, on which the shifted data is output, vary according to the desired offset value. In other words, the output wires actually used, that is to say conveying the offset output data, are not the same for a given bus size, as a function of the offset value. And this obviously poses a problem when one has to connect another circuit downstream of the barrel shift circuit. Also, we see immediately that these barrel shift circuits do not offer a satisfactory solution to the hardware flexibility and reconfigurability mentioned above and required to meet the emergence of different standards, except of course to use as many barrel shift circuits as there are bus sizes to consider, by means of an appropriate selection device, or a single barrel shift circuit having the maximum size with downstream a complex configurable wire routing device depending on the actual size of the input data bus. However, these two solutions have a significant surface encumbrance and / or complex routing problems. According to one embodiment there is provided an offset device for supporting any bus size from 1 to N thus providing a completely reconfigurable device. According to one aspect, there is provided an electronic offset device capable of shifting data of a desired offset global value, comprising N inputs capable of simultaneously receiving R input data, R being capable of taking all values from 1 to N. The device also comprises N outputs and a configurable shift circuit connected between the N inputs and the N outputs and having a cascade of shift stages.

  The number of stages depends on N and each stage comprises at least N controllable multiplexing means. Each multiplexing means of a stage has a first elementary input and a second elementary input respectively connected directly or indirectly, for example via one or more other multiplexing means, to a first input and a second input. taken from among the N inputs so as to, on command, not to shift a data present on said first elementary input and to shift a data present on the second elementary input of an elementary offset value which depends on the rank of the stage.

  Moreover, the direction of shift, shift to the right or shift to the left, is identical for all the multiplexing means of the circuit. The electronic offset device also comprises control means able to control the various multiplexing means so as to deliver the R input data to R predetermined outputs regardless of the overall value of offset desired that is less than R. According to a In one embodiment, the shift circuit comprises two parts, one of which can be related, from the point of view of the number of multiplexing means, to a conventional barrel shift circuit. On the other hand, from a connection point of view, it is in fact a modified barrel circuit since all the multiplexing means of this first part are connected so as to possibly always shift in the same direction. The shift circuit also comprises a second portion possibly comprising additional multiplexing means. As regards the control of the multiplexing means, this is more complex than for a conventional barrel shift circuit because the multiplexing means of a given shift stage are not necessarily controlled in the same way. Thus, according to one embodiment, the shift circuit is, as regards the control of the multiplexing means, divided virtually into two parts, which are not necessarily the same two parts mentioned above, the boundary between these two dependent parts of the value S + NR, where S is the desired global offset value. Thus, according to one embodiment, each shift stage comprises a first group of adjacent multiplexing means and a second group of adjacent multiplexing means, the number of multiplexing means in each group depending on the rank of the stage and the S + NR value where S denotes the desired global offset value, and the control means are able to independently control the two groups of multiplexing means of each stage, and identically all the multiplexing means of a group. one stage, so that the multiplexing means of all the first groups perform a total offset equal to s and the multiplexing means of all the second groups perform a total offset equal to S + NR. If the input data is coded on a single bit, each multiplexing means is in fact a multiplexer. On the other hand, if the input data is coded on several bits, each multiplexing means is a set of several multiplexers connected in parallel and respectively associated with the data bits. Each set of multiplexers is individually controllable and all the multiplexers of the same set are controlled identically. The shifting device may for example be in the form of an integrated circuit. According to another aspect, it is also proposed a channel coding device, in particular able to perform an encoding with an LDPC code, incorporating an offset device as defined above. According to another aspect, it is also proposed a channel decoding device, in particular capable of effecting a decoding of blocks encoded with an LDPC code, incorporating an offset device as defined above. Other advantages and characteristics of the invention will appear on examining the detailed description of embodiments, in no way limiting, and the appended drawings in which: FIG. 1 schematically illustrates an embodiment of an offset device of data ; FIG. 2 schematically illustrates a multiplexing means; - Figures 3 and 4 schematically illustrate more particularly an embodiment of a shift circuit incorporated in the data shifter of Figure 1; FIGS. 5 to 18 illustrate various embodiments and operations of a data shifting device; FIG. 19 schematically illustrates the internal structure of a communication chain, for example a wireless device, incorporating channel coding and decoding means, and; FIG. 20 illustrates in more detail but always schematically an embodiment of an LDPC decoder incorporating a data shifter. In FIG. 1, the reference DDC designates an electronic offset device comprising N inputs E 1 ù EN and N outputs S1-SN. The DDC device is adapted to receive Wi data from a BSE input bus, and to output data shifted on an output bus BS S. As will be seen in more detail below, the organization of these data able to be actually received at the input of the DDC device, can be different. Thus, for example, the device DDC can simultaneously receive N data W 1 -WN organized for example in a single group, or a group of data whose size can take any value greater than or equal to 1 and less than N. 25 In other words, the DDC device is here a multimode device in that it is capable of handling the case of a BSE bus of size N, that is to say simultaneously receiving R = N input data. or the case of bus of intermediate size, that is to say receive as input on the bus BSE a number R of data less than N and greater than or equal to 1. And, whatever the organization of In the input data, the DDC device will output the offset output data to predetermined outputs of the DDC device, regardless of the overall offset value considered compatible with the organization of the input data. Thus, an example of an overall S offset value compatible with an input organization is an offset value S less than the size R of the received data group. The shift device DDC also comprises control means MC1 able to control the various multiplexing means so as to output the R input data to R predetermined outputs regardless of the overall value of offset S that is smaller than R. More particularly, each multiplexer MUX comprises a first elementary input EM1 and a second elementary input EM2, as well as an output SM. According to the value of the control signal cde; delivered by the control means MC1, the first elementary input EM1 or the second elementary input EM2 will actually be connected to the output SM.

  When the first elementary input EM1 is connected to the output SM, the multiplexer MUX is in a first state ETT1 in which, as will be seen in more detail below, it does not shift a data present on said first input EM1. On the other hand, when the second elementary input EM2 is effectively connected to the output SM, the multiplexer MUX is in a second state ETT2 in which it shifts a data present on this second elementary input of an elementary offset value which depends on the rank of the offset stage of the shift circuit.

  Reference will now be made more particularly to FIGS. 3 to 16 in order to describe in greater detail a first variant embodiment more particularly concerning a DDC shifter capable of shifting the data to the left. In the examples described here, for a given group of R (R less than or equal to N and greater than or equal to 1) arriving at the R inputs E1 to ER of the DDC shifter, the predetermined R outputs on which the data will be output. offset, regardless of the global offset value S desired, are the R outputs of rank 1 to R referenced S1 to SR.

  As seen more particularly in FIGS. 3 and 4, the CDC shift circuit comprises a first portion PTA having a regular architecture and a second part PTB. The CDC shift circuit comprises a cascade of AND shift stages; whose number is a function of N. More particularly, the number of shift stages is equal to ceil (log2 (N)), where ce (X) denotes the upper integer function of X. In the PTA part of the circuit to CDC shift to regular architecture, each shift stage has N multiplexers MUX.

  Furthermore, a shifting stage of rank i in the cascade comprises an additional number of multiplexers arranged in the PTB part. This number may be zero and it depends generally on rank i of the stage as well as the number N. More precisely, each shift stage thus has a total of a number of multiplexers equal to N + 2i.floor N -21- -1) / 2i, where floor (X) denotes the lower integer function of X and i denotes the rank of the stage, the first stage being the stage of rank i equal to 1. All these multiplexers are able to shift in the same direction of shift (here on the left).

  It thus emerges from this formula and from the number of shifting stages that the last stage of the cascade comprises only N multiplexers, that is to say that this last shifting stage does not include any additional multiplexer arranged in the PTB part. .

  Moreover, as seen more particularly in FIG. 3, among the N inputs El-EN of the DDC device, N-1 inputs are in fact split. These are the N-1 entries of rank 2 to N. Only the first entry of rank 1, referenced El, is not split. In other words, if one places oneself at the level of the CDC shift circuit, the latter comprises, at the level of the PTA part, N inputs which can be described here as intermediate inputs, and referenced Ela-ENa. . These N intermediate inputs correspond to N inputs El-EN. The N-1 intermediate inputs E2b-ENb which correspond virtually to the inputs of the second PTB part of the CDC circuit are at least for some of them respectively connected to the N-1 corresponding inputs E2a-ENa, and therefore to the N1 inputs E2 -IN. This is the reason why we speak of a splitting of the N-1 inputs E2-EN while only the entry of rank 1, that is to say the input E l is not split. In fact, as will be seen in more detail below, and especially on particular examples, for the first stage and if we consider only the first portion PTA, only the entry of rank N, EN, is split.

  For the tier 2 stage and considering only the first PTA part, the first two entries from the left, ie the EN and EN-1 entries of rank N and N-1 are split. More generally, for the stage of rank i and if we consider only the first part PTA, the first 21- 1 entries from the left are split, that is to say they are connected to two multiplexers of different ranks of this stage of rank i. Moreover, since the size of the BSE bus can take all the values between 1 and N, each of the N input data has the possibility of being present on each of the N outputs S1-SN.

  Thus, in the present case, the data present on the input ENa can only be present on the output SN. So, this data which is also present on the input ENb must be able to be present on the outputs S1, S2, ..., SN-1. Therefore, the input data present on the input ENb must be able to be shifted to the left by an offset value equal to 1, 2, 3, ..., or N-1. Similarly, given the offset direction, the data present on the EN-la input can only be present on the SN or SN-1 outputs. Therefore, this data also present on the input EN-lb must be able to be present on the outputs S1, S2, ..., SN-2. Therefore, the data present on the input EN- lb must be shifted to the left by an offset value of 2, 3, ..., or N-1. The data present on the input E3a can be present on one of the outputs S3 to SN. Thus, the data present on the input E3b must be present on the output S1 or S2. Therefore, the data present on the input E3b must be shifted to the left of N-2 or N-1. Finally, the data present on the input E2a may be present on any of the outputs S2 to SN. Thus, the data present on the input E2b must be present on the output S1. Therefore, the data present on this input E2b must be shifted to the left of N-1. More generally, the data present on the input Ejb must be shifted to the left of N-1, N-2, ..., or N-j + 1.

  The architecture of the CDC shift circuit comprising the first part PTA and the second part PTB makes it possible to realize these various offsets as will now be explained in more detail on more particular examples of embodiment. As indicated above, whatever the part of the CDC shift circuit, all the MUX multiplexers are able to shift data always in the same direction of shift, here on the left. In other words, the second elementary input EM2 of a multiplexer of rank r is always connected, directly or indirectly via at least one other multiplexer, to an input Eq of rank q different from the rank of the multiplexer , for example of lower rank. In other words, this is shown graphically in FIGS. 4 to 12 which show offsets on the left, by an oblique connection to the right of the second elementary inputs of all the multiplexers MUX. Furthermore, each multiplexer of a shift stage of rank i is able to shift via the second elementary input, a piece of data of an elementary offset value which is identical for all the multiplexers of this stage. This elementary offset value is equal to 2'- 'for a stage of rank i, the first stage being the stage of rank i equal to 1. Moreover, as explained above in different terms, the second elementary inputs of all the multiplexers of an offset stage are respectively connected directly or indirectly to inputs of consecutive ranks, it being understood that the rank N is considered to be consecutive to the rank 1. This is illustrated on the embodiments of FIGS. 12.

  In these figures, for purposes of simplification, the inputs El-EN and the outputs S1-SN are represented only by the number of their rank 1 to N. Thus, in FIG. 5, which illustrates the case N = 3, the second elementary inputs of the multiplexers of ranks 3, 2 and 1 of the stage ET1 are respectively linked to the inputs of consecutive ranks 2, 1 and 3. Similarly, the second elementary inputs of the multiplexers of ranks 3, 2 and 1 of the second stage ET2 are respectively connected to the entries of consecutive ranks 1, 3 and 2.

  In the case of Figure 6, the DDC device is a device provided for N = 4. The second elementary inputs of the adjacent multiplexers of the stage ET1 (part PTA and part PTB) are respectively connected to the inputs of consecutive ranks 3, 2, 1, 4, 3, 2. The second elementary inputs of the four multiplexers of the part PTA the last stage ET2 are respectively connected indirectly to the inputs of consecutive ranks 2, 1, 4, 3. The same principle is found in FIGS. 7 to 12 which respectively illustrate DDC shifters for values of N = 5, 6, 7, 10, 11 and 13.

  Moreover, as can be seen in these figures, only one of the N inputs is directly connected to two different multiplexers while each of the other N-1 successive row inputs is directly connected to at least three different multiplexers so that data present on one of these N-1 other inputs can be shifted in said offset direction of any global offset value smaller than N and compatible with the rank of said input. More specifically, in the examples described here, these N-1 other inputs are the inputs of ranks 2 to N and each of these inputs is directly connected to at least three different multiplexers so that a data present on one of these inputs can be shifted in the offset direction of any global offset value between N-1 and N-r + 1, where r denotes the rank of said input. In these examples, the only input that is directly connected to two different multiplexers is the Tier 1 input. Referring back to the examples now, for example in Figure 9, which illustrates the N = 7 case. , the row 2 input connected to the PTB part must be shifted to the left by an offset value equal to 6. Therefore, since the second stage ET2 shifts by an elementary offset value equal to 2 and that the third stage ET3 shifts by an elementary offset value equal to 4, it is necessary here to insert a multiplexer m5 at the stage ET2 whose first elementary input is connected indirectly via the multiplexer ml to l 4-rank input and whose second elementary input is connected to the input of rank 2. The output of this multiplexer m5 is connected to the second elementary input of the multiplexer of rank 1 of the stage ET3. The Tier 3 data at the PTB part must be offset by an offset value equal to 6 or 5. Since 5 is an odd value, an elementary offset of 1 is required at the level of the first stage. where the presence of the multiplexer ml whose first elementary input is connected to the input of rank 4 and whose second elementary input is connected to the input of rank 3. An elementary offset of 2 is also required to perform the global shift of 6, which requires the presence of the m6 multiplexer at the second stage ET2. The input of rank 4 must be offset by a global offset value equal to 6, 5 or 4. A global offset value equal to 4 is obtained through the multiplexers of the PTA portion of the CDC circuit. On the other hand, to reach an overall offset value of 5 or 6, an elementary shift of 1 or 2 is required. This is why it is planned here to insert additional multiplexers m2 and m7 respectively to the first stage ET1 and the second stage ET2.

  The same reasoning continues for the other inputs, which effectively leads to the architecture illustrated in FIG. 9. More generally, in the examples described here for a shift to the left, the first elementary inputs of the N multiplexers of FIG. Rank 1 to N of a row of rank i are respectively connected directly or indirectly to the N inputs of rank 1 to N. The second elementary input of the row 1 multiplexer of rank 1 (that is to say the first floor) is connected to the entry of rank N.

  The first and second elementary inputs of the possible other multiplexing means of the stage of rank i, that is to say the possible multiplexers of the PTB part, are connected directly or indirectly to at least some of the inputs of rank N to 2 given the elementary offset value associated with this stage.

  The second elementary inputs of some of the N multiplexers of the last stage are also connected directly or indirectly to the inputs of rank N to 2 taking into account the elementary offset value associated with this stage. The control of the multiplexers of the different stages is illustrated on two particular examples (Figures 13 and 14 on the one hand, Figures 15 and 16 on the other hand). In fact, as seen in these figures, and in particular in FIGS. 13 and 15, the graph of the CDC shift circuit is divided into two parts PT1 and PT2, which depend on the value S + NR where S denotes the global value offset, and R the actual number of data received on the BSE bus, that is to say the effective size of the BSE bus. The multiplexers of the first part PT1 carry out a total shift of S while the multiplexers of the part PT2 make a total shift of S + N-R. The first part PT1 comprises at each shift stage a first group of adjacent multiplexers. The second part PT2 comprises at each stage a second group of adjacent multiplexers.

  The control means MC 1 independently controls the two groups of multiplexers of each stage and identically all the multiplexers of a group of one stage, so as to obtain the total offsets mentioned above.

  The number of multiplexers of the first group (i.e., belonging to the first part PT1) of a stage of rank i is equal to min (MX, N- (mod (S + NR, 2 ') - ( NR))) where mod (X, Y) denotes the remainder of the division of X by Y, min denotes the minimum function, and MX denotes the number of multiplexers of the tier of rank i.

  More particularly, in the case of FIGS. 13 and 14, N is equal to 6, R is equal to 4 and S is equal to 3. In these figures, a logic control signal equal to 1 means that a multiplexer is in its ETT2 offset state, while a logic control signal equal to 0 means that a multiplexer is in its non-offset state ETT1. Therefore, the number of stages is equal to 3 and the first part PT1 of the first stage ET1 has seven multiplexers. Since, moreover, the stage ET1 comprises in total ten multiplexers, the part PT2 comprises for this stage ET1 three multiplexers. All six multiplexers of stage ET2 belong to part PT1. Finally, the part PT1 of the stage ET3 comprises three multiplexers as well as the part PT2.

  The multiplexers of the part PT1 must carry out a total shift equal to 3. Therefore, as the elementary shift made by the multiplexers of the stage ET1 is equal to 1 that that made by the multiplexers of the stage ET2 is equal to 2 it is the multiplexers of the part PT1 of the stages ET1 and ET2 which are controlled to be in their state ETT2, that is to say in their state of shift, while the multiplexers of the part PT1 of the stage ET3 are ordered to be in their state ETT1, that is to say in their state where they do not shift the data. The multiplexers of the part PT2 must globally carry out an offset equal to 3 + 6-4, that is to say 5. This global shift of 5 is obtained by an elementary shift of 1 (multiplexers of the PT2 part of the ET1 stage) and by an elementary shift of 4 obtained by means of the multiplexers of the PT2 part of the stage ET3. The configuration of the multiplexers is illustrated in bold in Figure 14. Of course, since in the example mentioned here the data are output on the outputs of the rows 1 to R, that is to say on the outputs S1 at S4, the data path W2, W3 and W4 via the multiplexers MUXa of Fig. 14 is unimportant.

  In FIG. 15, N is equal to 6, R is equal to 5 and S is equal to 1. As a consequence, the first stage ET1 has in its part PT1 seven multiplexers (i group) and in its part PT2 three multiplexers (second group). The stage ET2 comprises in its part PT1 five multiplexers and in its part PT2 a multiplexer. It is the same for stage ET3. The global offset performed by the multiplexers of the part PT1 is equal to 1, which is obtained only by the multiplexers of the first stage.

  The global offset performed by the multiplexers of the part PT2 is equal to 2, which is obtained only by the multiplexer of the part PT2 of the stage ET2. The data path W1-W5 is accordingly illustrated in bold in Fig. 16.

  Materially, the control means MC1 can be easily made from gates and / or logic circuits according to the values of S, Net R. All that has just been described also applies to a shifting device capable of to make a shift to the right as illustrated for example in two particular cases in Figures 17 and 18. In fact, as seen in these examples, the structure of such a DDC device capable of performing a shift to the right has a symmetrical architecture compared to that illustrated in the previous figures.

  And, in the case of a shift to the right, the first elementary inputs of the N multiplexers of rank 1 to N are again connected respectively directly or indirectly to the N inputs of rank 1 to N. The second elementary input of the multiplexer of rank 1 is always connected to the input of rank N. In addition to these two figures, the R predetermined outputs are the outputs of rank 1 to R (which are this time the R outputs left in these figures). In all that has been described above, it has been assumed that the data is coded on a single bit. However, the invention also applies to data coded in a more general manner on several bits. In this case, if the data is coded on a number nbit, each multiplexer MUX is in fact replaced by a set of nbit multiplexers in parallel and each connected identically. The arrangement and the configuration as well as the control of the different multiplexers of the shift circuit depend not only on the number of intermediate sizes that can be processed, that is to say on the number N, but also on the choice of inputs on which the R input data and the choice of R predetermined outputs of the shifter are received. Indeed, it is quite possible to consider outputting the R data for an intermediate size smaller than N on R outputs certainly predetermined regardless of the desired overall offset value, but different outputs S1 to SR. In the same way, the R input data can be made on R different inputs from the inputs E 1 to ER. The person skilled in the art will therefore be able to configure the shift circuit on a case-by-case basis and connect it between the N inputs and the N outputs as a function of the application envisaged, provided, of course, with the general principles mentioned above and relating to the number of offset stages, the number of multiplexers per shift stage, in the same offset direction for all the multiplexers as well as a control of the multiplexers per group according to a suitable division.

  The invention can find an interesting application in the context of systems operating according to wireless transmission standards, such as for example the IEEE 802.16e standard intended for the systems designated under the name Fixed and Mobile Broadband Wireless Access Systems or the standard. IEEE 802.1 ln concerning the networks designated under the name Anglo-Saxon Local and Metropolitan Networks. We can also mention the DVB-S2 standard, especially for satellite transmissions.

  Such systems use channel coding and decoding means which may advantageously incorporate shifters as described above. More specifically, in Fig. 19, the WAP reference designates a wireless apparatus for use in a communication system according to the DVB-S2 standard. The wireless device WAP comprises a TXCH transmission chain capable of transmitting on a transmission channel CH, for example air, coded and modulated information. On the other hand, this WAP apparatus also has an RXCH receive string capable of receiving and decoding information from the CH transmission channel. The TXCH transmission chain comprises, in a conventional and well-known manner, SCM source coding means receiving APP application data, in particular for compressing them so as to reduce the data rate. The transmission chain also comprises channel coding means whose function is in particular to add redundancy so as to subsequently correct the potential errors in reception due to the noise of the transmission channel. These channel coding means comprise, for example, LDPC coding means. The transmission chain also comprises MDM modulation means so as to adapt the signal to the transmission channel (satellite channel or radio channel, for example). The RXCH receive chain comprises counterpart means 35 performing inverse functions. More precisely, there are DMDM demodulation means, followed by CHDCM channel decoding means comprising for example an LDPC decoder, followed by SDCM source decoding means delivering to the user the DUT user data corresponding to the data of the user. APP application.

  The LDPC code is a block-based code. The encoder processes blocks of K bits and delivers blocks of N bits. Thus, N-K redundancy bits are added. These N-K bits are called parity bits. The coding rate (Code rate, in English) is defined by the ratio K / N. The lower the coding rate, the higher the number of redundancy bits and the greater the noise protection of the transmission channel. These N-K bits are calculated using a parity matrix H. The LDPC code is therefore also a code based on a matrix. This matrix has N-K rows and N columns and is composed of 1 and 0 with a number of 1 low relative to the number of 0's. This is the reason why such codes based on such a matrix are referred to as LDPC codes, i.e., low density codes. The N-bit BLC encoded block is calculated by solving the equation HBLCT = 0, where H is the parity matrix, and T is the transposed function. On the decoder side, the correction of the erroneous bits is performed from the relationships between the coded information of the block. These relations are given by the parity matrix H. The decoder uses internal metrics corresponding to the 1 of the matrix H. The matrix H corresponds to the Tanner graph of the LDPC code comprising so-called control nodes (check nodes) and nodes of information (bit nodes) interconnected by the path of the graphs representative of the messages exchanged iteratively between the nodes thus connected. These metrics are updated by rows (update of the control nodes) taking into account the internal metrics of the same line. Then, the decoder updates these metrics by columns (updating of the information nodes) taking into account the internal metrics on the same column as well as the corresponding information input decoder and from the transmission channel. An iteration is the update of the control nodes for all internal metrics followed by the update of the information nodes for all internal metrics. Decoding a block requires several iterations. The values of the decoded bits, also called hard decisions, are obtained by adding the internal metrics by columns with the information received and taking the sign of the result. In other words, the sign of the result gives the value 0 or 1 of the bit while the absolute value of the result gives a confidence indication (probability) for this logical value 0 or 1. The codes of the LDPC type are of interest because they make it possible to obtain a very low Bit Error Rate (BER) because of the iterative nature of the decoding algorithm. Several iterative decoding algorithms exist to decode LDPC codes. It will be possible to mention the conventional algorithm known as propagation of belief and well known to those skilled in the art under the Anglo-Saxon name Belief Propagation (BP). Referring now more particularly to FIG. 20, it can be seen that an example of an LDPC decoder, referenced DEC, essentially and schematically comprises MMCH input memory means, MDCD decoding means, memory means MMHD output as well as MCTL control means. The MMCH input memory means receive a succession of BLC blocks; encoded with LDPC code. Each block has a predetermined number of coded information, 64 800 in the DVB-S2 standard. This information is in fact probability ratios and is generally known to those skilled in the art under their Anglo-Saxon LLR (Log Likelihood Ratio) name. This information is encoded on n bits. The sign of each piece of information is representative of its logical value while its absolute value is representative of the confidence that the logical value of this piece of information is the correct one. Each block received BLC; is decoded in the MDCD decoding means comprising in this example F processors operating in parallel, F being equal to 360 in a DVB-S2 standard application.

  The battery of F processors updates the control nodes and the information nodes. A MMT metric store contains internal metrics (in a number equal to the number of 1 in the parity matrix).

  A DDC shifter such as that described above makes it possible to place the right data in front of the right processors. During iterative decoding, the channel information, initialized by the information of the block to be decoded, is updated using the updated metrics.

  Finally, at the end of the decoding, the processors deliver in the memory MMHD, the hard decisions corresponding to the decoded logical values of the block BLC; These hard decisions are actually the signs of channel information updated at the last iteration. The use of a DDC shifter as described above, whether within the channel coding means or channel decoding means, makes it possible to reduce the number of multiplexers. By way of example, in the 802.11n standard, the bus sizes to be able to be processed are equal to 81, 54 and 27. The use of a conventional barrel shift circuit of size 81 leads to to a number of multiplexers equal to 3402 with 6-bit coded data. A 54-size barrel shift circuit has 1944 multiplexers. A barrel shift circuit of size 27 has 810 multiplexers.

  Accordingly, an option of providing three conventional barrel shift circuits having a size of 81, 54 and 27 respectively to support the three sizes required by 802.1 ln results in a total number of multiplexers equal to 6156 at which it must be added a selection circuit.

  On the other hand, a data shift device according to an embodiment of the invention having a maximum size equal to 81 and capable of processing all sizes from 1 to 81 results in a total number of 5526 multiplexers (with coded data on 6 bits).

  With regard to the 802.16e standard, the number of modes is much greater, typically equal to 19. More precisely, the size of the data bus can vary from 24 to 96. And, as an indication, with data coded on 6 bits, the size of a standard barrel circuit of size 96 thus able to cover only one mode namely the maximum mode, has a total number of multiplexers equal to 4032. For comparison, a device of data offset such as that described above and that would be able to cover all sizes from 1 to 96 and therefore all possible modes of the 802.16e standard would have a number of multiplexers equal to 6540, just slightly more 1.6 times the number of multiplexers of the conventional barrel circuit processing only the size 96.

Claims (14)

  1. Electronic shifting device capable of shifting data of a desired offset global value, characterized in that it comprises N inputs able to simultaneously receive R input data, R being capable of taking all the values of 1 at N, N outputs, a configurable shift circuit (CDC) connected between the N inputs and the N outputs comprising a cascade of shift stages (ETi), the number of stages being a function of N, each stage comprising at least N controllable multiplexing means (MUX), each multiplexing means of a stage having a first elementary input (EM1) and a second elementary input (EM2) respectively directly or indirectly connected to a first input and a second input taken from among the N inputs (Ei) so, on command, do not shift a data present on said first elementary input and shift data present on the two elementary input of an elementary shift value depending on the rank of the stage, the offset direction being identical for all the multiplexing means of the circuit, and control means (MC1) able to control the various means of multiplexing the to deliver the R input data to R predetermined outputs regardless of the overall desired offset value less than R.   2. Device according to claim 1, wherein the number of shift stages (ETi) is equal to ceil (log2 (N)), where ceil (X) denotes the upper integer function of X.   3. Device according to claim 1 or 2, wherein each shift stage (ETi) comprises a number of multiplexing means equal to N + 2'.floor ((N-2 '-'-1) / 2')) , where floor (X) denotes the lower integer function of X and i denotes the rank of the stage, the first stage being the rank tier i equal to 1.   4. Device according to one of the preceding claims, wherein only one (El) N inputs is directly connected to two different multiplexing means while each of the N-1 other inputs of successive ranks is directly connected to at least three means of multiplexing so that a data present on one of these N-1 other inputs can be shifted in said offset direction of any global offset value less than N and compatible with the rank of said input.   5. Device according to claim 4, wherein the N-1 other inputs are the inputs of rank 2 to N and each of these inputs is directly connected to at least three different means of multiplexing so that a data present on one of these inputs can be shifted in said offset direction from any global offset value between N-1 and N-r + 1, where r denotes the rank of said input.   6. Device according to one of the preceding claims, wherein the elementary offset value of a stage of rank i is identical for all the multiplexing means of the stage and is equal to 2'- 'the first stage being the l stage of rank i equal to 1, and the second elementary inputs of all the multiplexing means (MUX) of a stage are respectively connected directly or indirectly to entries of consecutive ranks.   7. Device according to one of the preceding claims, wherein the last stage has only N multiplexing means (MUX).   8. Device according to claims 6 and 7, wherein the first elementary inputs of the N multiplexing means of ranks 1 to N of a stage of rank i are respectively connected directly or indirectly to the N entries of ranks 1 to N, the second elementary input of the rank 1 multiplexing means of the rank i stage equal to 1 is connected to the rank N input, the first and second elementary inputs of any other multiplexing means of the rank i stage are connected directly or indirectly to at least some of the inputs of rank N to 2 taking into account the elementary offset value associated with this stage, and the second elementary inputs of some of the N multiplexing means of the last stage are also connected directly or indirectly to the inputs of rank N to 2 given the elementary offset value associated with this stage.   9. Device according to one of the preceding claims, wherein each shift stage comprises a first group of adjacent multiplexing means (PT1) and a second group of adjacent multiplexing means (PT2), the number of multiplexing means in each group depending on the rank of the stage and the value S + NR where S denotes the desired global offset value, and the control means are able to independently control the two groups of multiplexing means of each stage, and identical to all the multiplexing means of a group of one stage, so that the multiplexing means of all the first groups perform an offset equal to s and the multiplexing means of all the second groups perform an offset equal to S + NR.   10. Device according to claim 9, wherein the number of multiplexing means of the first group of a stage of rank i is equal to min (MX, N- (mod (S + NR, 2 ') - (NR)) where mod (X, Y) represents the remainder of the division of X by Y, min represents the minimum function, and MX the number of multiplexing means of the tier of rank i.   11. Device according to one of the preceding claims, wherein the offset direction is left or right.   12. Device according to one of the preceding claims, realized in the form of an integrated circuit.   13. A channel coding device, in particular adapted to perform an encoding with an LDPC code, characterized in that it incorporates an offset device (DDC) according to one of the preceding claims.   14. A channel decoding device, in particular adapted to perform a decoding of blocks encoded with an LDPC code, characterized in that it incorporates an offset device (DDC) according to one of claims 1 to 12.