FR2900521B1 - METHOD OF ANALYSIS IN A RECEIVER OF BITTER DATA FRAMES ISSUED BY A TRANSMITTER - Google Patents

METHOD OF ANALYSIS IN A RECEIVER OF BITTER DATA FRAMES ISSUED BY A TRANSMITTER

Info

Publication number
FR2900521B1
FR2900521B1 FR0603832A FR0603832A FR2900521B1 FR 2900521 B1 FR2900521 B1 FR 2900521B1 FR 0603832 A FR0603832 A FR 0603832A FR 0603832 A FR0603832 A FR 0603832A FR 2900521 B1 FR2900521 B1 FR 2900521B1
Authority
FR
France
Prior art keywords
bitter
transmitter
receiver
analysis
data frames
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0603832A
Other languages
French (fr)
Other versions
FR2900521A1 (en
Inventor
Philippe Alarcon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CS Systemes dInformation SA
Original Assignee
CS Systemes dInformation SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CS Systemes dInformation SA filed Critical CS Systemes dInformation SA
Priority to FR0603832A priority Critical patent/FR2900521B1/en
Priority to PCT/FR2007/000714 priority patent/WO2007125202A1/en
Publication of FR2900521A1 publication Critical patent/FR2900521A1/en
Application granted granted Critical
Publication of FR2900521B1 publication Critical patent/FR2900521B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/06—Code representation, e.g. transition, for a given bit cell depending only on the information in that bit cell
    • H03M5/12—Biphase level code, e.g. split phase code, Manchester code; Biphase space or mark code, e.g. double frequency code
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
FR0603832A 2006-04-28 2006-04-28 METHOD OF ANALYSIS IN A RECEIVER OF BITTER DATA FRAMES ISSUED BY A TRANSMITTER Expired - Fee Related FR2900521B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0603832A FR2900521B1 (en) 2006-04-28 2006-04-28 METHOD OF ANALYSIS IN A RECEIVER OF BITTER DATA FRAMES ISSUED BY A TRANSMITTER
PCT/FR2007/000714 WO2007125202A1 (en) 2006-04-28 2007-04-26 Analyzing method in a frame receiver of binary data transmitted by a transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0603832A FR2900521B1 (en) 2006-04-28 2006-04-28 METHOD OF ANALYSIS IN A RECEIVER OF BITTER DATA FRAMES ISSUED BY A TRANSMITTER

Publications (2)

Publication Number Publication Date
FR2900521A1 FR2900521A1 (en) 2007-11-02
FR2900521B1 true FR2900521B1 (en) 2008-07-11

Family

ID=37487554

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0603832A Expired - Fee Related FR2900521B1 (en) 2006-04-28 2006-04-28 METHOD OF ANALYSIS IN A RECEIVER OF BITTER DATA FRAMES ISSUED BY A TRANSMITTER

Country Status (2)

Country Link
FR (1) FR2900521B1 (en)
WO (1) WO2007125202A1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2243269B (en) * 1990-04-19 1994-04-13 British Broadcasting Corp Decoding binary-coded transmissions
DE10148891A1 (en) * 2001-10-05 2003-04-24 Infineon Technologies Ag Evaluation circuit for digitally encoded signal, has shifter which switches between upper and lower threshold values used in comparator

Also Published As

Publication number Publication date
WO2007125202A1 (en) 2007-11-08
FR2900521A1 (en) 2007-11-02

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Year of fee payment: 10

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Effective date: 20161230