FR2897226A1 - DEVICE FOR MEASURING PARAMETERS RELATING TO TEMPORAL STAMPLES NOTABLY PRESENTED IN STREAMS, AND FREQUENCY SYNTHESIZER - Google Patents

Abstract

The invention relates to a device for measuring parameters relating to time stamps. The device comprises a comparator delivering the difference between the time stamps and estimated time stamps, a loop filter filtering the result delivered by the comparator, a frequency synthesizer delivering a clock signal, controlled by the signal received from the filter. loop, a counter generating teriporal pads estimated from the signal delivered by the frequency synthesizer, said estimated time stamps being sent to the comparator, means for measuring parameters relating to time stamps. The clock signal comprises pulses spaced a regular duration. The synthesizer modifies the frequency of the clock signal by introducing a delay of a fixed duration between two pulses or by decreasing by an advance equal to a fixed duration, the interval between two pulses. The time between two updates of the frequency of the clock signal is a function of the signal received from the loop filter. The invention also relates to a frequency synthesizer. In particular, the invention applies to a device for measuring the parameters relating to the time stamps present in the MPEG-2 streams for the evaluation of the quality of service. The invention also relates to a frequency synthesizer.

Description

Device for measuring parameters relating to time stamps

  notably present in streams, and frequency synthesizer. The invention relates to a device for measuring parameters relating to time stamps present in streams. In particular, the invention applies to a device for measuring the parameters relating to the time stamps present in the MPEG-2 or MPEG-4 streams for the evaluation of the quality of service. The invention also relates to a synthesizer of. frequency.

  In the context of digital television, in particular for the digital video broadcasting standard or Digital Video Broadcasting, programs including in particular audiovisual data are broadcast in transport streams (or according to the expression Anglo-Saxon Transport Stream) in MPEG-2 format. MPEG-2 transport streams, in addition to audio and video data, include time information such as timestamps, or the English expression Program Clock Reference. The timestamps also make it possible to accurately restore the clock of the MPEG-2 encoder which compressed the audiovisual data of a program. The digital TV quality of service measurement recommendations described in ETSI TR101290 present various methods and devices for measuring time stamp parameters. To do this, the recommendations suggest for measuring the parameters relating to time stamps the use of a phase-locked loop (or phase-locked loop) including a voltage-controlled oscillator (or according to the English expression Voltage Control Oscillator). Or a transport stream includes several programs possibly generated by several different MPEG-2 encoders. Thus, for each program whose time stamp parameters are to be measured and the clock reconstructed, it is necessary to use a voltage controlled oscillator. A transport stream comprising several programs, the use of voltage controlled oscillators is therefore expensive and complex to implement.

  The purpose of the invention is in particular to overcome the aforementioned drawbacks. To this end, the subject of the invention is a device for measuring parameters relating to time stamps, receiving as input at least one data stream comprising time stamps. The device comprises - a comparator delivering the difference between the time stamps and estimated time stamps; a loop filter filtering the result delivered by the comparator; a frequency synthesizer delivering a clock signal, controlled by the signal received from the loop filter, a counter generating time stamps estimated from the signal delivered by the frequency synthesizer, said estimated time stamps being sent to the comparator ; means for measuring parameters relating to time stamps. The clock signal comprises pulses spaced a regular duration Tnom. The synthesizer modifies the frequency of the clock signal by: introducing a delay of a fixed duration between two pulses; or by decreasing by an advance equal to a fixed duration, the interval between two pulses. The time between two updates of the frequency of the clock signal is a function of the signal received from the loop filter.

  In one embodiment, the frequency synthesizer is associated with at least one of the following devices: a frequency offset measuring device; a device for measuring the frequency drift; a device for measuring the overall jitter; a device for measuring inaccuracies. The loop filter may be Proportional-Integral type, outputting an input signal. Since the error signal (ERR) is delivered by the comparator (20), G1 being a proportional term and G2 being an integral term, the transfer function of said loop filter can then be expressed by the following formula: IN SYNTH ( z) _ G G2 ERR (z) '+ 1u z-' Between two successive time stamps, the clock signal (Fr) comprises for example: - Nnom periods of duration Tnom and Nnom + aT periods of duration Tnom + bT or Nnom -TT periods of duration Tnom û i5T. The average period T is then expressed by the following formula: ## EQU1 ## Advantageously, the data streams are MPEG-2 or MPEG-4 streams.

  The subject of the invention is also a frequency synthesizer controlled by an input signal. It comprises: a block delivering the absolute value of the input signal IN_SYNTH (n) on an output Abs, a signal S indicating whether the input signal IN SYNTH (n) is negative, a signal Z indicating whether the signal of input IN_SYNTH (n) is null; a divider generating a signal corresponding to the division of the signal representing a constant fixed to a given value CST by the signal sent on the output Abs of the block; a register storing the signal generated by the divider and outputting the previously stored signal; a counter delivering a signal on a CNT output OUT corresponding to the number of pulses received from an oscillator, the counter having a reset input enabling it to be reset; a comparator comparing the signal delivered by the register with the output signal of the counter and outputting B> = A a signal corresponding to the result; a finite state machine using the S, Z signals indicating whether the input signal IN_SYNTH (n) is negative or zero of the block for generating a clock signal Fr, the finite state machine being phase shifted on the signal of clock Fr when it receives the signal delivered by the comparator on its input DIV. In one embodiment, the comparator, the counter and the finite state machine are synchronized by the oscillator delivering a signal whose frequency rn.Fnom is equal to the product of an integer m with the center frequency Fnom of the signal of In a particular embodiment, the frequency of the signal delivered by the oscillator is substantially equal to four times the central frequency Fnom. The clock signal Fr delivered by finite state machine has a

  equal period: 3 to Ti = 4 * Fnom if the input S of the state machine indicates that the input signal IN_SYNTH (n) is negative and the input DIV of the finite state machine corresponds to case where the condition B> = A of the comparator is verified; either at T4 = 1 if the input Z of the finite state machine indicates that the Fnom input signal IN_SYNTH (n) is zero or that the input DIV of the finite state machine corresponds to the case where condition B > = A of the comparator (53) is not checked; either at TS = 5 if the input S of the finite state machine indicating that 4 * Fnom the input signal IN_SYNTH (n) is positive and that the input DIV of the finite state machine corresponds to the case where the condition B> = A of the comparator is checked. The frequency synthesizer may comprise a Proportional-Integral type loop filter, said loop filter generating the input signal (IN_SYNTH (n)) as an output. Since the error signal is generated, G being a proportional term and G2 being an integral term, the transfer function of said loop filter can then be expressed by the following formula: IN SYNTH (z) - G2 ERR (z) The advantages of the invention include that it makes it possible to implement in a single digital circuit a complete measurement system of the parameters relating to the time stamps. In addition, the invention can be implemented within a logic programmable circuit such as an inexpensive and particularly flexible FPGA circuit.

  Other characteristics and advantages of the invention will become apparent with the aid of the following description made with reference to the appended drawings which represent:

  Figure 1 is a system clock model of an MPEG-2 encoder and measurement parameters relating to program-specific time stamps;

  FIG. 2, a device for measuring parameters relating to time stamps, according to the prior art; FIG. 3, a device for measuring parameters relating to time stamps, according to the invention; FIG. 4, an example of a clock signal generated by the fully digital phase-locked loop according to the invention; • Figure 5, the instantaneous phase error on the time separating the receipt of two time stamps; FIG. 6, an embodiment of the frequency synthesizer according to the invention. Figure 1 illustrates a system clock model of an MPEG-2 encoder and measurement parameters relating to program-specific time stamps. In digital television, for example according to the digital video broadcasting standard or the English expression Digital Video Broadcasting, the audio and video data are compressed according to the MPEG-2 standard. This data is transmitted through transport streams with frames of 188 bytes. To these 188 bytes of transport packet can also be added 16 bytes including a Reed-Solornon code for correcting transmission errors. Transport packets can therefore have up to 204 bytes. In the case of Digital Terrestrial Television, the bit rate of each stream is substantially equal to 27 Mbits / s and comprises 6 programs. In addition to audio and video, the frames may include data bits and information to retrieve the programs available in the stream, such as timestamps (or the English expression Program Clock Reference). The timestamps are used to accurately render the clock of the MP'EG-2 encoder which compressed the audio-visual data of a program. However, the transmission network may be exposed to certain effects which are not transparent with respect to the transport flows and which are caused by the elements of the network. One of the predominant effects is the introduction of jitter by the communication network which has the effect of affecting the position of the time stamps in the stream, which leads to errors relating to time stamps. Thus, the standard of measurement of the quality of service in digital television, described in document ETSI TR101290, proposes to measure four parameters relating to time stamps. Figure 1 illustrates the measurement parameters for time stamps specific to a PID program (p). The model of the inaccuracies relating to a multiplexer encoder 7 comprises a system clock 1, coming for example from a 27 MHz frequency oscillator. The instantaneous frequency of the oscillator deviates by a function fdeV (p, t), t representing the time and p the considered program. A device for measuring the parameters relating to time stamps has the particular function of measuring the errors induced by the system clock 1 of the multiplexer encoder 7. Among the errors induced by the system clock 1, mention may be made of: frequency shift error as a function of time between the actual frequency of the system clock 1 and the nominal frequency of the system clock 1; the error of drift over time of the frequency corresponding to the measurement of the function fdev (p, t). The system clock 1 of the multiplexer encoder 7 increments a counter 10 of timestamps 2, the result of which can be modeled by an ideal time stamp N (p, i). Sources of inaccuracies 3 are added 4 to the ideal time stamp N (p, i) according to, in particular, the program and the position in the transport stream. In particular, a device for measuring the parameters relating to the time stamps has the function of measuring the accuracy of the time stamps by measuring the sources of inaccuracies. 3 Between a receiver 8 and the multiplexer encoder 7 is the communication network. The communication network introduces delays 5, variable between the start time Ti and the arrival time U; a bit i of the transport stream. In the case of a time stamp, the instant of arrival U; is the arrival time of the last bit of the last byte containing the base of the time stamp. The sum between jitter J; introduced by the network whose average value is defined as zero, and the sources of inaccuracies 3 corresponds to the overall jitter. A device for measuring the parameters relating to the time stamps has the function of measuring the overall jitter. For example, the ISO / IEC 13818-1 standard defines limits on these parameters relating to time stamps. If one of these parameters goes beyond the limits of the standard, it may be considered that the decoding quality of the MPEG-2 video stream may be degraded. For the frequency offset error, this limit is set to +/- 810 Hz, ie normalized value, +/- 30 ppm. The drift of the frequency of the system clock 1 with respect to time is limited to +/- 75 mHz / s, ie a normalized value of +/- ppm / h compared to the nominal frequency of 27 MHz 35 of the clock system 1. The phase tolerance is set to + 1- 500 ns, which represents the maximum error on the value of the time stamp with respect to its time position in the transport stream. The value of + 1-500 ns is the absolute lirnite when generating the time stamp and does not include the jitter introduced by the network.

  FIG. 2 shows a device for measuring parameters relating to time stamps, according to the prior art. Elements identical to the elements already presented in the other figures bear the same references. The device for measuring parameters relating to timestamps 1 receives as input a data stream 15 comprising timestamps. The device further comprises a phase locked loop 10 (or in the English expression Phase Locked Loop). The phase locked loop 10 may be associated with a frequency offset measuring device 11. The frequency offset measuring device 11 measures the frequency offset between the actual frequency of the system clock 1 and the nominal frequency of the system clock 1. The frequency offset measuring device 11 is implemented by filtering, using a low-pass filter, the control signal of a voltage-controlled oscillator. The phase-locked loop 10 can be associated with a device for measuring the frequency drift 12. The device for measuring the frequency drift 12 measures the drift over time of the frequency corresponding to the measurement of the function fdev (p, t). The frequency drift measurement is derived from the comparison of the time stamps, filtered by a low-pass filter and then multiplied by a factor which depends on the arrival rate of the time stamps and the open-loop gain of the lock loop. The phase lock loop 10 may be associated with an overall jitter measuring device 13. The overall jitter measuring device 13 measures the accumulated jitter of the jitter produced by the imprecision on the jitter. the time stamp of entry. The phase-locked loop 10 may be associated with an inaccuracy measurement device 14. This measurement is performed by counting the number of bytes of the stream separating two successive time stamps, using an index. The difference of the time stamps is compared with the difference of the indexes, then brought back to the real period and filtered, in order to extract the parameter of precision. The phase-locked loop 10 comprises in particular a voltage-controlled quartz oscillator or in the English expression Voltage Controlled Crystal Oscillators. The device for measuring parameters relating to the time stamps according to the prior art must comprise as much voltage-controlled crystal oscillator as programs included in the data stream to measure all the parameters relating to the time stamps of the data stream. 15.

  FIG. 3 shows a device for measuring parameters relating to time stamps, according to the invention. Elements identical to the elements already presented in the other figures bear the same references. In input, the device receives a data stream including time stamps Ee. The value of the nth time stamp Ee received is denoted Ee (n). The device establishes measures relating to time stamps Ee for at least one program included in the data stream. For this, the device generates estimated time stamps Er from a recalculated clock signal from the encoder that was used to code the program. The value of the nth estimated time stamp Er calculated is denoted Er (ri). The estimated time stamps Er depend on the time of arrival of the time stamps Ee and the frequency Fr (n) of the recalculated clock signal of the encoder which was used to code the program. If the duration that separates two successive time stamps is denoted T, this relation can be expressed by the following expression by: Er (n) = Er (n-1) • ± T. Fr (n-1). To retrieve the clock signal from the encoder that was used to code the program, a comparator 20 receives and compares the time stamps Ee and the estimated time stamps Er. When at a given moment the difference between the time stamps Ee and the estimated time stamps Er is zero, then the synchronization is perfect. A loop filter 21 receives the result delivered by the comparator 20. At the output, the loop filter 21 sends a control signal to a frequency synthesizer 22. The loop filter 21 therefore controls the frequency of the signal delivered by the synthesizer 22. The frequency synthesizer 22 delivers a clock signal whose average frequency depends on the slow variations of the error signal delivered by the comparator 20 and filtered by the loop filter 21. The clock signal delivered by the frequency synthesizer 22 is sent to a counter 23. The counter 23 in turn generates estimated time stamps Er, which are then redirected and used by the comparator 20. In order to measure the parameters relating to the time stamps, a set of This filtering device set may in particular comprise: a device for measuring the offset equation 11; a device for measuring the frequency drift 12; a device for measuring the overall jitter 13; FIG. 4 illustrates an example of a clock signal generated by the fully digital phase-locked loop according to the invention. Elements identical to the elements already presented in the other figures bear the same references. FIG. 4 comprises a diagram whose axis of abscissa 32 represents the time and the ordinate axis 30 the amplitude of the clock signal Fr generated by the fully digital phase-locked loop according to the invention. The frequency synthesizer 22 according to the invention generates a clock signal Fr whose phase can be shifted by a fixed duration 6T. The modification of the phase by the frequency synthesizer according to the invention is distributed in a homogeneous manner over time. The average frequency of the clock signal Fr is modified by changing the periodicity of the delays or advances applied to the phase. Indeed, the clock signal Fr comprises pulses spaced a regular duration Tnom. In order to modify the frequency of the clock signal Fr, the frequency synthesizer according to the invention can: either introduce a delay 6T between two pulses; to decrease, by an advance equal to âT, the interval between two pulses.

  The central frequency Fnom of the generated clock signal Fr is equal to the inverse of the duration Tnom. Between two successive time stamps, that is to say during a duration T, the clock signal Fr comprises: Nnom periods of duration Tnom and Nnom + 5T periods of duration Tnom + δT or Nnom -TT periods of duration Tnom

  The average period T can then be expressed by the following formula: ## EQU1 ## It is then possible to determine the jitter from the clock signal thus generated.

  FIG. 5 illustrates the instantaneous phase error over the time separating the reception of two time stamps. The elements identical to the elements already presented in the other figures bear the same references. FIG. 5 comprises a diagram whose abscissa axis 40 represents the time and the ordinate axis 41 the instantaneous phase time value extracted from the time stamps. A curve 42 represents the evolution over time of the temporal values extracted from the time stamps Ee. A curve 43 represents the time course of the time values of the estimated time stamps Er. The frequency synthesizer 22 according to the invention makes phase offsets on the clock signal Fr spaced a duration To. Also, in the example of FIG. 5, between the arrival of a time stamp on the clock At the instant nT and the arrival of a subsequent time stamp at (n + 1) .T, the frequency synthesizer 22 according to the invention has made three phase shifts on the clock signal Fr, spaced each of a duration To. The calculation of the duration parameter To is a function of the error on the time stamps corresponding to each instant to the difference between the curve 43 and the curve 42. A solution for realizing this delay 30 of a duration To is to use a counter, for example a ramp generator, operating at a frequency which is a multiple of the central frequency Fnom of the clock signal Fr. The counter is then reset after a duration To by comparing the output of the counter with a threshold Th (n) l to the duration To.

  Figure 6 shows an embodiment of the frequency synthesizer according to the invention. Elements identical to the elements already presented in the other figures bear the same references. The frequency synthesizer according to the invention receives as input an IN SYNTH signal (n) corresponding to the control signal generated by the loop filter 21. The signal IN_SYNTH (n) corresponds to the result delivered by the comparator 20 and filtered, c ' that is, the filtered error signal between the estimated time stamps Er and the time stamps Ee. A block 50 receives on an IN input the signal IN_SYNTH (n) and delivers on an output Abs the absolute value of the signal IN_SYNTH (n). The block 50 additionally delivers a signal S indicating whether the signal IN_SYNTH (n) is negative. Block 50 again delivers a signal Z indicating whether the signal IN_SYNTH (n) is zero. These operations are synchronized with the receipt of time stamps Ee. A divider 51 receives on an input B the signal sent on the output Abs of the block 50. The divider 51 receives on an input A a signal representing a constant 52 whose value is denoted CST. The constant 52 is chosen proportional to the signal IN_SYNTH (n) and to the product of the duration T by the central frequency Fnom. The divider 51 proceeds to divide the signal present on its input A by the signal present on its input B and sends the resulting signal to an output A / B. The resulting signal sent on the output A / B corresponds to a signal whose value corresponds to the threshold Th (n). The signal sent on the NB output is sent to a register 52. The register 52 is synchronized with the receipt of the time stamps Ee. Also, the register 52 stores the threshold Th (n) received and outputs the Th threshold (n-1) previously stored. A comparator 53 has an input A and an input B. At the output, the comparator 53 delivers a signal corresponding to the result of the logical expression B> = A on an output B> = A. The comparator 53 is synchronized by an oscillator 56 delivering a signal whose frequency m.Fnom is equal to the product of an integer m with the central frequency Fnom. A counter 54 delivers a signal on an output CNT_OUT corresponding to the number of pulses received from the oscillator 56 with which it is synchronized. The counter 54 furthermore comprises a reset input connected to the output B> = A of the comparator 53. When a signal is received on the reset input, the counter is reset and reset. A finite state machine 55 has an input S connected to the output S of the block 50, an input Z connected to the output Z of the block 50, an input DIV connected to the output B> = A of the comparator 53. The state machine Finished 55 has an output Fr to which is sent the clock signal Fr that it generates. The finite state machine 55 is synchronized with the oscillator 56. The input DIV receives the signal indicating the moment when a phase shift must be made on the clock signal Fr. In the case where m is chosen equal to 4 that is, in the case where the frequency of the signal delivered by the oscillator 56 is equal to four times the center frequency Fnom, the clock signal Fr delivered by the finite state machine 55 has an equal period: either at T, = 4 * F if the input S indicates that the signal IN_ name SYNTH (n) is negative and that the input DIV corresponds to the case where the condition B> = A of the comparator 53 is verified; either at T'4 = 1 if the input Z indicates that the signal IN_SYNTH (n) is Fnom null or that the input DIV corresponds to the case where the condition B> = A of the comparator 53 is not verified; either at T; = 4 * Fnom if the input S indicates that the signal IN_SYNTH (n) is positive and that the input DIV corresponds to the case where the condition B> = A 20 of the comparator 53 is verified. In the domain of the z-transform, the frequency Fr of the output signal of the frequency synthesizer 22 as a function of the signal IN_SYNTH can be expressed by the following formula: F, (z) = Fnom * (1 + IN_SYNTH * z-`) CST In one embodiment, the frequency synthesizer according to the invention is associated with a Proportional-Integral type loop filter 21 making it possible to obtain a zero phase error on the clock signal Fr for a phase jump and a zero frequency error on the clock signal Fr 30 for a frequency hopping. Its transfer function can be expressed by the following formula: IN _ SYNTH (z) _ G G2 ERR (z) ù '+ 1 where ERR is the signal delivered by the comparator 20, G1 represents a proportional term of the corrector and G2 , an integral term. The loop filter 21 outputs the input signal IN_SYNTH (n).

  In one embodiment, when the measurement system must analyze parameters relating to time stamps Ee for an N number of programs, a first solution consists in implementing N fully digital phase-locked loops according to the invention by pooling the operators allowing the comparison of the timestamps, that is to say in particular the block 50, the constant 52, the divider 51, the register 52, the comparator 53, the counter 54 and the oscillator 56. These operators can be reused to the using multiplexers and demultiplexers.

  The device for measuring parameters relating to the time stamps according to the invention as well as the frequency synthesizer according to the invention can be used in the context of digital television. In particular, the object of the invention proves particularly useful for measuring parameters relating to time stamps present in audiovisual streams of the MPEG-2 or MPEG-4 type and more generally for all data streams comprising time stamps. . The frequency synthesizer according to the invention can be used in other fields requiring a controllable frequency synthesizer.

Claims (12)

  1. Device for measuring parameters relating to time stamps, receiving as input at least one data stream comprising time stamps (Ee), characterized in that it comprises: a comparator (20) delivering the difference between the time stamps (Ee) and estimated time stamps (Er) - a loop filter (21) filtering the result delivered by the comparator (20); a frequency synthesizer (22) delivering a clock signal (Fr), controlled by the signal received from the loop filter (21), a counter (23) generating estimated time stamps (Er) from the signal delivered by the frequency synthesizer (22), said estimated time stamps (Er) being sent to the comparator (20); means for measuring parameters relating to the time stamps (11, 12, 13, 14); the clock signal (Fr) comprising pulses spaced by a regular duration (Tnom), the synthesizer modifying the frequency of the clock signal (Fr) by: introducing a delay of a fixed duration (6T) between two pulses ; or by decreasing by an advance equal to a fixed duration (âT), the interval between two pulses, the duration (TO) separating two updates of the frequency of the clock signal (Fr) being a function of the signal received from the loop filter (21).   2. Device according to claim 1 characterized in that the frequency synthesizer (22) is associated with at least one of the following devices: a frequency offset measuring device (11); a device for measuring the frequency drift (12); a device for measuring the overall jitter (13); an inaccuracy measuring device (14).   3. Device according to any one of the preceding claims characterized in that the loop filter (21) is Proportional-Integral type, said loop filter (21) generating an output signal input (IN_SYNTH (n) ).   4. Device according to claim 3 characterized in that the error signal (ERR) being delivered by the comparator (20), G1 being a proportional term and G2 being an integral term, the transfer function of said loop filter is expressed by the following formula: IN SYNTH (z) ù G G2 ERR (z) '+ 1ùz   5. Device according to any one of the preceding claims, characterized in that, between two successive time stamps, the clock signal (Fr) comprises: Nnom periods of duration Tnom and Nnom + aT periods of duration Tnom + bT or Nnom-sT periods of duration Tnom 15 ùâT; the average period being expressed by the following formula: 7+ _ Tnom'Nnom + (Tnomt57) 'Nnom S Nnom + Nnom S   6. Device according to any one of the preceding claims, characterized in that the data streams are MPEG-2 streams.   7. Device according to any one of the preceding claims, characterized in that the data streams are MPEG-4 streams. 25   8. Device according to any one of claims 1 to 7 characterized in that the frequency synthesizer (22) controlled by an input signal (IN SYNTH (n)) comprises: a block (50) delivering the value absolute of the input signal (IN_SYNTH (n)) on an output (Abs), a signal (S) indicating whether the input signal (IN_SYNTH (n)) is negative, a signal (Z) indicating whether the signal input (IN_SYNTH (n)) is a divider (51) generating a signal corresponding to the division of the signal representing a constant (52) fixed to a given value (CST) by the signal sent on the output (Abs) of the block (50); a register (52) storing the signal generated by the divider (51) and outputting the previously stored signal; a counter (54) outputting a signal on an output (CNT_OUT) corresponding to the number of pulses received from an oscillator (56), the counter (54) having an input (RAZ) for resetting it; a comparator (53) comparing the signal delivered by the register (52) with the output signal of the counter (54) and outputting (B> = A) a signal corresponding to the result; a finite state machine (55) using the signals (S, Z) indicating whether the input signal (IN_SYNTH (n)) is negative or zero of the block (50) for generating a clock signal Fr; finite state (55) operating a phase shift on the clock signal Fr when it receives the signal delivered by the comparator (53) on its input (DIV).   9. Device according to claim 8, characterized in that the comparator (53), the counter (54) and the finite state machine (55) are synchronized by the oscillator (56) delivering a signal whose frequency m.Fnom is equal to the product of an integer m with the center frequency Fnom of the clock signal Fr.   10. Device according to any one of claims 8 to 9 characterized in that the frequency of the signal delivered by the oscillator (56) being substantially equal to four times the center frequency Fnom, the clock signal Fr delivered by machine to finite state (55) has a period equal to either T3 = 4 * F if the input (S) of the finite state machine (55) name indicates that the input signal (IN_SYNTH (n)) is negative and that the input (DIV) of the finite state machine (55) corresponds to the case where the condition (B> = A) of the comparator (53) is satisfied; T4 = 1 if the input (Z) of the finite state machine (55) indicates Fnom that the input signal (IN_SYNTH (n)) is zero or that the input (DIV) of the machine finite state (55) corresponds to the case where the condition (B> = A) of the comparator (53) is not satisfied; either at TS = 4 * Fnom if the input (S) of the state machine (55) indicates that the input signal (IN_SYNTH (n)) is positive and that the input (DIV) of the machine to finite state (55) corresponds to the case where the condition (B> = A) of the comparator (53) is satisfied.   11. Device according to any one of claims 8 to 10 characterized in that it comprises a loop filter (21) Proportional-Integral type, said loop filter (21) outputting the input signal (IN_SYNTH (not)). 15   12. Device according to claim 11 characterized in that an error signal (ERR) being generated, G1 being a proportional term and G2 being an integral term, the transfer function of said loop filter is expressed by the following formula: IN_SYNTH (z) + G2 20 ERR (z) 1-z-