FR2880463A1 - Line decoder for electronic memory, has transistors associated to each group of line driver circuits, and connecting one of two PMOS transistors of circuits to supply terminal carrying supply voltage related to selected state - Google Patents

Abstract

The decoder has line driver circuits (DL) distributed in groups and having PMOS transistors connected to word lines of a memory array to position the lines respectively in selected or deselected state. Decoding circuits (30-34) select a circuit (DL) based on a line address. Transistors (41-44) associated to each group connect one of the PMOS transistors to a supply terminal carrying a supply voltage related to the selected state. Independent claims are also included for the following: (A) an integrated electronic circuit having an electronic memory with a memory array coupled with an line decoder (B) a method for addressing a line of a memory array using line driver circuits.

Description

LINE DECODER AND LOW ELECTRONIC MEMORY

  The invention relates to electronic memories and more particularly to a row decoder of a storage array.

  Electronic memories are components used in many electronic products. There are different types of memories whose differences come essentially from the type of elementary storage cells. Whatever this type may be, the internal structure of a memory is basically the same.

  An example of a memory structure is shown in FIG. 1. The storage matrix 1 comprises a plurality of elementary storage cells 2 organized in rows 3 and 4. A row decoder 5 is connected to word lines corresponding to the rows 3 of cells, to allow selection of a row of cells in the array based on a line address. Read and / or write circuits 6 are connected to the columns 4 of cells to enable reading and / or writing in one or more cells of the selected line.

  The line decoder 5 comprises an address decoding circuit and a plurality of DL line driver circuits. A line driver DL is connected to a single line 3 of cells and serves to amplify the current to quickly bring the voltage of line 3 to a voltage corresponding to the selection of the cells of the line.

  FIG. 2 represents an exemplary DL line control circuit, according to the state of the art, realized in CMOS technology. The DL circuit comprises three PMOS transistors 10 to 12 and three NMOS transistors 20 to 22. The transistors 10 and 20 form an output inverter which drives a word line WL 3. The transistor 11 makes it possible to lock the output inverter in a deselected state. Transistor 21 serves to switch the DL circuit to a selected state when said DL circuit is selected by an address decode circuit. Transistors 12 and 22 serve to synchronize the switching of the DL circuit with a clock signal CK.

  The line driver circuit of Figure 2 gives good results and is widely used in the memories. However, one constantly seeks to improve memory performance. The research focuses on increasing the memory capacity, increasing its operating speed and reducing its power consumption.

  With regard to the power consumption of a memory, all elements of the memory must be considered individually. The line driver circuit DL of Figure 2 has a low static consumption when it is not selected. This static consumption is essentially due to the leakage currents of the blocked transistors. The largest leakage current is that of transistor 10 which is sized to pass a large current.

  The reduction of the leakage currents of the transistors can be done by acting on their intrinsic characteristics by varying manufacturing parameters such as, for example, the concentration of carriers. For example, for transistors made in a 90 nm technology where 90 nm corresponds to a minimum transistor size, the leakage current of the transistor 10 can vary between 0.2 and 10 A. These values may appear low but are to multiply by the number of lines of a memory which is commonly greater than or equal to 210, to obtain the consumption related to the leakage current of these transistors for a complete decoder.

  By acting on the manufacturing parameters, all the characteristics of the transistors change and a low power consumption generally corresponds to a reduction of the switching speeds of the transistors and therefore to a slower memory. For manufacturing parameters corresponding to a fast memory, the leakage currents become very important and can represent more than half of the current necessary for the operation of a line decoder.

  One solution to not penalize the speed of memory is to switch the memory into a sleep mode when it is not used. In the standby mode, power is removed from the memory circuits that do not actively participate in the storage of the data. In practice, the power supply is cut off for all the circuits of the memory except for the memory matrix and possibly a refresh circuit.

  Such a solution reduces the consumption of the memory when it is not requested but does not reduce the consumption thereof when it is in operation. In addition, the transition from standby mode to the operating mode requires a significant period of time to replenish all the circuits of the memory.

  The invention proposes a solution for reducing memory consumption by providing a low power line decoder. According to the invention, the line control circuits of the line decoder are divided into groups. Each control group has its power partially cut off if no control circuit of the group is selected. The power supply is partially cut only for transistors with the largest leaks. The partial power failure is done independently for each group by cutting off the supply of a portion of the transistors of each line driving circuit constituting the group. Thus, the power switching of a group of line driver circuits uses much less currents than a memory standby and does not require any precaution when the power is turned back on. group. This power switching can be used during the operation of the memory without penalizing the speed of operation.

  According to a first aspect, the invention is a row decoder for a storage array comprising a plurality of line control circuits, decoding circuits and at least one additional transistor. The line control circuits are intended to be each connected to a respective line of said matrix. Each line driver circuit comprises at least a first and a second output transistor each connected to said line to allow to position said line respectively in a selected state or in an unselected state. The decoding circuitry makes it possible to select a line driver circuit from among said plurality of line driver circuits as a function of a line address. The plurality of line driver circuits are divided into at least two groups of line driver circuits. At least one additional transistor is associated with each group of line driving circuits, said additional transistor connecting the first output transistors of the line drive circuits of the group to a first power supply terminal which supports a supply voltage corresponding to the selected state.

  To further reduce the leakage currents, it is possible to apply the same principle to other transistors of the control circuit.

  Preferably, each line control circuit comprises a selection transistor, a control electrode of which is connected to a decoding circuit for selecting or deselecting said line control circuit, the decoder further comprising at least one additional second transistor associated with each group of line driver circuits, said second transistor connecting the selection transistors of a group to a second power supply terminal.

  According to a preferred embodiment, the additional transistor and optionally the second additional transistor are controlled by one of the decoding circuits in order to be on when one of the line control circuits of the associated group is selected and in order to blocked when none of the line control circuits of the associated group is selected.

  According to a second aspect, the invention is an electronic memory comprising at least one storage matrix coupled to a line decoder according to the first aspect. An integrated electronic circuit may comprise at least one electronic memory according to this second aspect.

  According to a third aspect, the invention is a line addressing method of a storage array using a plurality of line driver circuits coupled to decoding circuits. The line driving circuits are divided into at least two groups. The supply of the line driving circuits of a group is partially cut off when no line control circuit of said group is selected.

  The invention will be better understood and other features and advantages will appear on reading the description which follows, the description referring to the appended figures in which: FIG. 1 shows an example of a memory structure, FIG. example of a line driver circuit according to the state of the art, Figure 3 shows an example of line driver circuit according to the invention, Figure 4 shows an example line decoder according to the invention.

  The invention concerning the line decoders of the memories, the memory structure of FIG. 1 is also used with the invention. The memory structure of FIG. 1 represents a memory having a single storage matrix. There are memory structures with multiple arrays. However, when a memory structure has more than one matrix, the structure of FIG. 1, at least for the part relating to the row decoder 5, is duplicated as many times as there are matrices. The line decoder according to the invention can be used both in a single-matrix memory structure and in a memory structure having several matrices.

  In the present description, the logic signals are active in the high state and inactive in the low state. The high state corresponds to a voltage between the supply voltage and half of the supply voltage VDD. The low state corresponds to a voltage between the ground voltage and half of the supply voltage. To simplify the explanations while approaching the reality, it is considered that the high state substantially corresponds to the supply voltage VDD and that the low state substantially corresponds to the ground voltage.

  FIG. 3 represents an exemplary DL line driving circuit according to the invention. The DL circuit comprises three PMOS transistors 10 to 12 and three NMOS transistors 20 to 22. The transistors 10 and 20 form an output inverter which drives the line 3 of cells. The gates of the transistors 10 and 20 are connected together and form the input of the output inverter. The drains of the transistors 10 and 20 are connected together and form the output of the output inverter which corresponds to the output of the circuit DL connected to the line 3 of storage cells. The source of transistor 20 is connected to ground. The source of the transistor 10 is connected to a high voltage terminal which receives a switched high voltage VDDH.

  The transistor 11 makes it possible to lock the output inverter in an unselected state. The gate of transistor 11 is connected to the output of the output inverter. The drain of transistor 11 is connected to the input of the output inverter. The source of the transistor 11 is connected to the supply voltage VDD.

  The transistor 21 makes it possible to switch the DL circuit in a selected state when said control circuit is selected by an address decoding circuit. The gate of transistor 21 receives a selection signal Sel from an address decoding circuit. The source of the transistor 21 is connected to a low voltage terminal which receives a switched low voltage Vss.

  Transistors 12 and 22 serve to synchronize the switching of the DL circuit with a clock signal CK. The gates of the transistors 12 and 22 are connected together and form an input receiving the clock signal CK. The drains of transistors 12 and 22 are connected together to the input of the output inverter. The source of the transistor 12 is connected to the supply voltage VDD. The source of transistor 22 is connected to the drain of transistor 21.

  If it is considered that the switched high voltage VDDH is connected to the supply voltage VDD and the switched low voltage Vss is connected to ground, the line control circuit DL operates in the same way as a control circuit. the state of the art. For this purpose, the transistors 10 to 12 and 20 to 22 are sized as those of the state of the art. The transistor 11 is of minimum size, the transistors 21 and 22 are of sufficient size to call a current greater than the current that can provide the transistor 11. The transistors 10 and 20 are sized to be able to provide a sufficient current to quickly load the line of cells to which they are connected. The size of the transistors 10 and 20 is much larger than the size of the other transistors of the DL circuit.

  When the clock signal CK is inactive, the transistor 12 is on while the transistor 22 is off. The input voltage of the output inverter is substantially equal to the supply voltage VDD. The output voltage is then at a low level. While the clock signal is low, decoder circuits determine which line driver must be selected based on a line address. The duration of the low state of the clock signal CK is sufficiently large to mask the switching time of the decoding circuits, so that when the clock signal CK becomes active only one line driving circuit is selected by the decoding circuits while all the other control circuits are deselected.

  When the clock signal CK is active and the line driving circuit is selected, that is to say when the signal Sel is active, the transistors 21 and 22 are on. The input voltage of the output inverter is substantially equal to the ground voltage. The output of the inverter is active and selects the line of cells connected to the line driver circuit DL.

  When the clock signal CK is active and the line control circuit is deselected, that is to say when the signal Sel is inactive, the transistor 21 is blocked. The input voltage of the output inverter is maintained at a voltage substantially equal to the supply voltage VDD by the transistor 11.

  If it is considered that the switched high voltage VDDH and the switched low voltage Vs are connected to a floating potential, typically an open circuit, the output inverter remains locked by the transistor 11 and the line driver DL provides a voltage substantially equal to the ground voltage corresponding to a deselection of the line 3.

  A line decoder 5 according to the invention is shown in FIG. 4. This row decoder 5 comprises a plurality, for example 210, of DL line driver circuits in accordance with the line driver circuit of FIG. 3. The decoder of lines 5 further comprises decoding circuits 30 to 34, first transistors 41 to 44, inverters 51 to 54 and second transistors 61 to 64.

  By way of example, the memory comprises 210 rows of cells also called word lines denoted WLO to wu 023. Each word line WLi is connected to the output of one of the 1024 line control circuits DL. The addressing of a word line WLi is done using a line address @ L0_9 consisting of 10 bits, each address value corresponding to a single line WLi.

  The decoding circuits 30 to 34 are arranged in cascade over two stages according to a known technique for constituting an address decoding circuit. The decoding circuits 30 to 34 each have an address address bus i, a validation input EN and 2 'selection outputs. When the signal on the EN enable input is inactive, all selection outputs are inactive. When the signal on the enable input EN is active, a selection output corresponding to the input address is active, the other outputs being inactive.

  The decoding circuit 30 decodes one of 16 addresses, it receives the four most significant bits @ L6_9 of the line address @ L0_9 on a 4-wire address bus and a validation signal CS on a validation input EN . The signal CS is activated for example when the memory is selected according to a known technique. Each of the sixteen selection outputs of the decoding circuit 30 is connected to the validation input EN of one of the sixteen decoding circuits 31 to 34 (only four are represented so as not to overload the drawing).

  The decoder circuits 31 to 34 each decode one of 64 addresses, each receiving the six low order bits @ L0_5 of the line address L0_9 on a 6-wire address bus. Each of the 64 outputs of each of the sixteen decoder circuits 31 to 34 is connected to the selection input of one of the 1024 DL line driver circuits.

  The 1024 DL circuits are grouped into sixteen groups of 64 DL circuits, each group corresponding, for example, to one of sixteen decoder circuits 31 to 34. Each of the first transistors 41 to 44 connects the high voltage terminals of the control circuits. DL line of, respectively, each of the DL circuit groups to a conductor supporting the supply voltage VDD. The gate of each of the first transistors 41 to 44 is connected, via one of the inverters 51 to 54, to the selection output of the decoding circuit 30 which corresponds to the decoding circuit 31 to 34 connected to said group. Thus, each first transistor 41 to 44 is controlled by the decoding circuit 30 to be on when one of the DL line driver circuits of the associated group is selected and to be blocked when none of the DL circuits of the group partner is not selected.

  Each of the second transistors 61 to 64 connects the low voltage terminals of the line driver DL, respectively, each of the DL circuit groups to a ground conductor. The gate of each of the second transistors 61 to 64 is connected to the selection output of the decoding circuit 30 which corresponds to the decoding circuit 31 to 34 connected to said group. Thus, each second transistor 61 to 64 is controlled by the decoding circuit 30 to be on when one of the DL line driver circuits of the associated group is selected and to be blocked when none of the DL circuits of the group partner is not selected.

  The clock inputs of the DL line driver circuits are all connected together and receive the same clock signal CK. The links of the clock inputs are not shown in FIG. 4 so as not to overload the drawing.

  To address a line, the line address @ L0_9 should be supplied to the decoder circuits 30 to 34 and the CS signal activated. The decoding circuit 30 decodes the four most significant bits @ L6_9 and activates only one of its selection outputs. In response to the activation of the output, one of the decoder circuits 31 to 34 corresponding to one of the DL line driver circuits groups decodes the six LSBs @ L0_5 and activates one of its exits. The first and the second transistors of the corresponding group are on and the line decoder corresponding to the address @ L0_9 selects the corresponding word line.

  The first and second transistors corresponding to the unselected groups are blocked. Thus, the unselected DL line drive circuit groups are partially powered and the transistor 10 and the transistor 21 are not powered for these unselected groups. Decoding circuits that are not selected all have their outputs inactive.

  The consumption related to leakage currents is greatly reduced. If you consider the selected group, 63 of the 64 DL circuits are deselected and only one is selected. For the DL circuit selected, the leakage currents are located in the transistors 11, 12 and 20, the sum of these currents corresponding to II. For a deselected line driving circuit, the leakage currents are located in the transistors 10, 21 and 22, the sum of these currents corresponding to 12.

  If we consider the deselected groups, the leakage currents are located on the one hand in the transistors 10, 21 and 22 but also in the first and second transistors 41 to 44 and 61 to 64.

  However, the first and second transistors 41 to 44 and 61 to 64 are sized to pass a current sufficient to ensure the power of the transistors 10, 21 and 22 of the DL circuits of the group without penalizing the switching speed, it is that is, by supplying a current corresponding to the maximum current required for a selected line driving circuit, supplemented with a current corresponding to the leakage currents of the deselected DL circuits of the group and a current for charging the parasitic capacitance related the lengths of conductors connecting the first and second transistors to the DL circuits of their group. For groups of 64 DL line driver circuits, the first and second transistors are sized to pass a current for example four times larger than the transistors 10, 21 and 22 to which they are connected.

  The sum of the leakage currents of the 64 DL line driver circuits is limited to the leakage currents of the first and second transistors 41 to 44 and 61 to 64. Thus for each unselected group of DL line driver circuits, the Leakage current is limited to four times current 12 when the size of the first and second transistors is in a ratio four with transistors 10, 21 and 22.

  In a first approximation of the example described, the total sum of the leakage currents then becomes equal to 11 + 63 * 12 + 15 * 4 * I2, ie Il + 123 * 12.

  In the state of the art, for the same number of lines, 1023 control circuits have a leakage current equal to 12 and a line drive circuit has a leakage current equal to 1, ie a total equal to Li + 1023 * 12. If we consider Il = 12, the gain provided by the invention corresponds to a decrease of 87% of the leakage currents in this example.

  However, in a second approximation, it should be noted that this gain is even greater because the addition of the first and second transistors 41 to 44 and 61 to 64 creates a voltage drop on the sources of the transistors 10 and 21 when said first and second transistors are on. This voltage drop reverse bias the source / substrate junction of the transistors 10 and 21, which causes a leakage current reduction for said transistors, thus the sum of the leakage currents for the transistors 10, 21 and 22 of the control circuits. not selected from the selected group is 63 * 2, with 1'2 <12.

  Many variations of the invention are possible. The example described corresponds to a preferred embodiment of the invention for a line decoder connected to a storage matrix of 210 word lines.

  The number of word lines depends on the size of the memory, and a good compromise must be found between the number of groups of line driver circuits and the number of line driver circuits per group to be able to reduce the consumption of Memory. The larger the size of a group, the lower the leakage currents when the group is deselected and the greater the leakage currents are important when the group is selected.

  The example shows a decomposition into 16 groups of 64 line driver circuits because the reduction of the leakage currents is significant with such a choice but also because the decoding circuits commonly used consist of 8 or 8 decoding circuit circuits. 16 outputs. The 64-output decoding circuit is for example made by a combination of two stages of circuits with eight outputs. In a preferred manner, the distribution of the groups uses a distribution compatible with the distribution of the already existing decoding circuits to select the line control circuits in order to avoid adding a specific circuit to control the first and second transistors.

  Also, the example described uses second transistors to reduce the leakage currents on the transistors 21 and 22. These leakage currents are much lower than the leakage currents of the transistors 10 and may not be compensated for simplifying the memory.

  The same signal is used to control the first transistors 41 to 44 and the second transistors 61 to 64. The use of the same control signal requires the addition of the inverters 51 to 54 which complicates the structure. If one is satisfied only with the first transistors, it is possible to choose decoding circuits providing a control signal adapted to the first transistors, to suppress the inverters.

  The conventions on the active and inactive states, corresponding to high or low voltages, can also be changed according to technological choices without calling into question the invention. It then suffices to replace the PMOS transistors with NMOS and to reverse the supply voltages.

  Finally, another advantage comes from the functional redundancy of the enable inputs EN of the decoding circuits 31 to 34 and the second transistors 61 to 64. If the second transistors 61 to 64 are used, the decoding circuits 31 to 34 do not need validation input and can be simplified. - 13-

Claims (9)

  1 line decoder for a storage array comprising: a plurality of line control circuits (DL) intended to be each connected to a respective line (WLO to WL1024) of said matrix, each line control circuit comprising at least first and second output transistors (10, 20) each connected to said line for positioning said line respectively in a selected state or in a deselected state, - decoding circuits (30- -34) for selecting a circuit line driver (DL) of said plurality of line driver circuits as a function of a line address (@ L0_9), characterized in that the plurality of line driver circuits are divided into at least two groups of line driving circuits, and in that it comprises at least one additional transistor (41-44) associated with each group of line driving circuits, said additional transistor connecting the first output transistors (10) of the line drive circuits of the group to a first power supply terminal which supports a supply voltage corresponding to the selected state.   The decoder according to claim 1, wherein the additional transistor (41-44) is controlled by one (30) of the decoder circuitry to be on when one of the line driver circuits (DL) of the associated group is selected and to be locked when none of the associated group's line driving circuits are selected.   The decoder according to claim 1 or claim 2, wherein each line drive circuit comprises a selection transistor (21) having a control electrode connected to a decoder circuit (31-34) for selecting or deselecting said line driving circuit, the decoder further comprising at least one additional second transistor (61-64) associated with each group of line driving circuits, said second transistor connecting the selection transistors of a group to a second terminal of 'food.   The decoder according to claim 3, wherein the second additional transistor is controlled by one of the decoding circuits to be on when one of the associated group's line driver circuits is selected and in order to be switched on. blocked when none of the line control circuits of the associated group is selected.   5. Electronic memory comprising at least one storage matrix (1) coupled to a line decoder (5), characterized in that the line decoder is according to one of claims 1 to 4.   6. Integrated electronic circuit characterized in that it comprises at least one electronic memory according to claim 5.   7. A row addressing method of a storage array using a plurality of line driver circuits (DL) coupled to decoder circuits (30-34), the line driver circuits ( DL) being divided into at least two groups, characterized in that the supply of the line driving circuits of a group is partially cut off when no line driving circuit of said group is selected.   The method according to claim 7, wherein, each line driving circuit comprising at least two output transistors (10, 20), one (10) of the two output transistors is no longer powered when the group of Line control circuits including it is partially powered.   9. A method according to claim 7 or 8, wherein, each line driving circuit having at the molins a selection transistor (21) connected to the decoding circuits, the selection transistor (21) is not powered when the group line control circuitry comprising it is partially powered.