FR2880185B1 - PROCESS FOR PROCESSING A WAFER SURFACE - Google Patents

PROCESS FOR PROCESSING A WAFER SURFACE

Info

Publication number
FR2880185B1
FR2880185B1 FR0413922A FR0413922A FR2880185B1 FR 2880185 B1 FR2880185 B1 FR 2880185B1 FR 0413922 A FR0413922 A FR 0413922A FR 0413922 A FR0413922 A FR 0413922A FR 2880185 B1 FR2880185 B1 FR 2880185B1
Authority
FR
France
Prior art keywords
processing
wafer surface
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0413922A
Other languages
French (fr)
Other versions
FR2880185A1 (en
Inventor
Cecile Delattre
Frederic Metral
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Priority to FR0413922A priority Critical patent/FR2880185B1/en
Priority to US11/145,455 priority patent/US7919391B2/en
Priority to EP05823924A priority patent/EP1829099A1/en
Priority to PCT/EP2005/057003 priority patent/WO2006069945A1/en
Priority to KR1020077014457A priority patent/KR100884672B1/en
Priority to JP2007547504A priority patent/JP2008526006A/en
Priority to TW094145970A priority patent/TWI333258B/en
Publication of FR2880185A1 publication Critical patent/FR2880185A1/en
Application granted granted Critical
Publication of FR2880185B1 publication Critical patent/FR2880185B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
FR0413922A 2004-12-24 2004-12-24 PROCESS FOR PROCESSING A WAFER SURFACE Expired - Fee Related FR2880185B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0413922A FR2880185B1 (en) 2004-12-24 2004-12-24 PROCESS FOR PROCESSING A WAFER SURFACE
US11/145,455 US7919391B2 (en) 2004-12-24 2005-06-02 Methods for preparing a bonding surface of a semiconductor wafer
PCT/EP2005/057003 WO2006069945A1 (en) 2004-12-24 2005-12-21 Method for treating the surface of a wafer
KR1020077014457A KR100884672B1 (en) 2004-12-24 2005-12-21 Method for treating the surface of a wafer
EP05823924A EP1829099A1 (en) 2004-12-24 2005-12-21 Method for treating the surface of a wafer
JP2007547504A JP2008526006A (en) 2004-12-24 2005-12-21 Wafer surface processing method
TW094145970A TWI333258B (en) 2004-12-24 2005-12-23 A method of treating a wafer surface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0413922A FR2880185B1 (en) 2004-12-24 2004-12-24 PROCESS FOR PROCESSING A WAFER SURFACE

Publications (2)

Publication Number Publication Date
FR2880185A1 FR2880185A1 (en) 2006-06-30
FR2880185B1 true FR2880185B1 (en) 2007-07-20

Family

ID=34953367

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0413922A Expired - Fee Related FR2880185B1 (en) 2004-12-24 2004-12-24 PROCESS FOR PROCESSING A WAFER SURFACE

Country Status (1)

Country Link
FR (1) FR2880185B1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3187109B2 (en) * 1992-01-31 2001-07-11 キヤノン株式会社 Semiconductor member and method of manufacturing the same
JPH07183288A (en) * 1993-12-24 1995-07-21 Toshiba Corp Semiconductor wafer treating agent
US5916819A (en) * 1996-07-17 1999-06-29 Micron Technology, Inc. Planarization fluid composition chelating agents and planarization method using same
US6896826B2 (en) * 1997-01-09 2005-05-24 Advanced Technology Materials, Inc. Aqueous cleaning composition containing copper-specific corrosion inhibitor for cleaning inorganic residues on semiconductor substrate
US7235461B2 (en) * 2003-04-29 2007-06-26 S.O.I.Tec Silicon On Insulator Technologies Method for bonding semiconductor structures together

Also Published As

Publication number Publication date
FR2880185A1 (en) 2006-06-30

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Legal Events

Date Code Title Description
CD Change of name or company name

Effective date: 20120423

Owner name: SOITEC, FR

ST Notification of lapse

Effective date: 20130830