FR2879013A1 - Phase changeable memory cell comprises phase change material pattern disposed on lower interlayer dielectric layer to contact lower conductive plug - Google Patents

Abstract

Phase changeable memory cell comprises lower interlayer dielectric layer; lower conductive plug; phase change material pattern disposed on the lower interlayer dielectric layer to contact the lower conductive plug; upper interlayer dielectric layer; and conductive layer pattern in direct contact with the phase change material pattern through a plate line contact hole that penetrates the upper interlayer dielectric layer. Phase changeable memory cell comprises lower interlayer dielectric layer formed on a semiconductor substrate; lower conductive plug passing through the lower interlayer dielectric layer; phase change material pattern (41a-b) disposed on the lower interlayer dielectric layer to contact the lower conductive plug; upper interlayer dielectric layer (45) covering the phase change material pattern and lower interlayer dielectric layer; and conductive layer pattern in direct contact with the phase change material pattern through a plate line contact hole (45b) that penetrates the upper interlayer dielectric layer. An independent claim is also included for a method of forming a phase changeable memory cell, comprising forming a lower interlayer dielectric layer on a semiconductor substrate; forming a lower conductive plug passing through the lower interlayer dielectric layer; forming a phase change material pattern on the lower interlayer dielectric layer, the phase change material pattern being in contact with the lower conductive plug; forming an upper interlayer dielectric layer to cover the phase change material pattern and the lower interlayer dielectric layer; patterning the upper interlayer dielectric layer to form a plate line (51) contact hole that exposes a portion of the phase change material pattern; and forming a conductive layer pattern that is in direct contact with the exposed portion of the phase change material pattern through the plate line contact hole.

Description

The present invention relates to devices

  and non-volatile memory devices retain their stored data even when their power supplies are turned on. off, and therefore non-volatile memory devices have been widely used in conjunction with computers, mobile telecommunication systems, smart cards, etc. For example, the flash memory device is a widely used type of nonvolatile memory device. Many flash memory devices employ memory cells having a stacked gate structure. The stacked gate structure of a flash memory device typically includes a tunnel oxide layer, a floating gate, an intergrid dielectric layer, and a control gate electrode, all of which are stacked successively on a channel region. In addition, to improve the reliability and programming efficiency of flash memory cells, the film quality of the tunnel oxide layer must be improved and the coupling ratio of the flash memory cell must be increased.

  Other types of nonvolatile memory devices, such as phase change memory devices, have recently been used in place of flash memory devices. An elementary cell of a phase change memory device typically includes a switching device and a data storage element connected in series with the switching device. The data storage element of a phase change memory device comprises a lower electrode electrically connected to the switching device, a phase change material pattern disposed on the lower electrode, and an upper electrode disposed on the pattern of phase change material. In general, the lower electrode performs the function of a heating element. For example, when a write current flows through the switching device and the lower electrode, heat, measured in units of energy (joules), is generated at an interface between the pattern of change material. phase and the lower electrode. The heat measured in units of energy (joules) converts the pattern of phase change material into an amorphous state or a crystalline state.

  Fig. 1 is a sectional view illustrating a portion of a conventional phase change memory cell.

  With reference to FIG. 1, it will be noted that a lower interlayer dielectric layer 3 is established on a semiconductor substrate 1. The semiconductor substrate 1 is electrically connected to a contact crossing 5, which passes through the lower interlayer dielectric layer 3.

  The contact crossing 5 fulfills the function of a lower electrode. A phase change material pattern 7 is stacked on the lower interlayer dielectric layer 3 to cover the lower electrode 5. In addition, an upper surface of the phase change material pattern 7 is in contact with an upper electrode 9. The upper electrode 9 is self-aligned with the phase change material pattern 7 so as to have the same width as the phase change material pattern 7.

  The phase change material pattern 7 may consist of a layer of a chalcogenide material, such as a layer of GeSbTe (hereinafter referred to as a layer of GST). The GST layer readily reacts with a layer of conductive material, such as a polycrystalline silicon (poly-Si) layer. For example, when the GST layer is in direct contact with a poly-Si layer, silicon atoms in the poly-Si layer infiltrate into the GST layer, which has the effect of increasing the resistance. of the GST layer. As a result, the characteristics of the GST layer are degraded. Therefore, the lower and upper electrodes 5 and 9 which are in direct contact with the phase change material pattern 7, are formed by stable conductive layers which do not react with the phase change material pattern 7. For example, a metal nitride layer such as a titanium nitride layer is widely used in the formation of the lower and upper electrodes 5 and 9.

  Furthermore, the entire surface of the semiconductor substrate 1 having the upper electrode 9 is covered with an upper interlayer dielectric layer 11. A metallization line 13 is disposed on the upper interlayer dielectric layer 11 and is electrically connected to the upper electrode 9 through a metallization line contact hole 11a which passes through the upper interlayer dielectric layer 11.

  To store desired data in a phase change memory cell having the phase change material pattern 7, a write current IW must flow through the upper electrode 9, the phase change material pattern 7 and the lower electrode 5. Part 7a of the phase change material pattern 7, which is in contact with the lower electrode 5, can be changed to a crystalline or amorphous state in accordance with the value of the write current IW. . In addition, the metallization line contact hole 11a may typically have a width smaller than that of the upper electrode 9. However, despite the variations mentioned above which can be made to the In the conventional phase, the write current IW will always flow uniformly through the entire region of the upper electrode 9, as shown in FIG. 1, because the upper electrode 9 has a lower resistivity than the material pattern. Therefore, the write current density in the volume region of the phase change material pattern 7 of the conventional phase change memory cell contemplated above is lower than that the interface between the lower electrode 5 and the phase change material pattern 7, which degrades the phase transition efficiency in the volume region of the tif of phase change material 7 of these conventional devices.

  Another conventional phase change memory cell is set forth in U.S. No. 6,545,903 issued to Wu, entitled "Self-Aligned Resistive Plugs for Forming Memory Cell with Phase Change Material". The phase change memory cell described in the Wu patent comprises a first layer of high resistivity material and a second layer of high resistivity material which are respectively disposed below and above a layer of material having a high resistivity. phase change. In addition, a first low resistivity crossing and a second low resistivity crossing, which are mutually self-aligned, are respectively disposed in the first and second layers of high resistivity material. The first and second layers of high resistivity material consist of polycrystalline silicon (poly-Si) or amorphous silicon (A-Si), and self-aligned low resistivity crossings are formed by implanting impurity ions into the layers of high resistivity material, using an ion implantation process. Therefore, the phase change material layer of the phase change memory cell described in the Wu patent is in direct contact with silicon layers, which has the effect of rendering unstable the characteristics of the interfaces between the layer of phase change material and the silicon layers of this conventional memory cell.

  An exemplary embodiment provides a phase change memory cell. The phase change memory cell comprises a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive vias through the lower interlayer dielectric layer.

  A phase change material pattern is disposed on the lower interlayer dielectric layer and in contact with the lower conductive bushing. The phase change material pattern and the lower interlayer dielectric layer are covered by an upper interlayer dielectric layer. The phase change material pattern is in direct contact with a conductive layer pattern through a metallization line contact hole that passes through the upper interlayer dielectric layer.

  Another exemplary embodiment of the invention provides a phase change memory cell. The phase change memory cell includes a separation layer formed in a predetermined region of a semiconductor substrate to define an active region. A switching device is formed in the active region. A lower interlayer dielectric layer is formed on the substrate having the switching device. The switching device is electrically connected to a lower conductive bushing passing through the lower interlayer dielectric layer. A phase change material pattern is disposed on the lower interlayer dielectric layer and in contact with the lower conductive bushing. The phase change material pattern and the lower interlayer dielectric layer are covered by an upper interlayer dielectric layer. A metallization line is disposed on the upper interlayer dielectric layer and in direct contact with the phase change material pattern, through a metallization line contact hole that passes through the upper interlayer dielectric layer.

  Another exemplary embodiment provides a phase change memory cell. The phase change memory cell includes a separation layer formed in a predetermined region of a semiconductor substrate to define an active region. A switching device is formed in the active region. An interlayer dielectric layer is formed on the substrate having the switching device. The switching device is electrically connected to a lower conductive bushing passing through the lower interlayer dielectric layer. A phase change material pattern is disposed on the lower interlayer dielectric layer and in contact with the lower conductive bushing. The phase change material pattern and the lower interlayer dielectric layer are covered by an upper interlayer dielectric layer. The phase change material pattern is in direct contact with an upper conductive feedthrough which fills a metallization line contact hole through the upper interlayer dielectric layer. A metallization line is disposed on the upper interlayer dielectric layer and the metallization line is electrically connected to the upper conductive vias.

  Another exemplary embodiment provides a phase change memory cell. The phase change memory cell comprises a lower interlayer dielectric layer formed on a semiconductor substrate and a lower conductive vias through the lower interlayer dielectric layer. A lower electrode is disposed on the lower interlayer dielectric layer and the lower electrode is in contact with the lower conductive vias. The lower electrode and the lower interlayer dielectric layer are covered by a molding layer. A phase change material pattern is disposed on the molding layer and the phase change material pattern is in contact with the lower electrode through a phase change material contact hole which passes through the molding layer. . An upper interlayer dielectric layer is disposed on the substrate having the phase change material pattern. The phase change material pattern is in direct contact with a conductive layer pattern through a metallization line contact hole that passes through the upper interlayer dielectric layer.

  Another exemplary embodiment of the invention provides a phase change memory cell. The phase change memory cell includes a separation layer formed in a predetermined region of a semiconductor substrate to define an active region. A switching device is formed in the active region. A lower interlayer dielectric layer is disposed on the substrate having the switching device. The switching device is electrically connected to a lower conductive bushing passing through the lower interlayer dielectric layer. A lower electrode is disposed on the lower interlayer dielectric layer and the lower electrode is in contact with the lower conductive vias. The lower electrode and the lower interlayer dielectric layer are covered by a molding layer. A phase change material pattern is disposed on the molding layer and the phase change material pattern is in contact with the lower electrode through a phase change material contact hole which passes through the molding layer. . An upper interlayer dielectric layer is disposed on the substrate having the phase change material pattern. A metallization line is disposed on the upper interlayer dielectric layer and the metallization line is in direct contact with the phase change material pattern through a metallization line contact hole which passes through the upper interlayer dielectric layer.

  Another exemplary embodiment of the invention provides a phase change memory cell. The phase change memory cell includes a separation layer formed in a predetermined region of a semiconductor substrate to define an active region. A switching device is formed in the active region. A lower interlayer dielectric layer is disposed on the substrate having the switching device. The switching device is electrically connected to a lower conductive bushing passing through the lower interlayer dielectric layer. A lower electrode is disposed on the lower interlayer dielectric layer and the lower electrode is in contact with the lower conductive vias. The lower electrode and the lower interlayer dielectric layer are covered by a molding layer. A phase change material pattern is disposed on the molding layer and the phase change material pattern is in contact with the lower electrode through a phase change material contact hole which passes through the molding layer. . An upper interlayer dielectric layer is disposed on the substrate having the phase change material pattern. The phase change material pattern is in direct contact with an upper conductive feedthrough which fills a metallization line contact hole through the upper interlayer dielectric layer. A metallization line is disposed on the upper interlayer dielectric layer and the metallization line is electrically connected to the upper conductive vias.

  Another exemplary embodiment of the invention provides a method of forming a phase change memory cell. The method includes forming a lower interlayer dielectric layer on a semiconductor substrate and forming a lower conductive vias through the lower interlayer dielectric layer. A pattern of phase change material is formed on the lower interlayer dielectric layer. The pattern of phase change material is formed so that it is in contact with the lower conductive bushing. An upper interlayer dielectric layer is formed on the phase change material pattern and the lower interlayer dielectric layer. A pattern is defined in the upper interlayer dielectric layer to form a metallization line contact hole that exposes a portion of the phase change material pattern. A conductive layer pattern is formed so that it is in direct contact with the exposed portion of the phase change material pattern through the metallization line contact hole.

  Yet another exemplary embodiment provides a method of forming a phase change memory cell. The method includes forming a lower interlayer dielectric layer on a semiconductor substrate and forming a lower conductive vias through the lower interlayer dielectric layer. A lower electrode is formed on the lower interlayer dielectric layer so that it is in contact with the lower conductive bushing. A molding layer is formed on the lower electrode and the lower interlayer dielectric layer. A pattern is formed in the molding layer to form a phase change material contact hole which exposes the lower electrode. A pattern of phase change material is formed on the molding layer. The pattern of phase change material is formed so that it is in contact with the lower electrode through the phase change material contact hole. An upper interlayer dielectric layer is formed on the substrate having the phase change material pattern. A pattern is defined in the upper interlayer dielectric layer to form a metallization line contact hole that exposes a portion of the phase change material pattern. A conductive layer pattern is formed so that it is in direct contact with the exposed portion of the phase change material pattern through the metallization line contact hole.

In the drawings.

  Figure 1 is a sectional view of a conventional phase change memory cell.

  Fig. 2A is a sectional view illustrating a pair of phase change memory cells according to an exemplary embodiment of the present invention.

  Fig. 2B is a sectional view illustrating a pair of phase change memory cells according to an exemplary embodiment of the present invention.

  Fig. 3A is a section illustrating a confined phase change memory cell according to an exemplary embodiment of the present invention.

  Fig. 3B is a section illustrating a confined phase change memory cell according to an exemplary embodiment of the present invention.

  Figures 4 to 8 are sections for illustrating methods of forming phase change memory cells in accordance with an exemplary embodiment of the present invention.

  Fig. 9 is a graphical representation illustrating switching characteristics of a conventional phase change memory cell and a phase change memory cell according to an exemplary embodiment of the present invention.

  The examples of embodiments of the present invention will now be described more fully in the following with reference to the accompanying drawings, which show examples of embodiments of the invention. The invention may, however, be embodied in various forms and should not be construed as limited to the embodiments presented herein. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. The same reference numbers are used to designate the same elements throughout the description.

  Fig. 2A is a vertical section of phase change memory cells according to an exemplary embodiment of the present invention, and Fig. 2B is a vertical section of phase change memory cells according to other examples. embodiments of the present invention.

  Referring to Figures 2A and 2B, it is noted that a separation layer 23 is formed in a predetermined region of a semiconductor substrate 21 to define an active region 23a. A first word line 27a and a second word line 27b are arranged to intersect the active region 23a at a higher level. The first and second word lines 27a and 27b are electrically isolated from the active region 23a by a gate dielectric layer 25. A common source region 29s is formed in the active region 23a between the first and second word lines 27a and 27b . A first drain region 29d 'is formed in the active region 23a which is adjacent to the first word line 27a and is placed opposite the common source region 29s, and a second drain region 29d' is formed in the region 23a, which is adjacent to the second word line 27b and is placed opposite the common source region 29s, with the result that the first word line 27a is arranged to intersect at a higher level a region of channel between the first drain region 29d 'and the common source region 29s, and the second word line 27b is arranged to intersect, at a higher level, a channel region between the second drain region 29d "and the common source region 29s. The first word line 27a, the common source region 29s and the first drain region 29d constitute a first switching device, i.e. a first access MOS transistor, and the second word line 27b, the common source region 29s and the second drain region 29d "constitute a second switching device, i.e. a second access MOS transistor.

  In other exemplary embodiments of the present invention, the first and second switching devices may be respectively a first bipolar transistor and a second bipolar transistor. In this case, the first and second word lines 27a and 27b may respectively be electrically connected to base regions of the first and second bipolar transistors.

  A lower interlayer dielectric layer 38 is formed on the substrate having the first and second switching devices. A bit line 35s is disposed in the lower interlayer dielectric layer 38. The bit line 35s is electrically connected to the common source region 29s through a source contact path 33s. The bit line 35s may be arranged parallel to the word lines 27a and 27b when considering a plan view. Alternatively, the bit line 35s may be disposed perpendicular to the word lines 27a and 27b when considering a plan view. On the other hand, when the first and second switching devices are the first and second bipolar transistors, as described above, the bit line 35s may be electrically connected to emitter regions of the first and second bipolar transistors.

  The first drain region 29d 'may be electrically connected to a first drain contact passage 33d' in the lower interlayer dielectric layer 38, and the second drain region 29d 'may be electrically connected to a second drain contact passage 33d'. in the lower interlayer dielectric layer 38. An upper surface of the first drain contact passage 33d 'may be in contact with a lower surface of a first drain pad 33d' in the lower interlayer dielectric layer 38, and a surface upper of the second drain contact passage 33d "may be in contact with a lower surface of a second drain pad 35d" in the lower interlayer dielectric layer 38.

  In addition, an upper surface of the first drain pad 35d 'may be in contact with a lower surface of a first lower conductive passage 39a in the lower interlayer dielectric layer 38, and an upper surface of the second drain pad 35d "may be in contact with a lower surface of a second lower conductive passage 39b in the lower interlayer dielectric layer 38. The upper surfaces of the first and second upper conductive vias 39a and 39b may have the same level as the upper surface of the lower interlayer dielectric layer 38.

  When the first and second switching devices are the first and second bipolar transistors, as described above, the first and second lower conductive vias 39a and 39b can be electrically connected respectively to a collector region of the first bipolar transistor and a region of collector of the second bipolar transistor.

  A first phase change material pattern 41a and a second phase change material pattern 41b are set on the lower interlayer dielectric layer 38. A first hard mask pattern 43a and a second hard mask pattern 43b may be stacked in in addition to the first and second phase change material patterns 41a and 41b, respectively. In this case, the first and second hard mask patterns 43a and 43b are respectively self-aligned with the first and second phase change material patterns 41a and 41b. Thus, the first hard mask pattern 43a may have the same width as the first phase change material pattern 41a, and the second hard mask pattern 43b may have the same width as the second phase change material pattern 41b . The first and second hard mask patterns 43a and 43b may be a layer of material having an etch selectivity to the first and second phase change material patterns 41a and 41b. For example, the first and second hard mask patterns 43a and 43b may include at least one layer selected from the group consisting of a silicon oxide layer, a silicon nitride layer, and an insulating metal oxide layer. The insulating metal oxide layer may be an aluminum oxide layer or a titanium oxide layer.

  As described above, upper electrodes, which are generally employed in conventional phase change memory cells, are not disposed on the phase change material patterns 41a and 41b of the phase change memory cells of the phase change memory cells. examples of embodiments of the present invention. The upper electrodes used in the conventional phase change memory cell may typically be a metal nitride layer, such as a titanium nitride layer. However, one of the difficulties with conventional phase-change memory cells is that the upper electrodes may be lifted during subsequent processes due to poor adhesion between the upper electrodes and the material patterns to be removed. phase change 41a and 41b. In an attempt to overcome the above difficulties, other conventional phase change memory cells have been designed in which an adhesion layer, such as a titanium layer, is interposed between the upper electrodes and the electrodes. phase change material 41a and 41b. The adhesion layer is formed in order to enhance the adhesion between the upper electrodes and the phase change material patterns 41a and 41b. Nevertheless, with these other conventional devices, metal atoms (eg titanium atoms) ) in the adhesion layer may diffuse into the phase change material patterns 41a and 41b, degrading the characteristics of the phase change material patterns 41a and 41b. However, with the phase change memory cells of the exemplary embodiments, the above-mentioned difficulties of conventional devices are avoided, because upper electrodes and adhesion layers are not used with the devices of the exemplary modes. of realization.

  Referring back to the exemplary embodiments of the present invention, it is noted that the first and second phase change material patterns 41a and 41b are arranged to be respectively in contact with the first and second lower conductive leads 39a and 39b. . Therefore, it is preferable that the first and second lower conductive vias 39a and 39b consist of a conductive material that does not react with the phase change material patterns 41a and 41b. For example, the first and second lower conductive vias 39a and 39b may consist of a metal layer, a metal nitride layer, or a metal silicide layer. In more detail, the first and second lower conductive vias 39a and 39b may include, but are not limited to, a tungsten layer (W), a titanium nitride (TiN) layer, a tantalum nitride layer (TaN ), a layer of tungsten nitride (WN), a layer of molybdenum nitride (MoN), a layer of niobium nitride (NbN), a layer of titanium nitride-silicon (TiSiN), a layer of titanium nitride aluminum (TiAlN), a titanium nitride - boron (TiBN) layer, a zirconium - silicon nitride (ZrSiN) layer, a silicon (WSiN) layer, a (WBN) layer, a zirconium nitride layer ( ZrAlN), a layer of molybdenum nitride (MoSiN), a (MoAlN), a (TaSiN), a (TaAlN), a titanium (Ti) layer, a (Mo) layer, a tantalum (Ta) layer, a layer of titanium (TiSi), a layer of silicide layer of molybdenum nitride layer of nitride layer of tantalum nitride tantalum nitride tungsten - tungsten nitride - boron - aluminum - silicon - aluminum - silicon-aluminum tantalum silicide molybdenum (TaSi), a layer of titanium - titanium oxynitride titanium oxynitride layer - tungsten oxynitride aluminum (WON), a tungsten (TiW), a (TiON), a (TiAlON) layer, a tantalum oxynitride layer (TaON) or a copper (Cu) layer.

  In addition, the first and second lower conductive vias 39a and 39b may be smaller in width than the first and second phase change material patterns 41a and 41b. Thus, contact areas between the lower conductive vias 39a and 39b and the phase change material patterns 41a and 41b may be smaller than the planar areas of the respective phase change material patterns 41a and 41b. Alternatively, the lower conductive vias 39a and 39b may have the same width as the phase change material patterns 41a and 41b.

  On the other hand, the phase change material patterns 41a and 41b may be a layer of material containing at least one of chalcogenide elements such as tellurium (Te) or selenium (Se). For example, the phase change material patterns 41a and 41b may be a chalcogenide layer such as a GeSbTe layer (hereinafter referred to as a GST layer).

  An upper interlayer dielectric layer 45 is formed on the substrate having hard mask patterns 43a and 43b. The upper interlayer dielectric layer 45 may be a silicon oxide layer, which is widely used as a conventional interlayer dielectric layer. Part of the first phase change material pattern 41a is in direct contact with a first conductive layer pattern through a first metallization line contact hole 45a which penetrates into the upper interlayer dielectric layer 45. In addition, a portion the second phase change material pattern 41b is in direct contact with a second conductive layer pattern through a second metallization line contact hole 45b which penetrates the upper interlayer dielectric layer 45. For example, as shown in FIG. 2A, the first and second phase change material patterns 41a and 41b may respectively be in direct contact with a first upper conductive passage 49a and a second upper conductive path 49b which pass through the upper interlayer dielectric layer 45. The first and second upper bushings 49a and 49b may be electrically connected to a metallization line 51 disposed on the upper interlayer dielectric layer 45. In this case, the metallization line 51 may be arranged to intersect, at a higher level, the first and second word lines 27a and 27a. 27b, as shown in Figure 2A. According to one variant, the first and second upper conductive feedthroughs 49a and 49b may respectively be electrically connected to first and second metallization lines which are arranged on the upper interlayer dielectric layer 45. In this case, the first and second metallization lines may be arranged parallel to the word lines 27a and 27b, and the bit line 35s can be arranged to intersect, at a higher level, the word lines 27a and 27b.

  In other exemplary embodiments of the present invention, the first and second phase change material patterns 41a and 41b may be in direct contact with a conductive layer pattern disposed on the upper interlayer dielectric layer 45; that is, a metallization line 51 ', as shown in FIG. 2B. In this case, the metallization line 51 'extends so as to pass through the upper interlayer dielectric layer 45. According to one variant, the first and second phase change material patterns 41a and 41b may be in direct contact with respectively the first and second metallization lines which are arranged on the upper interlayer dielectric layer 45. In this case, the first and second metallization lines may be arranged parallel to the word lines 27a and 27b, and the bit line 35s may be arranged way to cross, at a higher level, the word lines 27a and 27b.

  When the first and second hard mask patterns 43a and 43b are stacked respectively on the first and second phase change material patterns 41a and 41b, the upper conductive leads (49a and 49b of Fig. 2A) or the bit line ( 51 'of FIG. 2B) can pass through the hard mask patterns 43a and 43b and the upper interlayer dielectric layer 45 to be in direct contact with the phase change material patterns 41a and 41b. The contact areas between the upper conductive bushings 49a and 49b and the phase change material patterns 41a and 41b may be smaller than the planar areas of the phase change material patterns 41a and 41b. Similarly, the contact areas between the metallization line 51 'and the phase change material patterns 41a and 41b may be smaller than the planar areas of the phase change material patterns 41a and 41b.

  As shown in Fig. 2A, insulative contact spacer members 47 may be additionally incorporated between side walls of the upper conductive vias 49a and 49b and side walls of the metallization line contact holes 45a and 45b. In this case, the contact areas between the upper conductive vias 49a and 49b and the phase change material patterns 41a and 41b are further reduced. The insulating contact spacing elements 47 may consist of a silicon nitride layer or a silicon oxynitride layer. Similarly, the insulative contact spacer members 47 may be interposed between the metallization line 51 'and side walls of the metallization line contact holes 45a and 45b, as shown in FIG. 2b.

  It is preferred that the upper conductive bushings 49a and 49b be composed of a layer of material that does not react with the phase change material patterns 41a and 41b, because the upper conductive bushings 49a and 49b are in direct contact with each other. with the phase change material patterns 41a and 41b. For example, the upper conductive bushings 49a and 49b may include, but are not limited to, a tungsten (W) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a molybdenum nitride (MoN) layer, a niobium nitride (NbN) layer, a titanium nitride - silicon (TiSiN) layer, a titanium - aluminum nitride layer ( TiAlN), a titanium boron nitride (TiBN) layer, a zirconium - silicon nitride (ZrSiN) layer, a tungsten - silicon nitride (WSiN) layer, a tungsten boron nitride (WBN) layer , a zirconium - aluminum nitride (ZrAlN) layer, a molybdenum - silicon nitride (MoSiN) layer, a molybdenum - aluminum nitride (MoAlN) layer, a tantalum - silicon nitride (TaSiN) layer, a tantalum nitride-aluminum layer (TaAlN), a titanium (Ti) layer, a molybdenum layer (Mo), a tantalum layer (Ta), a titanium silicide layer (TiSi), a tantalum silicide layer (TaSi), a titanium-tungsten (TiW) layer, a titanium oxynitride layer ( TiON), a layer of aluminum titanium oxynitride (TiAlON), a tungsten oxynitride (WON) layer, a tantalum oxynitride layer (TaON) or a copper (Cu) layer.

  As described above, the lower surfaces of the phase change material patterns 41a and 41b are in direct contact with the lower conductive bushings 39a and 39b, and the upper surfaces of the phase change material patterns 41a and 41b are in contact with each other. direct contact with the upper conductive bushings 49a and 49b or with the metallization line 51 ', without the insertion of upper electrodes. In addition to the contact areas between the upper conductive bushings 49a and 49b (or the lower conductive bushings 39a and 39b) and the phase change material patterns 41a and 41b, the contact areas between the metallization line 51 'and the The phase change material patterns 41a and 41b may also be smaller than the planar areas of the phase change material patterns 41a and 41b. Therefore, when a write current IW 'flows through a selected one of the phase change material patterns 41a and 41b (e.g., the first phase change material pattern 41a), the current density d IW 'writing in a volume region of the selected phase change material pattern 41a is significantly increased in comparison with the prior art. As a result, the phase transition efficiency (i.e., thermal generation efficiency) of the selected phase change material pattern 41a of the phase change memory cell of the exemplary modes of realization, is increased. In other words, with the phase change memory cell of the exemplary embodiments of the present invention, the write efficiency of the memory cell is significantly increased and the thermal loss of the material pattern changes. The selected phase phase 41a is significantly reduced in comparison with conventional phase change memory cells, because upper electrodes with high thermal conductivity are not used with the exemplary embodiments.

  In the exemplary embodiment shown in Fig. 2A, when the insulating contact spacers 47 are set on the side walls of the metallization line contact holes 45a and 45b, the contact areas between the conductive bushings upper 49a and 49b and the phase change material patterns 41a and 41b may be smaller than the contact areas between the lower conductive vias 39a and 39b and the phase change material patterns 41a and 41b. In this case, if the write current IW 'flows through the first phase change material pattern 41a, a phase transition 2879013 22 occurs at an interface between the first lead conductor 49a and the first material pattern. with phase change 41a. Similarly, in the exemplary embodiment shown in Fig. 2B, when the insulating contact spacers 47 are set on the side walls of the metallization line contact holes 45a and 45b, the contact areas between the metallization line 51 'and the phase change material patterns 41a and 41b may be smaller than the contact areas between the lower conductive vias 39a and 39b and the phase change material patterns 41a and 41b. In this case, if the write current IW 'flows through the first phase change material pattern 41a, a phase transition occurs at an interface between the metallization line 51' and the first material change pattern. phase 41a.

  The above exemplary embodiments are applicable to both axis-shift phase-shift memory cells and to offset-axis phase change memory cells. Thus, a vertical center axis 45x 'of the first metallization line contact hole 45a may be in coincidence or spaced from a vertical center axis 39x' of the first lower conductive passage 39a. Similarly, a vertical center axis 45x "of the second metallization line contact hole 45b may be in coincidence or spaced from a vertical center axis 39x" of the second lower conductive passage 39b.

  In previous changes 3A and 3B. In

  2A and 2B, in addition, the exemplary embodiments are applicable to confined phase memory cells shown in the figures referring to FIGS. 3A and 3B, it will be noted that the switching device described with reference to FIGS. that is, the access MOS transistor or the bipolar access transistor may be formed in a semiconductor substrate 251. A lower interlayer dielectric layer 253 is provided on the substrate having the switching device. The switching device is electrically connected to a lower conductive vias 259 which passes through the lower interlayer dielectric layer 253. The lower conductive vias 259 may be made of the same material layer as the lower conductive vias 39a and 39b described with reference to Figs. 2A and 2B. A lower electrode 261 is disposed on the lower interlayer dielectric layer 253. The lower electrode 261 is arranged to cover the lower conductive bushing 259. Thus, the lower electrode 261 is electrically connected to the lower conductive bushing 259. Lower electrode 261 may be a metal nitride layer such as a titanium nitride layer.

  The lower electrode 261 and the lower interlayer dielectric layer 253 are covered by a molding layer 263. The molding layer 263 may be an insulating layer such as a silicon oxide layer. A pattern of phase change material 265 is disposed on the molding layer 263, and the phase change material pattern 265 is in direct contact with a portion of the lower electrode 261 through a contact hole of phase change 263h which penetrates into the molding layer 263. A vertical central axis 263x of the phase change material contact hole 263h may be spaced from a vertical central axis 259x of the lower conductive bushing 259, as shown in FIGS. Figures 3A and 3B. Alternatively, the vertical central axis 263x of the phase change material contact hole 263h may be identical to the vertical center axis 259x of the lower conductive bushing 259.

  An upper interlayer dielectric layer 267 is formed on the substrate having the phase change material pattern 265. A hard mask pattern 266 may be formed between the phase change material pattern 265 and the upper interlayer dielectric layer 267. Hard mask pattern 266 may be made of the same material layer as the hard mask patterns 41a and 41b described with reference to Figures 2A and 2B. A portion of the phase change material pattern 265 is in direct contact with a conductive layer pattern through a metallization line contact hole 267h which penetrates the upper interlayer dielectric layer 267 and the hard mask pattern 266. By for example, the phase change material pattern 265 may be in direct contact with an upper conductive lead 271 which passes through the upper interlayer dielectric layer 267 and the hard mask pattern 266, as shown in FIG. 3A. The upper conductive bushing 271 may be electrically connected to a metallization line 273 which is disposed on the upper interlayer dielectric layer 267. The upper conductive vias 271 may be made of the same material layer as the upper conductive vias 49a and 49b described in FIG. reference to FIGS. 2A and 2B.

  In other exemplary embodiments of the present invention, the phase change material pattern 265 may be in direct contact with a conductive layer pattern disposed on the upper interlayer dielectric layer 267. In other words, the The phase change material pattern 265 may be in direct contact with a metallization line 273 'disposed on the upper interlayer dielectric layer 267, as shown in FIG. 3B. In this case, the metallization line 273 'extends to penetrate the upper interlayer dielectric layer 267 and the hard mask pattern 266.

  A vertical centerline 267x of the metallization line contact hole 267h may be spaced from a vertical centerline 263x of the phase change material contact hole 263h. Alternatively, the vertical centerline 267x of the metallization line contact hole 267h may be identical to the vertical centerline 263x of the phase change material contact hole 263h.

  An insulative contact spacer 269 may be further disposed between side walls of the upper conductive passage 271 and side walls of the metallization line contact hole 267h. In this case, an area of contact between the upper conductive bushing 271 and the phase change material pattern 265 is further reduced. The insulating contact spacer 269 may be composed of a silicon nitride layer or a silicon oxynitride layer. Similarly, the insulative contact spacer members 269 may be interposed between the metallization line 273 'and the side walls of the metallization line contact hole 267h, as shown in FIG. 3B.

  Methods of forming phase change memory cells in accordance with exemplary embodiments of the present invention will now be described.

  Figures 4 to 8 are vertical sections illustrating methods of forming the phase change memory cells shown in Figure 2A, in accordance with exemplary embodiments of the invention.

  Referring to Figure 4, it is noted that a separation layer 23 is formed in a predetermined region of a semiconductor substrate 21 to define an active region 23a. A gate dielectric layer 25 is formed on the active region 23a, and a gate conductive layer is formed on the substrate having the gate dielectric layer 25. A pattern is defined in the gate conductive layer to form a first gate electrode 27a and a second gate electrode 27b, which are parallel to each other and arranged to intersect, at a higher level, the active region 23a. The first and second gate electrodes 27a and 27b may extend so as to respectively fulfill the functions of the first and second word lines.

  Impurity ions are implanted in the active region 23a using the word lines 27a and 27b and the separation layer 23 as ion implantation masks, thereby forming a common source region 29s and first and second regions The common source region 29s is formed in the active region 23a between the first and second word lines 27a and 27b, and the first drain region 29d 'is formed in the active region 23a. which is adjacent to the first word line 27a and located opposite the common source region 29s In addition, the second drain region 29d "is formed in the active region 23a which is adjacent to the second word line 27b and located next to the 29s common source area. The first word line 27a, the common source region 29s and the first drain region 29d 'constitute a first switching device, i.e. a first access MOS transistor. Similarly, the second word line 27b, the common source region 29s and the second drain region 29d "constitute a second switching device, i.e. a second access MOS transistor. In other exemplary embodiments, the first and second switching devices may be formed to have bipolar transistor structures, and a first lower interlayer dielectric layer 31 is then formed on the substrate having the first and second switching devices.

  Referring to FIG. 5, a pattern is formed in the first lower interlayer dielectric layer 31 to form a common source contact hole, a first drain contact hole and a second drain contact hole which respectively expose the common source region 29s, the first drain region 29d 'and the second drain region 29d ". A common source contact crossing 33s, a first drain contact passage 33d' and a second bushing crossing. 33d "drain contact are formed in the respective contact holes using a conventional method.

  A conductive layer is formed on the substrate having the contact vias 33s, 33d 'and 33d ". A pattern is defined in the conductive layer to form a bit line 33s, a first drain pad 35d' and a second drain pad 35d "which respectively cover the common source contact feedthrough 33s, the first drain contact bushing 33d 'and the second drain contact bushing 33d" .The bit line 35s can be formed parallel to the word lines 27a and 27b Alternatively, the bit line 35s may be formed to intersect, at a higher level, the word lines 27a and 27b.A second lower layer dielectric layer 37 is formed on the substrate having the bit line 35s and the first and second drain pads 35d 'and 35d ". The first and second lower interlayer dielectric layers 31 and 37 constitute a lower interlayer dielectric layer 38.

  Referring to Figure 6, it is noted that a pattern is formed in the second lower interlayer dielectric layer 37 to form first and second storage node contact holes which respectively expose the first and second drain pads respectively. 35d 'and 35d', a first lower conductive passage 39a and a second lower conductive passage 39b are respectively formed in the first and second storage node contact holes, and a layer of phase change material 41 is then formed on the substrate having the lower conductive bushings 39a and 39b The layer of phase change material 41 may consist of a layer of material containing at least one of chalcogenide elements such as tellurium (Te) or selenium (Se) For example, the layer of phase change material 41 may consist of a chalcogenide layer such as a layer of GST. s, the lower conductive vias 39a and 39b are in direct contact with the layer of phase change material 41. Therefore, the lower conductive vias 39a and 39b may consist of a conductive layer which does not react with the layer of phase-change material 41. For example, the lower conductive vias 39a and 39b may include, but are not limited to, a tungsten layer (W), a titanium nitride (TiN) layer, a tantalum nitride layer (TaN), a layer of tungsten nitride (WN), a layer of molybdenum nitride (MoN), a layer of niobium nitride (NbN), a layer of titanium nitride silicon (TiSiN), a layer of nitride of titanium - aluminum (TiAlN), a titanium nitride - boron (TiBN) layer, a zirconium - silicon nitride (ZrSiN) layer, a tungsten silicon nitride (WSiN) layer, a boron - tungsten nitride layer (WBN), a layer of aluminum zirconium nitride (ZrAlN), a layer of molybdenum - silicon nitride (MoSiN), a layer of aluminum molybdenum nitride (MoAlN), a layer of tantalum - silicon nitride (TaSiN), a layer of nitride of tantalum - aluminum (TaAlN), a titanium (Ti) layer, a molybdenum (Mo) layer, a tantalum (Ta) layer, a titanium silicide (TiSi) layer, a tantalum silicide (TaSi) layer , a titanium - tungsten (TiW) layer, a titanium oxynitride (TiON) layer, a titanium - aluminum oxynitride (TiAlON) layer, a tungsten oxynitride (WON) layer, a tantalum oxynitride (TaON) or a layer of copper (Cu).

  A hard mask layer may be further formed on the layer of phase change material 41. The hard mask layer may be formed of an insulating layer having an etch selectivity to the layer of change material. For example, the hard mask layer may consist of a layer of material including at least one layer selected from the group consisting of a silicon oxide layer, a silicon nitride layer, and a layer of silicon oxide. insulating metal oxide. The silicon oxide layer may be formed of a tetraethylorthosilicate (TEOS) layer, and the metal oxide layer may be formed of an aluminum oxide layer or an oxide layer of titanium. A pattern is defined in the hard mask layer to form a first hard mask pattern 43a and a second hard mask pattern 43b respectively on the first and second lower conductive leads 39a and 39b.

  Referring to Fig. 7, it is noted that the phase change material layer 41 is etched using the hard mask patterns 43a and 43b as etch masks, thereby forming a first phase change material pattern. 41a and a second phase change material pattern 41b which are in direct contact with the first and second lower conductive leads 39a and 39b, respectively. Alternatively, the phase change material patterns 41a and 41b may be formed using a photolithography process, without using the hard mask patterns 43a and 43b.

  An upper interlayer dielectric layer 45 is formed on the substrate having hard mask patterns 43a and 43b. The upper interlayer dielectric layer may consist of a silicon oxide layer. A pattern is formed in the upper interlayer dielectric layer 45 and the hard mask patterns 43a and 43b, to form a first metallization line contact hole 45a and a second metallization line contact hole 45b that respectively expose the first and second phase change material patterns 41a and 41b. The first metallization line contact hole 45a may be formed to have a vertical central axis which is spaced from a vertical central axis of the first lower conductive passage 39a. Similarly, the second metallization line contact hole 45b may be formed to have a vertical central axis spaced from a vertical central axis of the second conductive passage 39b.

  The first and second phase change material patterns 41a and 41b may suffer etch damage during an etching process to form the metallization line contact holes 45a and 45b.

  When the etching damage that is suffered is severe, characteristics of the phase change material patterns 41a and 41b can be degraded. Therefore, the etching process for forming the metallization line contact holes 45a and 45b is preferably performed using an etching technique which is capable of minimizing the etch damage caused to the phase change material patterns 41a and 41b. To minimize the etching damage, it is preferable that the etching process to form the metallization line contact holes 45a and 45b has a high etch selectivity of at least 5. In other words, it is preferable to that the etching rate of the upper interlayer dielectric layer 45 and hard mask patterns 43a and 43b is 5 times higher than that of the phase change material patterns 41a and 41b.

  In the exemplary embodiments of the present invention, when the upper interlayer dielectric layer 45 and the hard mask patterns 43a and 43b are made of a silicon oxide layer and the phase change material patterns 41a and 41b consist of a GST layer, the etching process for forming the metallization line contact holes 45a and 45b can be accomplished using a first main etching gas of a CXHYFZ system and a second main etching gas of a CvF system, at a pressure of 1.3 to 13 Pa. In addition, the etching process can be accomplished using a plasma power of 300 to 1000 W. In these exemplary embodiments, the first main etching gas may be a gas consisting of CHF3, CH2F2 or CH3F, and the second main etching gas may be a gas consisting of CF4, C4F6, C4F8 or C5F8. In addition, the etching process may be accomplished with at least one of argon (Ar), nitrogen (N2) and oxygen (02) gas in addition to the first and second major etching gases. In this case, the total flow rate of the first and second main etching gases may be at least 10% of the total flow rate of all the gases used in the etching process.

  Referring to Figure 8, it is noted that a conductive layer is formed on the substrate having the metallization line contact holes 45a and 45b, and a thickness reduction etch is applied to the conductive layer to An upper surface of the upper interlayer dielectric layer 45 is shown. As a result, a first upper conductive passage 49a and a second upper conductive passage 49b are respectively formed in the first and second metallization line contact holes 45a and 45b.

  The first and second upper conductor bushings 49a and 49b are formed to be in direct contact with the first and second phase change material patterns 41a and 41b, respectively. Therefore, the upper conductive bushings 49a and 49b may also consist of a conductive layer that does not react with the phase change material patterns 41a and 41b. For example, the upper conductive bushings 49a and 49b may include, but are not limited to, a tungsten (W) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN), a layer of molybdenum nitride (MoN), a layer of niobium nitride (NbN), a layer of titanium nitride silicon (TiSiN), a layer of titanium-aluminum nitride (TiAlN), titanium - boron nitride (TiBN) layer, zirconium - silicon nitride (ZrSiN) layer, tungsten silicon nitride (WSiN) layer, tungsten boron nitride (WBN) layer, zirconium nitride-aluminum (ZrAlN), a layer of molybdenum-silicon nitride (MoSiN), a layer of aluminum molybdenum nitride (MoAlN), a tantalum-silicon nitride layer (TaSiN), a tantalum nitride layer - aluminum (TaAlN), a layer of titanium (Ti), a layer of molybdenum (Mo), a layer of tantalum (Ta), a titanium silicide layer (TiSi), a tantalum silicide layer (TaSi), a titanium - tungsten (TiW) layer, a titanium oxynitride layer (TiON), a titanium oxynitride (TiAlON), a tungsten oxynitride (WON) layer, a tantalum oxynitride (TaON) layer or a copper (Cu) layer.

  In other exemplary embodiments of the present invention, insulative contact spacer members 47 may be formed on side walls of the metallization line contact holes 45a and 45b prior to depositing the conductive layer to form the conductive layers. first and second upper conductive bushings 49a and 49b. The insulating contact spacing elements 47 may consist of a silicon nitride layer or a silicon oxynitride layer.

  Then, a metallization layer is formed on the substrate having the upper conductive vias 49a and 49b, and a pattern is defined in the metallization layer to form a metallization line 51 which is electrically connected to the first and second upper conductive vias 49a and 49b.

  In yet other exemplary embodiments, the process of forming the upper conductive vias 49a and 49b may be omitted. In this case, the metallization line 51 is shaped to be in direct contact with the first and second phase change material patterns 41a and 41b through the metallization line contact holes 45a and 45b.

  Reference will now be made to FIGS. 3A and 3B of methods for forming confined phase change memory cells in accordance with exemplary embodiments of the present invention.

  Referring again to FIGS. 3A and 3B, it is noted that a switching device is formed in a semiconductor substrate 251. The switching device can be formed using processes identical to those described with reference to FIG. lower interlayer dielectric layer 253 is formed on the substrate having the switching device. A lower conductive bushing 259 is formed to pass through the lower interlayer dielectric layer 253. The lower conductive bushing 259 is electrically connected to the switching device. A lower electrode 261 is formed on the lower interlayer dielectric layer 253. The lower electrode 261 is formed to be in contact with the lower conductive bushing 259. A molding layer 263 is formed on the substrate having the lower electrode 261. The molding layer 263 may consist of an insulating layer such as a silicon oxide layer.

  A pattern is defined in the molding layer 263 to form a phase change material contact hole 263h that exposes a portion of the lower electrode 261. The phase change material contact hole 263h can be formed so as to have a vertical central axis 263x spaced from a vertical central axis 259x of the lower conductive bushing 259. A phase change material pattern 265 is formed on the molding layer 263 so as to fill the contact hole with phase change material 263h. In addition, a hard mask pattern 266 may also be formed on the phase change material pattern 265. The hard mask pattern 266 and the phase change material pattern 265 may be formed in a manner identical to that described above with reference to FIGS. 6 and 7. In addition, an upper interlayer dielectric layer 267 is formed on the substrate having the hard mask pattern 266.

  A pattern is defined in the upper interlayer dielectric layer 267 and the hard mask pattern 265 to form a metallization line contact hole 267h that exposes a portion of the phase change material pattern 265. An etching process for forming the metallization line contact hole 267h can be accomplished using the etching technique described with reference to FIG. 7. The metallization line contact hole 267h can be formed to have a vertical central axis 267x spaced apart from each other. 263x vertical central axis of the phase change material contact hole 263h. An insulative contact spacer 269 may be formed on a side wall of the metallization line contact hole 267h. The insulating contact spacer 269 may be an insulating layer such as a silicon oxide layer or a silicon oxynitride layer. An upper conductive bushing 271 is then formed to fill the metallization line contact hole 267h. The upper conductive bushing 271 may be formed using the method of forming the upper conductive bushings 49a and 49b shown in Fig. 8. As a result, a phase change material pattern 265 is formed to be in direct contact with each other. with the upper conductive bushing 271 passing through the upper interlayer dielectric layer 267 and the hard mask pattern 266. A metallization line 273 is then formed on the upper interlayer dielectric layer 267. The metallization line 273 may be formed to cover the upper conductive bushing 271.

  In other exemplary embodiments of the present invention, the formation process of the upper conductive bushing 271 may be omitted. In this case, a metallization line 273 ', which is in direct contact with the phase change material pattern 265, is formed on the upper interlayer dielectric layer 267, as shown in FIG. 3B.

<Examples>

  Fig. 9 is a graphical representation showing the writing characteristics (programming characteristics) of data storage elements according to the prior art and an exemplary embodiment of the present invention. In Fig. 9, a horizontal axis designates a write voltage Vw which is applied between an upper conductive bushing and a lower conductive bushing of each of the data storage elements, and a vertical axis denotes an electrical resistance R of each of the elements. data storage. In addition, in Fig. 9, data indicated by a reference numeral 101 corresponds to the programming characteristics of the conventional data storage element, and data indicated by a reference numeral 103 correspond to the programming characteristics of the data storage element. data storage element of an exemplary embodiment of the present invention.

  The data storage elements presenting the measurement results of Figure 9 were fabricated using the process conditions described in the following Table.

[Board]

  PRIOR ART Present Invention Conductive Crossing Material TiN layer Lower TiN layer Diameter 55 nm 55 nm Pattern of material to material GST layer GST layer phase change Diameter 680 nm 680 nm Thickness 100 nm 100 nm Upper electrode TiN layer - Pattern hard mask SiO layer SiO layer Dielectric layer SiO layer Upper interlayer SiO layer Conductive feedthrough Material W layer Top W layer Diameter 240 nm 240 nm With the conventional data storage element envisioned above, the Upper electrode was formed to have the same width (diameter) as the phase change material pattern. Thus, the upper electrode was self-aligned with the phase change material pattern. In this case, the upper conductive bushing was formed to contact the upper electrode.

  However, with the data storage element according to the exemplary embodiments of the present invention, the hard mask pattern consisted of a silicon oxide (SiO) layer and the hard mask pattern was self-contained. aligned with the material pattern at 2879013 change of phase. Thus, the hard mask pattern was formed to have the same width (diameter) as the phase change material pattern. In this case, the upper conductive bushing was formed to pass through the hard mask pattern. In other words, the upper conductive bushing was formed to be in direct contact with the phase change material pattern.

  Further, in the manufacture of the data storage element according to the exemplary embodiments of the present invention, a metallization line contact hole exposing a portion of the phase change material pattern was formed by successively defining patterns in the upper interlayer dielectric layer and in the hard mask pattern, using an oxide etching process. The oxide etching process was accomplished using a Magnetic Enhanced Reactive Ion Etch (MERIE) device at a pressure of 1.3 Pa and a plasma power of 500 W. In this case, a CHF3 gas and a CF4 gas were used as the main etching gas, and the flow rates of the CHF3 gas and CF4 gas were respectively 40 cm3 / min and 10 cm3 / min, in normalized values.

  In Fig. 9, the write voltage VW at each data point was applied to the data storage element for about 50 ns (nanoseconds).

  Referring to FIG. 9, it should be noted that the conventional data storage element exhibited an inset state resistance of about 1 x 104 ohms after applying a write voltage Vw of about 0 , 5 V for 500 ns, and the conventional data storage element exhibited a resistance in the restored state of about 1 x 106 ohms after applying a write voltage VW of about 1.2 V during 500 ns.

  On the other hand, the data storage element of the exemplary embodiments of the present invention had a resistance in the set state of about 1 x 104 ohms after applying a low write voltage Vw of about 0.3 V for 500 ns, and the data storage element of the present invention exhibited a high restored resistance of about 4 x 106 ohms, after applying a voltage of low write Vw of about 1.1 V for 500 ns.

  In conclusion, the data storage element according to the exemplary embodiments of the present invention had relatively lower start-up / restore voltages and relatively higher resistance in the restored state compared to the storage element of the present invention. classical data.

  In accordance with the exemplary embodiments of the present invention described above, a phase change material pattern is in direct contact with an upper conductive feedthrough or a metallization line that penetrates into an upper interlayer dielectric layer without the insertion of an upper electrode. Therefore, the density of a write current flowing through the volume region of the phase change material pattern of the phase change memory cell of the exemplary embodiments is increased, which also to enhance the write efficiency of the phase change memory cell.

  It goes without saying that many modifications can be made to the device and method described and shown, without departing from the scope of the invention.

Claims (43)

  A phase change memory cell, characterized in that it comprises a lower interlayer dielectric layer (38) formed on a semiconductor substrate (21); a lower conductive bushing (39a, 39b) passing through the lower interlayer dielectric layer (38); a phase change material pattern (41a, 41b) disposed on the lower interlayer dielectric layer (38) for contacting the lower conductive lead (39a, 39b); an upper interlayer dielectric layer (45) covering the phase change material pattern (41a, 41b) and the lower interlayer dielectric layer (38); and a conductive layer pattern (49a, 49b) disposed in direct contact with the phase change material pattern (41a, 41b), through a metallization line contact hole (45a, 45b) that penetrates the layer upper interlayer dielectric (45).   The phase change memory cell according to claim 1, characterized in that the lower conductive passage (39a, 39b) has a width smaller than that of the phase change material pattern (41a, 41b).   The phase change memory cell according to claim 1, characterized in that it further comprises an insulative contact spacer (47) interposed between a side wall of the conductive layer pattern (49a, 49b) and a side wall of the metallization line contact hole (45a, 45b).   The phase change memory cell according to claim 1, characterized in that it further comprises a hard mask pattern (43a, 43b) interposed between the upper interlayer dielectric layer (45) and an upper surface of the ground pattern. phase change material (41a, 41b); and in that the conductive layer pattern (49a, 49b) penetrates into the upper interlayer dielectric layer (45) and the hard mask pattern (43a, 43b).   The phase change memory cell of claim 4, characterized in that the hard mask pattern (43a, 43b) comprises at least one layer selected from a group consisting of a silicon oxide layer, a layer of silicon nitride and an insulating metal oxide layer.   A phase change memory cell according to claim 1, characterized in that the lower conductive passage (39a, 39b) has a vertical central axis (39x ', 39x ") spaced from a vertical central axis (45x', 45x ") of the conductive layer pattern (49a, 49b) in the metallization line contact hole (45a, 45b).   A phase change memory cell characterized by comprising a separation layer (23) formed in a predetermined region of a semiconductor substrate (21) for defining an active region (23a); a switching device formed in the active region (23a); a lower interlayer dielectric layer (38) formed on the substrate (21) having the switching device; a lower conductive bushing (39a, 39b) penetrating the lower interlayer dielectric layer (38), the lower conductive bushing (39a, 39b) being electrically connected to the switching device; a phase change material pattern (41a, 41b) disposed on the lower interlayer dielectric layer (38) in contact with the lower conductive bushing (39a, 39b); an upper interlayer dielectric layer (45) covering the phase change material pattern (41a, 41b) and the lower interlayer dielectric layer (38); and a metallization line (51 ') disposed on the upper interlayer dielectric layer (45) in direct contact with the phase change material pattern (41a, 41b) through a metallization line contact hole (45a, 45b) ) which enters the upper interlayer dielectric layer (45).   The phase change memory cell according to claim 7, characterized in that it further comprises an insulative contact spacer (47) interposed between the metallization line (51 ') in the contact hole. metallization line (45a, 45b) and a side wall of the metallization line contact hole (45a, 45b).   The phase change memory cell of claim 7, characterized in that it further comprises a hard mask pattern (43a, 43b) interposed between the upper interlayer dielectric layer (45) and an upper surface of the ground pattern. phase change material (4la, 41b); and in that the metallization line (51 ') penetrates into the upper interlayer dielectric layer (45) and the hard mask pattern (43a, 43b).   The phase change memory cell according to claim 9, characterized in that the hard mask pattern (43a, 43b) comprises at least one layer selected from a group consisting of a silicon oxide layer, a layer of silicon nitride and an insulating metal oxide layer.   The phase change memory cell according to claim 7, characterized in that it further comprises: an upper conductive passage (49a, 49b) filling the metallization line contact hole (45a, 45b) which enters the upper interlayer dielectric layer (45) and is in direct contact with the phase change material pattern (41a, 41b).   The phase change memory cell according to claim 11, characterized in that it further comprises an insulative contact spacer (47) interposed between a side wall of the metallization line contact hole (45a). 45b) and a side wall of the upper conductive bushing (49a, 49b).   The phase change memory cell according to claim 11, characterized in that it further comprises a hard mask pattern (43a, 43b) interposed between the upper interlayer dielectric layer (45) and an upper surface of the ground pattern. phase change material (41a, 41b); and in that the upper conductive bushing (49a, 49b) passes through the upper interlayer dielectric layer (45) and the hard mask pattern (43a, 43b).   14. A phase change memory cell according to claim 11, characterized in that the upper conductive passage (49a, 49b) is composed of a layer selected from a group comprising a tungsten layer (W), a nitride layer of titanium (TiN), a layer of tantalum nitride (TaN), a layer of tungsten nitride (WN), a layer of molybdenum nitride (MoN), a layer of niobium nitride (NbN), a layer of nitride titanium - silicon (TiSiN), a titanium - aluminum nitride layer (TiAlN), a boron titanium nitride (TiBN) layer, a zirconium - silicon nitride (ZrSiN) layer, a tungsten nitride layer - silicon (WSiN), a tungsten boron nitride (WBN) layer, a zirconium aluminum nitride (ZrAlN) layer, a molybdenum nitride silicon (MoSiN) layer, a molybdenum aluminum nitride (MoAlN) layer, a layer of tantalum-silicon nitride (TaSiN), a layer of nitride tantalum - aluminum (TaAlN), a titanium (Ti) layer, a molybdenum (Mo) layer, a tantalum (Ta) layer, a titanium silicide (TiSi) layer, a tantalum silicide (TaSi) layer , a titanium - tungsten (TiW) layer, a titanium oxynitride (TiON) layer, a titanium - aluminum oxynitride (TiAlON) layer, a tungsten oxynitride (WON) layer, a tantalum oxynitride (TaON) or a layer of copper (Cu).   15. A phase change memory cell, characterized in that it comprises a lower interlayer dielectric layer (253) formed on a semiconductor substrate (251); a lower conductive bushing (259) passing through the lower interlayer dielectric layer (253); a lower electrode (261) disposed on the lower interlayer dielectric layer (253) in contact with the lower conductive bushing (259); a molding layer (263) covering the lower electrode (261) and the lower interlayer dielectric layer (253); a phase change material pattern (265) formed on the molding layer (263), the phase change material pattern (265) being in contact with the lower electrode (261) through a contact hole of phase change material (263h) entering the molding layer (263); an upper interlayer dielectric layer (267) formed on the substrate having the phase change material pattern (265); and a conductive layer pattern (271) that is in direct contact with the phase change material pattern (265) through a metallization line contact hole (267h) that penetrates the upper interlayer dielectric layer (267) .   16. A phase change memory cell according to claim 15, characterized in that it further comprises an insulating contact spacing element (269) interposed between a side wall of the metallization line contact hole (267h). and the conductive layer pattern (271) in the metallization line contact hole (267h).   The phase change memory cell according to claim 15, characterized in that it further comprises a hard mask pattern (266) interposed between the phase change material pattern (265) and the interlayer dielectric layer superior (267); and in that the conductive layer pattern (271) passes through the upper interlayer dielectric layer (267) and the hard mask pattern (266).   18. A phase change memory cell, characterized in that it comprises a separation layer formed in a predetermined region of a semiconductor substrate (251) for defining an active region; a switching device formed in the active region; a lower interlayer dielectric layer (253) formed on the substrate (251) having the switching device; a lower conductive vias (259) penetrating the lower interlayer dielectric layer (253), the lower conductive vias (259) being electrically connected to the switching device; a lower electrode (261) disposed on the lower interlayer dielectric layer (253) in contact with the lower conductive bushing (259); a molding layer (263) covering the lower electrode (261) and the lower interlayer dielectric layer (253); a phase change material pattern (265) formed on the molding layer (263), the phase change material pattern (265) being in contact with the lower electrode (261) through a contact hole of phase change material (263h) entering the molding layer (263); an upper interlayer dielectric layer (267) formed on the substrate having the phase change material pattern (265); and a metallization line (273 ') disposed on the upper interlayer dielectric layer (267) in direct contact with the phase change material pattern (265) through a metallization line contact hole (267h) which enters the upper interlayer dielectric layer (267).   The phase change memory cell according to claim 18, characterized in that it further comprises an insulative contact spacer (269) interposed between the metallization line (273 ') in the contact hole of metallization line (267h) and a side wall of the metallization line contact hole (267h).   The phase change memory cell according to claim 18, characterized in that it further comprises a hard mask pattern (266) interposed between the phase change material pattern (265) and the upper interlayer dielectric layer (267); and in that the metallization line (273 ') passes through the upper interlayer dielectric layer (267) and the hard mask pattern (266).   The phase change memory cell according to claim 18, characterized in that it further comprises an upper conductive passage (271) filling the metallization line contact hole (267h) which penetrates into the upper interlayer dielectric layer (267) and is in direct contact with the phase change material pattern (265).   22. A phase change memory cell according to claim 21, characterized in that it further comprises an insulating contact spacing element (269) interposed between a side wall of the metallization line contact hole (267h). and a side wall of the upper conductive bushing (271).   The phase change memory cell according to claim 21, characterized in that it further comprises a hard mask pattern (266) interposed between the phase change material pattern (265) and the upper interlayer dielectric layer (267); and in that the upper conductive bushing (271) passes through the upper interlayer dielectric layer (267) and the hard mask pattern (266).   24. A phase change memory cell according to claim 21, characterized in that the upper conductive passage (271) consists of a layer selected from a group comprising a layer of tungsten (W), a layer of titanium nitride. (TiN), a layer of tantalum nitride (TaN), a layer of tungsten nitride (WN), a layer of molybdenum nitride (MoN), a layer of niobium nitride (NbN), a layer of titanium nitride silicon (TiSiN), a titanium - aluminum nitride layer (TiAlN), a boron titanium nitride (TiBN) layer, a zirconium - silicon nitride (ZrSiN) layer, a tungsten - silicon nitride layer ( WSiN), a tungsten boron nitride (WBN) layer, a zirconium - aluminum nitride layer (ZrAlN), a molybdenum - silicon nitride layer (MoSiN), a molybdenum - aluminum nitride layer (MoAlN) , a layer of tantalum-silicon nitride (TaSiN), a nitride layer of tantalum - aluminum (TaAlN), a layer of titanium (Ti), a layer of molybdenum (Mo), a layer of tantalum (Ta), a layer of titanium silicide (TiSi), a layer of tantalum silicide (TaSi ), a titanium - tungsten (TiW) layer, a titanium oxynitride (TiON) layer, a titanium - aluminum oxynitride layer (TiAlON), a tungsten oxynitride (WON) layer, a tantalum oxynitride (TaON) or a layer of copper (Cu).   25. A method of forming a phase change memory cell, characterized in that it comprises the steps of forming a lower interlayer dielectric layer (38) on a semiconductor substrate (21); forming a lower conductive bushing (39a, 39b) passing through the lower interlayer dielectric layer (38); forming a phase change material pattern (41a, 41b) on the lower interlayer dielectric layer (38), the phase change material pattern (41a, 41b) being in contact with the lower conductive bushing (39a, 39b) ; forming an upper interlayer dielectric layer (45) to cover the phase change material pattern (41a, 41b) and the lower interlayer dielectric layer (38); defining a pattern in the upper interlayer dielectric layer (45) to form a metallization line contact hole (45a, 45b) that exposes a portion of the phase change material pattern (41a, 41b); and forming a conductive layer pattern (49a, 49b) which is in direct contact with the exposed portion of the phase change material pattern (41a, 41b) through the metallization line contact hole (45a, 45b) .   The method of claim 25, characterized in that it further comprises forming a separation layer (23) in a predetermined region of the semiconductor substrate (21) to define an active region (23a), the separating (23) being formed prior to formation of the lower interlayer dielectric layer (38); and forming a switching device on the active region (23a); and in that the lower conductive bushing (39a, 39b) is electrically connected to the switching device.   The method of claim 25, further comprising forming a hard mask pattern (43a, 43b) self-aligned with the phase change material pattern (41a, 41b) on the pattern of phase change material, prior to formation of the upper interlayer dielectric layer (45); and in that the metallization line contact hole (45a, 45b) is formed to pass through the upper interlayer dielectric layer (45) and the hard mask pattern (43a, 43b).   The method of claim 25, further comprising forming an insulative contact spacer (47) on a side wall of the metallization line contact hole (45a, 45b).   The method of claim 25, characterized in that forming the conductive layer pattern comprises the steps of: forming a metallization layer that fills the metallization line contact hole (45a, 45b) and covers the dielectric layer upper interlayer (45); and defining a pattern in the metallization layer to form a metallization line (51 ') which covers the metallization line contact hole (45a, 45b).   The method of claim 25, characterized in that forming the conductive layer pattern comprises the steps of: forming an upper conductive lead (49a, 49b) that fills the metallization line contact hole (45a, 45b) and is in direct contact with the exposed portion of the phase change material pattern (41a, 41b); forming a metallization layer to cover the upper conductive passage (49a, 49b) and the upper interlayer dielectric layer (45); and defining a pattern in the metallization layer to form a metallization line (51 ') which is electrically connected to the upper conductive passage (49a, 49b).   31. The method of claim 30, characterized in that the upper conductive passage (49a, 49b) consists of a layer selected from a group comprising a tungsten layer (W), a layer of titanium nitride (TiN), a layer of tantalum nitride (TaN), a layer of tungsten nitride (WN), a layer of molybdenum nitride (MoN), a layer of niobium nitride (NbN), a layer of titanium nitride-silicon (TiSiN ), a titanium - aluminum nitride (TiAlN) layer, a titanium boron nitride (TiBN) layer, a zirconium - silicon nitride (ZrSiN) layer, a tungsten - silicon nitride (WSiN) layer, a layer of tungsten boron nitride (WBN), a layer of zirconium - aluminum nitride (ZrAlN), a layer of molybdenum - silicon nitride (MoSiN), a layer of molybdenum - aluminum nitride (NoA1N), a layer of of tantalum-silicon nitride (TaSiN), a layer of tantalum-aluminum nitride (TaAl 1N), a titanium (Ti) layer, a molybdenum (Mo) layer, a tantalum (Ta) layer, a titanium silicide (TiSi) layer, a tantalum silicide (TaSi) layer, a titanium-tungsten (TiW), a titanium oxynitride (TiON) layer, a titanium aluminum oxynitride layer (TiAlON), a tungsten oxynitride (WON) layer, a tantalum oxynitride layer (TaON) ) or a layer of copper (Cu).   32. The method of claim 25, characterized in that when the upper interlayer dielectric layer (45) is made of a silicon oxide layer, the metallization line contact hole (45a, 45b) is formed by etching the upper interlayer dielectric layer (45) using a first main etching gas consisting of a CXHYFZ system and a second main etching gas consisting of a CVFW system, as the main etching gas.   Method according to claim 25, characterized in that the metallization line contact hole (45a, 45b) is formed so as to have a vertical central axis (45x ', 45x ") spaced from a vertical central axis ( 39x ', 39x ") of the lower conductive bushing (39a, 39b).   34. A method of forming a phase change memory cell, characterized in that it comprises the steps of forming a lower interlayer dielectric layer (253) on a semiconductor substrate (251); forming a lower conductive bushing (259) passing through the lower interlayer dielectric layer (253); forming a lower electrode (261) on the lower interlayer dielectric layer (253), the lower electrode (261) being in contact with the lower conductive vias (259); forming a molding layer (263) for covering the lower electrode (261) and the lower interlayer dielectric layer (253); defining a pattern in the molding layer (263) to form a phase change material contact hole (263h) which exposes the lower electrode (261); forming a phase change material pattern (265) on the molding layer (263), the phase change material pattern (265) being formed to contact the lower electrode (261) through the phase change material contact hole (263h); forming an upper interlayer dielectric layer (267) on the substrate having the phase change material pattern (265); defining a pattern in the upper interlayer dielectric layer (267) to form a metallization line contact hole (267h) that exposes the phase change material pattern (265); and forming a conductive layer pattern (271) that is in direct contact with the phase change material pattern (265) through the metallization line contact hole (267h).   The method of claim 34, further comprising forming a hard mask pattern (266) on the phase change material pattern (265) prior to forming the upper interlayer dielectric layer. (267), the hard mask pattern (266) being self-aligned with the phase change material pattern (265); and in that the metallization line contact hole (267h) is formed to pass through the upper interlayer dielectric layer (267) and the hard mask pattern (266).   The method of claim 34, further comprising forming an insulative contact spacer (269) on a side wall of the metallization line contact hole (267h).   37. The method of claim 36, characterized in that the insulating contact spacing element (269) consists of a silicon nitride layer or a silicon oxynitride layer.   The method of claim 34, characterized in that forming the conductive layer pattern comprises the steps of: forming a metallization layer that fills the metallization line contact hole (267h) and covers the upper interlayer dielectric layer (267); and defining a pattern in the metallization layer to form a metallization line (273 ') which covers the metallization line contact hole (267h).   The method of claim 34, characterized in that forming the conductive layer pattern comprises the steps of: forming an upper conductive lead (271) that fills the metallization line contact hole (267h) and is in contact direct with the phase change material pattern (265); forming a metallization layer to cover the upper conductive passage (271) and the upper interlayer dielectric layer (267); and defining a pattern in the metallization layer to form a metallization line (273) that is electrically connected to the upper conductive passage (271).   40. The method of claim 39, characterized in that the upper conductive passage (271) consists of a layer selected from a group comprising a layer of tungsten (W), a layer of titanium nitride (TiN), a layer of tantalum nitride (TaN), a layer of tungsten nitride (WN), a layer of molybdenum nitride (MoN), a layer of niobium nitride (NbN), a layer of titanium nitride silicon (TaSiN), a titanium nitride - aluminum layer (TiAlN), a titanium nitride - boron (TiBN) layer, a zirconium - silicon nitride (ZrSiN) layer, a tungsten silicon nitride (WSiN) layer, a nitride layer Tungsten - boron (WBN), a zirconium - aluminum nitride (ZrAlN) layer, a molybdenum - silicon nitride (MoSiN) layer, a molybdenum aluminum nitride (MoAlN) layer, a tantalum nitride layer - silicon (TaSiN), a layer of tantalum-aluminum nitride (TaAlN), a titanium dioxide (Ti), a layer of molybdenum (Mo), a tantalum layer (Ta), a titanium silicide layer (TiSi), a tantalum silicide layer (TaSi), a titanium-tungsten layer ( TiW), a titanium oxynitride (TiON) layer, a titanium-aluminum oxynitride (TiAlON) layer, a tungsten oxynitride (WON) layer, a tantalum oxynitride (TaON) layer or a copper layer (Cu).   41. The method of claim 34, characterized in that when the upper interlayer dielectric layer (267) is made of a silicon oxide layer, the metallization line contact hole (267h) is formed by etching the layer. upper interlayer dielectric (267) using a first main etching gas consisting of a CXHyFZ system and a second main etching gas consisting of a CvF 2 system as the main etching gas.   The method of claim 34, characterized in that the phase change material contact hole (263h) is formed to have a vertical central axis (263x) spaced from a vertical center axis (259x) of the lower conductive bushing (259).   The method of claim 34, characterized in that the metallization line contact hole (267h) is formed to have a vertical central axis (267x) spaced from a vertical central axis (263x) of the contact hole. of phase change material (263h).