FR2864732A1 - Phase locked loop for phase/frequency modulation, has low pass filter controlling oscillator using voltage at capacitor terminal, and switch, between filter and terminal, controlled to insulate filter from capacitor during pulse generation - Google Patents

Abstract

The loop has a phase comparator generating a measurement signal with pulses, based on phase difference between divided frequency and reference signals. A low pass filter (34) controls a voltage controlled oscillator using voltage at a terminal of a capacitor (50) receiving load current from a load pump (33). A switch (51) placed between filter and terminal is controlled to insulate the filter from the capacitor during pulse generation.

Description

PHASE STACK LOOP

  The present invention relates to phase-locked loop (PLL) loops, particularly in their application to phase or frequency modulation.

  A PLL conventionally comprises a Voltage Controlled Oscillator (VCO) delivering a high frequency signal, a frequency divider converting the high frequency signal into a divided frequency signal, a phase comparator producing a signal. measuring a phase difference between the divided frequency signal and a reference signal, and a low-pass filter to which the measurement signal is applied and whose output controls the VCO.

  In the modulation application, instantaneous variations of the division factor applied by the frequency divider are introduced in order to obtain corresponding variations in the frequency or phase of the VCO output signal.

  The phase comparator may be constructed to activate the measurement signal during a measurement window in response to each active edge of one of the input signals of the phase comparator. The activation of the measurement signal comprises, when an active edge of the other input signal of the phase comparator, possibly delayed by a predetermined time, falls inside the measurement window, a first pulse between the beginning of the measurement window and this active edge and a second pulse opposite to the first pulse between the active edge and the end of the measurement window. A drift in phase of the loop with respect to its operating point results in an imbalance between the two pulses, which the low-pass filter integrates to make a compensation to the control input of the VCO.

  An example of such a phase comparator is described in EP-B-0 835 550. This comparator has the advantage of not presenting what is called a dead zone. In ordinary phase comparators, the dead zone results from the non-zero response times of the logic gates of the comparator: the phase shifts smaller than these response times are not detected, so that the response of the comparator has a zero slope range. (dead zone) in the vicinity of the origin. Such a dead zone affects the accuracy of the PLL and virtually prevents it from being used as a phase or frequency modulator.

  The non-dead phase phase comparator described in EP-B-0 835 550 also has the advantage of having a double slope response around its nominal operating point, which gives it excellent sensitivity for application to modulation.

  This application is particularly sensitive to even small disturbances introduced into the components of the loop, since the modulation corresponds to relatively small relative frequency variations with respect to the comparison frequency, that is to say at the frequency of the reference signal. An order of magnitude typical of these variations is one-thousandth of the comparison frequency. Under these conditions, subtle phenomena, difficult to identify, can cause noise or stray lines at the output of the VCO, and careful optimization of the PLL is required.

  An object of the present invention is to improve the performance of the PLL, in particular by reducing the parasitic lines at the output of the VCO.

  The invention thus proposes a phase-locked loop comprising a controlled oscillator for delivering a high frequency signal, a frequency divider for converting the high frequency signal into a divided frequency signal, a phase comparator for receiving the signal. frequency and a reference signal and producing a measurement signal having, at each cycle of the reference signal, at least one pulse of duration dependent on a phase difference between the divided frequency signal and the reference signal, a charge pump for generating a charging current in response to each pulse of the measurement signal, an integrating capacitor having a charging current receiving terminal, a low-pass filter for controlling the oscillator from the voltage to said terminal of the integration capacitor, and a switch placed between the low-pass filter and said terminal of the integration capacitor and controlled by is to isolate the low-pass filter integration capacitor during at least some pulses of the measurement signal.

  Other features and advantages of the present invention will appear in the following description of nonlimiting exemplary embodiments, with reference to the accompanying drawings, in which: - Figure 1 is a block diagram of a conventional PLL; FIG. 2 is a diagram of a low-pass filter that can be used in a PLL; Figures 3 to 5 are timing diagrams illustrating the operation of the PLL of Figure 1; FIGS. 6 and 7 are timing diagrams illustrating the operation of the PLL of FIG. 1 with another type of phase comparator; FIG. 8 is a block diagram of a PLL according to the invention; and FIG. 9 shows timing diagrams illustrating the operation of the PLL of FIG. 8.

  With reference to FIG. 1, a PLL conventionally comprises a VCO 30 delivering a radiofrequency signal S whose frequency fvco is for example of the order of a few hundred MHz. This signal is addressed to a frequency divider 31 applying a variable division factor P. A variation over time of this division factor P will provide a desired modulation of the output signal S. The divided frequency signal QA from the frequency divider 31 is addressed to an input of a CPF 32 which further receives a FREF reference signal produced from a crystal oscillator. The frequency FREF FREF signal is for example of the order of ten MHz. In order to obtain a fvco frequency at the output of the VCO 30, P = fvcolfrefÉ is used. By modulating P around the fvcolfref value, a frequency or phase modulation is carried out around a fvco carrier. In the example considered, the CPF 32 has an output signal consisting of two binary components INVP, INVN. A charge pump 33 receives these two components to establish a voltage V at an input node of a low pass filter 34. The filtered voltage produced by this filter 34 is used to control the frequency of the VCO 30.

  The role of the charge pump 33 is to generate a positive current when the component INVP is active, and a negative current of the same intensity when the component INVN is active. The total charge generated is an increasing function, substantially piecewise linear, of the time offset between the split frequency signal QA and the reference signal FREF.

  Accumulated in a capacitor, this charge results in a voltage operable to drive the VCO 30 to force the phase alignment between QA and FREF. In practice, a low-pass filter 34 intervenes between the charge pump 33 and the VCO 30 to eliminate high-frequency fluctuations due in particular to the switching of the components INVP and INVN.

  FIG. 2 shows the conventional structure of a low-pass filter 34 that can be used in such a PLL. The current from the charge pump 33 is sent to a node, whose voltage is denoted V, connected to the control input of the VCO 30. This node is connected to ground via two branches, the one having a resistor 40 and a capacitor 41 in series, and the other having a capacitor 42. By way of example, the resistor 40 may be of RI = 200 0, and the capacitors 41, 42 may have respective capacitances of Cl = 0.5 F and C2 = 50 nF. At the operating frequencies of the PLL, such a filter behaves as an integrator of equivalent capacitance Cl + C2.

  Figures 3 to 5 illustrate the behavior of the loop in the case where the phase comparator 32 is typically of the "backlash" type. Figure 3 shows how the VCO 30 is controlled when the PLL is in equilibrium. At each cycle of the reference signal FREF, the CPF 32 then generates two consecutive pulses of the same duration on its respective components INVP and INVN. The current delivered by the charge pump 33, which is proportional to INVP INVN, has the appearance shown in the third line of the figure, and it gives rise to a voltage VO at the control input of the VCO 30. This voltage An analog pulse is present at each FREF cycle, with a rise in voltage then a descent which, when the PLL is balanced, returns the voltage VO to the value it had before the pulse.

  The diagram of FIG. 4 corresponds to the case where the phase error is positive. In this case, one of the two pulses, INVN, is shortened by d (p with respect to its duration at equilibrium, so that the voltage pulse V1 at the input of the VCO (4th line of FIG. 4) is incomplete and leaves a residual voltage whose effect is to compensate for the detected phase error.

  The last line of FIG. 4 shows the difference between the voltage V1 observed when the error is positive and the voltage VO at equilibrium. The change in value of this difference V1 VO is performed over a period d (p equal in absolute value to the detected phase shift.

  Symmetrically, when the phase error is negative (FIG. 5), the pulse INVN is lengthened by the duration d (p) This duration d (p is again found in the command V2 received by the VCO.

  In the application of the PLL to the modulation, the instantaneous variations of the division factor P give rise permanently to phase shifts d (p) that the loop catches up to achieve the desired modulation.

  The last lines of FIGS. 4 and 5 show that the relative bias of the VCO at each cycle keeps track of this shift dcp, which has an impact on the spectral shape of the modulation, in particular by introducing parasitic lines. It should be noted that these parasitic lines can not be removed by filtering since the corresponding phase modulation is in the same range as the desired modulation.

  This problem exists with CPFs other than the backlash comparator referred to in Figures 3 and 5.

  The case of a phase comparator with no dead zone of the type described in EP-BO 835 550 is illustrated in FIGS. 3, 6 and 7. The behavior of this phase comparator at equilibrium is essentially the same as that described previously (Figure 3). When the phase error is positive (FIG. 6), the pulse INVN is shortened by the duration d (p, at the same time as the pulse INVP is elongated by the same duration d.sub.C. phase is doubled compared to the previous case.

  The last line of FIG. 6 shows that we find the shift d (p in the behavior of the relative stress VI VO felt by the VCO 30. Symmetrically, when the phase error is negative (FIG. 7), the signal INVP is shortened by the duration d (p, while the INVN pulse is extended by the same duration d (p) This duration d (p) is also found in the VCO control.

  To eliminate the above problem of parasitic lines, it is proposed to isolate the output of the charge pump 33 from the input of the low-pass filter 34 in the periods when the charge pump generates the current pulses. An integrating capacitor is mounted at the output of the charge pump to absorb these current pulses and then restore the resulting accumulated voltage.

  Such an embodiment of the PLL is illustrated in FIG. 8, where the elements bearing the references 30 to 34 are of the same nature as those described previously with reference to FIG. 1. The integration capacitor 50, whose capacitance CM is per example of the order of 100 pF, is connected between the output of the charge pump 33 and the ground. A switch 51 is placed between the output node of the charge pump, whose voltage is denoted V and the input node of the low-pass filter 34, whose voltage is denoted W. The switch 51 is controlled by a binary signal FC which, when the PLL is hooked in frequency, opens the switch 51 in a phase of each cycle of the reference signal FREF, this phase covering the duration of the current pulse from the charge pump 33.

  In the diagram of FIG. 9, the lines VO, V1 and V2 reproduce the corresponding lines of FIGS. 3, 6 and 7, and translate the voltage V across the integration capacitor 50 in the cases where the phase error detected is respectively zero, positive and negative. However, a difference with respect to the case of FIGS. 3, 6 and 7 is that the flanks of the voltage pulse are steeper since the integrating capacitor 50 has a lower CM capacitance than the equivalent capacitance of the pass filter. low 34.

  The peak voltage at the output of the charge pump 33 is therefore higher than in the previous case if the current delivered by the charge pump is of the same intensity. However, the CM value must be sufficient to maintain the linearity of the charge pump.

  The switch 51 is open in the time interval framed by the two dashed lines in FIG. 9, so that the voltage W at the input of the filter 34 and the VCO 30 has the shape represented at the lines W0, W1 and W2 in the three cases VO, VI, V2 above. It can be seen that the change of the control at the input of the VCO is effected according to a synchronous step with respect to the comparison frequency fref, without reflecting the shift dcp measured by the phase comparator.

  This makes it possible to avoid parasitic phenomena within the signal modulation lobe S at the output of the VCO 30.

  In the example shown in FIG. 9, the active edges of the reference signal FREF are falling edges, and the control signal FC is a version of this reference signal that is out of phase by a quarter cycle (t / 2). switch 51 is open when FC is at logic level 0 and closed when FC is at logic level 1.

  To generate the signals FREF and FC, it is possible to use a circuit 54 to which is applied an external signal FEXT whose frequency fext is twice the comparison frequency fref. In the example of FIG. 8, this circuit 54 comprises two D flip-flops 55, 56 respectively clocked by the signal FEXT and by its logical complement, produced by an inverter 57. The flip-flop with its inverting output is looped back on its input D. The reference signal FREF is taken from this inverting output. The flip-flop 56 has its input D connected to the Q output of flip-flop 55, and its output Q connected to an input of an OR gate 58. The other input of this OR gate receives a bit LD indicating whether the PLL is hooked in frequency (LD = 0) or not hooked in frequency (LD = 1). The control signal FC of the switch 51 is obtained at the output of the OR gate 58.

  When the PLL is hooked up in frequency, the signals FEXT, FREF and FC have the appearance shown on the first three lines of FIG. 9, the signal FC making it possible to exclude the desired portions of the voltage signal V. This mode of operation is inhibited before the PLL frequency snap (LD = 1). The OR gate 58 thus prevents the isolation between the integration capacitor 50 and the low-pass filter 34 in the loop frequency-seeking steps of the loop. This arrangement minimizes the duration of attachment, and therefore the switching speed of the modulator. A controller (not shown) of the PLL can simply determine that the PLL is hooked in frequency by the fact that the active edge of the reference signal FREF falls several times in succession within the measurement window of the phase comparator 32 and produce the LD bit accordingly.

  The fact that the integration capacitor 51 has a capacitance CM which is much smaller than the equivalent capacitance of the low-pass filter 34 ensures that the thermal noise induced by the resistor Ron that the switch 51 exhibits in the closed state remains negligible. It is easy to optimize the Ron and CM values so that they correspond to a time constant sufficiently low to transfer the charge from the capacitor 50 to the low pass filter 34 for half a period of time. In practice, the values CM = 100 pF, Ron = 30 S2 and Cl + C2> 10 nF are suitable for comparison frequencies of the order of ten MHz.

Claims (5)

  A phase locked loop comprising a controlled oscillator (30) for delivering a high frequency signal (S), a frequency divider (31) for converting the high frequency signal to a divided frequency signal (QA), a phase comparator (32) for receiving the divided frequency signal and a reference signal (FREF) and producing a measurement signal (INVP, INVN) having, at each cycle of the reference signal, at least one pulse of dependent duration of a phase difference between the divided frequency signal and the reference signal, a charge pump (33) for generating a charge current in response to each pulse of the measurement signal, an integrating capacitor (50) having a load current receiving terminal, a low pass filter (34) for controlling the oscillator from the voltage at said terminal of the integrating capacitor, and a switch (51) placed between the low pass filter and said condensate terminal ur of integration and controlled so as to isolate the low-pass filter of the integration capacitor during at least some of the pulses of the measurement signal.   The phase locked loop according to claim 1, further comprising means (54) for generating a control signal of said switch (51), synchronized with the reference signal (FREF).   The phase locked loop of claim 2, wherein the control signal (FC) is produced as a version of the reference signal (FREF) shifted by a quarter of a cycle.   A phase locked loop according to any one of the preceding claims, wherein the integrating capacitor (50) has a capacitance substantially less than an equivalent capacitance of the low pass filter (34).   A phase locked loop according to any one of the preceding claims, further comprising means (58) for preventing isolation between the integrating capacitor (50) and the low pass filter (34) in a step search for frequency snapping of the loop.