FR2864697A1 - Formation of transistor grids with smaller critical dimensions by two stage engraving for incorporation in microelectronics circuits - Google Patents

Abstract

The formation of transistor grids comprises: (A) engraving, across some first patterns (112) formed in a perforated masking layer (106), of a layer (104) of grid material resting on a substrate (100) to produce some second patterns in the layer of grid material; (B) engraving at least laterally of the second patterns to reduce the critical dimension of the second patterns (114) with respect to the critical dimension of the first patterns. An independent claim is also included for a microelectronics device incorporating such transistor grids.

Description

PROCESS FOR PRODUCING GRIDS OF TRANSISTORS

DESCRIPTION

TECHNICAL FIELD AND PRIOR ART

  The present invention relates to the field of microelectronics and more particularly to the processes for producing transistor gates.

  It is continuously sought to reduce the size of the transistors, in particular to improve their performance in terms of speed and reduce the manufacturing costs of microelectronic circuits. This implies, for example the realization of channels of smaller and smaller dimensions. A transistor channel is generally formed in a preformed semiconductor active layer on a substrate. Its thickness is mostly fixed by that of said active layer. The length of the channel is defined by the dimension or critical dimension of a grid covering it. Thus, it is useful to be able to reduce the gate size of the transistors.

  To form patterns of transistor gates, several technological steps are generally performed, including photolithography and etching steps. The minimum resolution or critical dimension of resin patterns able to delineate the size of grids, which can be obtained by photolithography processes is dependent on the wavelengths of radiation

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  used in these processes. The wavelengths that can be used for photolithography processes are becoming smaller. However, nowadays, they reach limits that prevent further reducing the ratings of transistor grids.

  In order to obtain critical dimensions or dimensions of transistor gates, which are smaller than those attainable by conventional photolithography methods, a first method described in the document [1] referenced at the end of the present description may be used.

  This method, which will be called resist trimming, makes it possible to reduce the size of photoresist patterns obtained by photolithography.

  It is carried out using a plasma that reacts with the photosensitive resin. It consists, using said plasma, to reduce, by erosion, photosensitive resin patterns obtained after photolithography.

  By etching a layer, for example of grid material, through patterns eroded in this way, it is possible to obtain grid patterns of dimensions smaller than those attainable directly after conventional photolithography.

  This method nevertheless has limitations. Indeed, the erosion of said resin patterns occurs isotropically. It causes a reduction in the thickness of these patterns in addition to a reduction of their critical dimension. If this erosion is too great, the pattern thickness may be too low. Indeed, the etching of a layer underlying resin patterns of too small thickness may cause the formation of degraded pattern in said underlying layer.

  To remedy this problem, the thickness of the resin layers used could be increased.

  But when the thickness of the resin patterns is too great, they tend to sag.

  Another method called hardmask trim, is described in the document [2] referenced at the end of the present description. It can be applied to obtain grid patterns of reduced critical dimension compared to the dimensions attainable directly after photolithography alone.

  It comprises a step of overgrading a hard mask layer lying under photoresist patterns. This overgrading makes it possible to form hard mask patterns of smaller size than the resin patterns. Then, by etching a layer of gate material underlying the hard mask, grid patterns of reduced critical size can be formed.

  PRESENTATION OF THE INVENTION The present invention proposes a method for producing transistor gates, making it possible to obtain gates with a critical dimension or dimension that are smaller than those attainable by conventional photolithography methods.

  By critical dimension is meant the minimum dimension of a geometric pattern made in a thin layer, except the one or more dimensions defined by the thickness of this thin layer.

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  For a grid, the dimension or critical dimension generally defines the length of the transistor channels, in the direction connecting source and drain.

  The method according to the invention comprises the steps of: a) etching or anisotropic etching through first patterns of a masking layer, a layer of gate material in order to produce second patterns in the layer of gate material b) lateral or isotropic etching of the second patterns to reduce the critical dimension of the second patterns.

  In step a), said anisotropic etching can be carried out for example by performing ion bombardment.

  Step b) can be carried out for example by means of a halogenated plasma for example a fluorinated plasma, or by means of a wet etching, for example based on TMAH (tetra methyl ammonium hydroxyl), in particular in the case where said gate material is silicon-based.

  With the aid of this method, it is possible to obtain second patterns or grid patterns having a high aspect ratio (ratio of the height of the patterns divided by their section), for example of the order of 10 and at least higher. at 5.

  The process according to the invention makes it possible to obtain patterns of higher aspect ratios, in particular those which can be obtained by the method of the prior art called resist trimming.

  The gate material may be, for example, based on a material such as polycrystalline silicon or polysilicon, which can support shape ratios such as those previously mentioned.

  The process according to the invention can make it possible to obtain second units of critical dimension at least 10 times smaller than that of the first units. In other words, the isotropic etching step b) can allow a reduction of the second units by a factor of at least 10. Said second units can reach a critical dimension of at least less than 30 nanometers.

  According to a variant of the method according to the invention, the latter can be achieved without using a hard mask. Indeed, the masking layer may be formed of a layer of photoresist. Said first patterns are in this case resin patterns through which the layer of gate material is etched.

  In the case where the masking layer is a layer of photoresist, the method according to the invention may further comprise, prior to step a), the steps of: - depositing the photoresist layer - forming the first patterns in the photoresist layer.

  According to another variant of the method according to the invention, the masking layer may be formed of a hard mask layer.

  The method according to the invention may then further comprise, prior to step a), the steps of: depositing a hard mask layer on the layer of gate material, depositing a layer of resin on the hard mask layer, - producing said first patterns in the resin layer to form a resin mask, - etching the hard mask layer through the resin mask to form said first patterns.

  removing the resin layer after the etching step of the hard mask layer.

  The hard mask layer can be made based on an organic or inorganic material. It may be formed of a material chosen, for example, from the following materials: SiO 2, SiON, Si 3 N 4.

  In the case where the masking layer is a hard mask layer, the first patterns are patterns of the hard mask. At the end of the process according to the invention, the patterns of the hard mask have a critical dimension greater than that of the second patterns or grid patterns. This characteristic is a specificity of the process according to the invention in particular with respect to the method of the prior art hardmask trim described above. This characteristic can be used during a complete realization of the transistors.

  Keeping hard mask patterns of greater critical size than the grid patterns, for example, can make it possible to achieve improved spacer zones. These spacing zones are insulating zones encompassing the gates of the transistors and allowing the passivation thereof.

  The substrate used in the process according to the invention may for example be a silicon on insulator substrate. One or more thin layers may be interposed between the substrate and said layer of gate material. Among these layers, a gate oxide layer is located beneath the gate material layer.

  Thus, the method according to the invention may further comprise the steps of: - forming a gate oxide layer prior to the step of forming the masking layer on said substrate, forming the layer of material 20 grid on the gate oxide layer.

  The etching carried out in step b) is preferably selective with respect to the gate oxide layer. The latter can be made for example based on SiO2 or based on a high dielectric constant material (high-k according to the English terminology). In the case where the gate oxide layer is made based on a high-k material, selective etching with respect to the gate oxide layer is easier than with SiO 2.

  According to one variant, the gate oxide layer may comprise a protective material with respect to the isotropic etching carried out in step b). Thus, the gate oxide layer may be: either formed of several sub-layers, at least one of which is based on said protective material, or entirely made of this protective material.

  Said protective material may for example be an oxide and advantageously a material of dielectric constant greater than 5 or a high dielectric constant material (high-k according to the English terminology) such as for example HfO2 or ZrO2.

  The invention also relates to a method for producing transistors comprising a method such as that described above and one or more steps of forming regions of sources and drains. This method may further comprise, after step b), a step of etching the gate oxide layer in order to complete the formation of transistor gates. It may also include, possibly, the formation of spacing insulating zones for these grids. One or more stages of siliciding of the grids may also be provided. Spacer zones or spacer are areas based on insulating material to passivation grids.

  The present invention also relates to a microelectronic device comprising: - a gate oxide layer resting on a substrate, - one or more gate material-based patterns resting on the gate oxide layer, the material-based patterns gate having a critical dimension d2 at least less than 30 nm.

  The device according to the invention may further comprise: - one or more other hard mask patterns disposed on the grid material based patterns having a critical dimension dl greater than that of the gate material patterns.

  The critical dimension d2 of the grid material patterns may be, for example, at least 10 times smaller than that of hard mask patterns.

BRIEF DESCRIPTION OF THE DRAWINGS

  The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings in which: FIGS. 1A-1C illustrate a first example of a method of FIG. 3A-3B illustrates a second example of a method for reducing the grid dimension according to the invention, FIG. identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another.

  The different parts shown in the figures are not necessarily in a uniform scale, to make the figures more readable.

  DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS An exemplary method according to the present invention will now be described with reference to FIGS. 1A-1C.

  A substrate 100, for example a silicon substrate or an SOI (SOI for silicon on insulator) substrate, is covered with a gate oxide layer 102, for example having a thickness of between 1 and 200 nanometers. This layer may be made based on a dielectric material such as, for example, SiO 2. It may optionally include or be based on a dielectric material of high dielectric constant (high-k according to the English terminology) such as for example Hf02, ZrO2, ZrSiO4i or HfSiO4.

  The gate oxide layer 102 is itself covered by a layer of gate material 104, for example based on polycrystalline silicon or polysilicon. This layer of gate material 104 has a thickness that can be between 30 and 500 nanometers, for example equal to 150 nanometers.

  It is desired to make grid patterns in the layer 104, preferably having a critical dimension smaller than that which can be obtained by a conventional method of photolithography.

  To this end, a hard mask layer 106, of thickness for example between 5 and 100 nanometers, is deposited firstly on the layer of gate material 104. The hard mask layer 106 can be made based on of an organic or inorganic material, it can be made for example based on a material such as TiN, SiON, Si3N4i or SiO2. A resin layer 108, for example based on polyimide, is then deposited on the hard mask layer 106.

  Then, using, for example, a photolithography step, patterns 110 are produced in the resin layer 108, of a shape similar to those which it is desired to form in the layer of gate material. These patterns have a critical dimension d1, for example of the order of 100 nanometers.

  The critical dimension d1 is measured in a direction parallel to a main plane of the substrate 100, or to the plane defined by the orthogonal reference [0; i; j] illustrated in Figure 1A. It corresponds to the minimum dimension of the resin patterns 110, except for their thickness.

  Next, the hard mask layer 106 is etched through the resin patterns 108 to form hard mask patterns 112 that mimic the resin patterns. The hard mask patterns 112 also have a critical dimension equal to dl (FIG. 1A).

  Then, the resin layer 108 is removed, for example by a stripping process. Anisotropic etching of the gate material layer 104 is then performed through the hard mask 112 to obtain grid patterns 114 in the gate material layer 104, reproducing those of the hard mask 112 (FIG. 1B). . The anisotropic etching can be carried out for example by ion bombardment.

  In order to reduce the size of the grid patterns 114, lateral or isotropic etching of the gate material layer 104 is then carried out. This reduction can be carried out for example using a halogenated plasma, for example a fluorinated plasma. The reduction can also be carried out by a wet etching process, for example with TMAH (tetra methyl ammonium hydroxyl), in particular in the case where the layer of gate material 104 is based on silicon.

  To minimize the grid patterns 114, protected on the top by the hard mask 112, it is possible to apply long etching times, for example of the order of several tens of seconds. It is thus possible to obtain patterns having aspect ratios of the order of 10 (ratio of the height of the patterns by their section).

  The patterns 114 can reach a critical dimension d2, measured in a direction parallel to d1, at least less than 30 nanometers.

  The critical dimension d2 may be more than 10 times smaller than the dimension d1 of resin patterns 111 and hard mask previously made d1, for example of the order of 300 nm or more, dl concerning (Figure 1C).

  The second etch is preferably very selective with respect to the gate oxide layer 102 in order to keep it integrated and not to damage the underlying substrate 100.

  According to a variant of the method according to the invention, the gate oxide layer 102 may comprise a protective material for protecting it vis-à-vis the isotropic etching step. Thus, the gate oxide layer may comprise or be based on a high-k dielectric material of high dielectric constant, such as, for example, HfO 2 or ZrO 2. Grid patterns 114, obtained by this method, have a critical dimension d2 less than that of the hard mask patterns 112. This characteristic can be used, for example for a process following the one just described and for making complete transistors.

  To complete the formation of transistor gates, after the step of lateral or isotropic etching, from the device illustrated in FIG. 1C, a step of partial etching of the gate oxide layer 102 is carried out.

  Then, a conformal deposition of an insulating layer 116, for example based on nitride, is made. This insulating layer 116 then covers the sides of the grid material patterns 104 as well as the hard mask patterns 112. Then, said insulating layer 116 is removed on the top of the hard mask patterns 112.

  FIG. 2 illustrates a transistor gate obtained using the method described above. This grid resting on the substrate 100, is formed of a pattern 114a, among the patterns 114 of gate material 104, covering a portion 102a of the gate oxide layer 102.

  An insulating spacer zone, formed by the insulating layer 116 and the hard mask 112, includes the gate 200 and serves for its passivation.

  To produce a complete transistor from the device illustrated in FIG. 2, several process steps can then follow one another. A source region and a drain region of the transistor may be formed for example by epitaxy and then implantation.

  At least one step of siliciding the gate as well as source and drain regions can also be performed. In the case where the hard mask has been preserved during the process, it is preferably removed before the siliciding step.

  A second example of a method according to the present invention will now be described with reference to FIGS. 3A-3B. This example of a method, similar to that previously described, does not require the use of a hard mask layer.

  To produce grid patterns in the gate material layer 104, the latter is directly covered by a resin layer 108, for example a photosensitive resin such as polyimide.

  Then, for example by photolithography, patterns 110 are made in the resin layer 108 of the same shape as the grid patterns that one wishes to achieve in the end. These patterns 110 have a critical dimension d1, for example of the order of 100 nanometers. Then, an anisotropic etching of the gate material layer 104 through the resin patterns 108, to form the gate patterns 114 (Fig. 3A).

  The grid patterns 114 then have a critical dimension substantially equal to that of the patterns 110 formed in the resin. These patterns are then reduced, by isotropic etching, of the gate material layer 110 (FIG. 3B).

  Following the isotropic etching step, the patterns 111 can have a critical dimension d2, for example of the order 20 nanometers.

  A process following the one just described can make it possible to produce complete transistors. Also, at the isotropic etching step may succeed several stages: among which an etching of the gate oxide layer, a step of forming spacers, steps of forming regions of sources and of drains, one or more silicidation steps to allow the complete realization of transistors.

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  Documents cited: [1]: Chian-Yuh Sin et al; "Resist Trimming Technique in CF4 / O2 High-Density Plasmas for Sub-0.1 μm MOSFET 5 Manufacturing Using 248-nm Lithography"; Microelectronic Engineering 65 (2003) p. 394-405 [2]: US 6,420,097.

Claims (22)

  A method of forming transistor gates comprising the steps of: a) etching through first patterns (110,112) formed in a perforated masking layer (108,106) of a layer of gate material (104) ) relying on a substrate (100) to provide second patterns in the gate material layer (104), b) at least lateral etching of second patterns to reduce the critical dimension of the second patterns (114) relative to the critical dimension of the first patterns (110, 112).   2. The method of claim 1, the masking layer being formed of a photoresist layer (108).   3. Method according to one of claims 1 or 2, wherein the masking layer is a photoresist layer (108), the method further comprising, prior to step a). depositing the photosensitive resin layer on the layer of gate material (104), forming said first patterns (110) in the photosensitive resin layer.   4. The method of claim 1, the masking layer being formed of a hard mask layer (106).   The method of claim 4, further comprising, prior to step a). depositing a hard mask layer (106) on the gate material layer (104); depositing a resin layer (108) on said hard mask layer (106); a resin mask (110) - etching the hard mask layer through the resin mask to form said first patterns.   6. Method according to one of claims 4 or 5, the hard mask layer (106) being based on a material selected from the following: SiO2, SiON, Si3N4.   The method according to one of claims 4 to 6, further comprising: removing the resin layer (108) after the step of etching the hard mask layer (106) and prior to step a ).   8. Method according to one of claims 1 to 7, further comprising prior to step a) the steps of: - forming a gate oxide layer (102) on said substrate (100), forming the gate material layer (104) on the gate oxide layer (102).   9. Method according to one of the claims   1 to 8, the gate oxide layer (102) comprising a protective material with respect to step b) 10. The method according to claim 9, wherein the protective material is a dielectric constant material greater than 5.   11. Method according to one of claims 9 or 10, the protective material being selected from the following materials: HfO2r ZrO2.   12. Method according to one of claims 1 to 11, the second units (114) having a critical dimension at least less than 30 nanometers.   13. Method according to one of claims 1 to 12, the second units (114) having a critical dimension at least 5 times smaller than the critical dimension of the first patterns (110,112).   14. Method according to one of claims 1 to 13, the second units (114) having a shape ratio at least greater than 5.   15. Method according to one of the claims   1 to 14, the substrate being a silicon on insulator substrate. 25   16. A method of producing transistors comprising a method according to one of claims 1 to 15, wherein a gate oxide layer is interposed between said layer of gate material and said substrate, and further comprising one or more steps forming one or more regions of springs and drains.   17. The method of claim 16, further comprising etching the gate oxide layer (102).   18. Method according to one of claims 16 or 17, further comprising the formation of one or more spacing zones (116,112) for passivation grids.   19. Method according to one of claims 16 to 18, further comprising at least one step of siliciding gates and / or regions of sources and drains.   A microelectronic device comprising: - a gate oxide layer (102) resting on a substrate (100), - one or more gate material-based patterns (114) (104) resting on the gate oxide layer gate (102), the grid material-based patterns (114) having a critical dimension d2 of at least less than 30 nanometers.   The device of claim 20, further comprising one or more other hard mask patterns (112) based on the grid material patterns (114) (114), said other hard mask patterns (112) having a critical dimension. dl greater than d2 of the patterns (114) of gate material (104).   22. Device according to claim 21, d2 being at least 10 times less than dl.