FR2863141A1 - Severe environment temperature modelling for military electronic board applications having sub assemblies/components environment defined/thermal model developed/compared then process repeated/optimised - Google Patents

Abstract

The electronic system thermal modelling process has an assembly of electronic boards. The process defines the electronic boards (Cfi) with sub assemblies and components. There is a first definition of the environment between the boards (v1 to v3), followed by thermal modelling and comparison. The steps are then repeated to optimise the results.

Description

2863141 1

  METHOD FOR MODELING A SYSTEM COMPRISING

  ELECTRONIC CARDS COMPRISING COMPONENTS

UNIT

  The field of the invention is that of electronic cards used in environmental conditions that can be severe and in particular in military applications and for which it is essential to be able to estimate the heating temperatures in operation to ensure a known and satisfactory component life. It may be for example a component of the type CDIP 16, a unique Ceramic Dual ln Line component comprising 16 legs mounted alone on a board, having a junction / ambient thermal resistance of 83 C! W before dissipation 0.6W if is subjected to a severe ambient temperature of +90 ° C. and having a junction temperature of 140 ° C.

  Currently to develop electronic components capable of withstanding the thermal constraints imposed by the nature of the intended applications while integrating the necessary electrical functions, the electronic components can be modeled as follows: A set of N unit components is defined to be mounted or embedded in a printed circuit board, these components can be positioned on said card by using an Allegro type component placement model distributed by the CADENCE company for example, which determines a possible position of the different unitary components. function of electrical constraints. The component placement model is usually associated with a thermal model that evaluates the feasibility and viability of the final component in operation, as a function of the temperature rises obtained at the level of each component component and the margin allowed with respect to the manufacturer data. .

  In case of non-validation due to overheating, it is then necessary to develop another architecture of unitary components by using again the component placement tool combined with the thermal modeling tool and it iteratively until heating of acceptable unit components is achieved.

  2863141 2 Moreover, the approaches of thermal modeling of the stresses applied to the electronic components remain on the scale of an electronic card and do not concern today the problem of the complex heating of a complete system including a set of cards e.

  In this context, the present invention proposes a new method of thermal modeling of an electronic system capable of heating up in a temperature range, taking into account the operating conditions applied to it, said system comprising a set of electronic cards, each of the cards having a subset of electronic components.

  More specifically, the subject of the invention is a method of modeling an electronic system for a given application comprising a set of electronic cards, each card comprising N unitary components mounted or integrated in a printed circuit characterized in that it comprises the steps The definition of a set of electronic boards each comprising a subset of unitary components having electrical functions mounted or integrated with printed circuits and leading to a total heat dissipation power A first definition of environmental parameters between various electronic cards A first determination of a set of thermal modeling operations for each of the electronic cards, comprising a step of determining placement parameters of the unitary components on each of the cards and leading to a set of junction temperatures for each of the cards; each of the unit components of each of the electronic boards A first comparison of said junction temperatures with so-called standard data The steps of definition, determination or comparison being repeated until the junction temperatures are obtained lower than standard data temperatures by varying the environment parameters or the placement parameters of the unit components at the circuit boards.

  Advantageously, the environment parameters may be of the fluid flow type circulating between the different electronic cards.

  It may be air or liquid flowing inside a conduit juxtaposed cards.

  Advantageously, the thermal modeling operations may comprise the following steps for each of the electronic cards comprising M unitary components mounted on or integrated in a printed circuit, comprising: a first step of determining N thermal models of N unitary components, N being greater or equal to m, a step of testing the N thermal models of the N components mounted on a given printed circuit in a given environment and a step of validating M thermal models corresponding to m components among N components by comparing the results of the tests with manufacturer data and determination of a margin of use of said M components.

  Advantageously, the thermal modeling processes can be characterized in that the unitary components comprising unitary units and electrical functions integrated into the housings, the step of modeling the N unitary components comprises the determination of thermal resistances and thermal exchange surfaces at from a first set of parameters specific to the housings of the individual components and from a second series of parameters specific to the electrical functions.

  Advantageously, the testing step may comprise the determination of the thermal resistances of the environment and of the thermal model / printed circuit interface from the N thermal models and the P printed circuits.

  Advantageously, the validation step can comprise the determination of junction temperatures between N unitary components and P printed circuits and the comparison of said temperatures with standard operating temperatures of said unitary components so as to select M suitable components, among the N components. tested on a given circuit board among the P circuits. For this, the resistor network is grouped in an identical manner to an electrical network, using the series-paralleling relations, in parallel, of star / delta conversion to obtain a resistance called Rja corresponding to the thermal resistance o junction of the component and the ambient. The junction temperature can then be obtained by adding the ambient temperature and the product of the equivalent thermal resistance Rja by the power Pu of the component. According to a first variant of the invention, the validation step can be performed by considering each unit component taken in connection with a printed circuit, in isolation from the other unitary components.

  According to a second variant of the invention, the validation step can be performed by considering that each unit component in relation with a printed circuit is constrained by the presence of other unitary components and that the environment corresponding to the surface of Heat exchange between the component unit circuit and the ambient is restricted.

  Advantageously, the step of validating the M unitary components on a given printed circuit may be followed by a step of placing the M unitary components combined with a step of thermal modeling of the N integrated components or mounted on a printed circuit and a step of validating all of said M components performed by comparing the junction temperatures between the N components. and a given printed circuit and standard operating temperatures of said components.

  The invention will be better understood and other advantages will appear on reading the description which follows and with the appended figures, in which: FIG. 1 illustrates an electronic system, composed of a housing comprising a motherboard Cm and a set of daughter cards Cfi that the method of the invention proposes to model.

  FIGS. 2a and 2b illustrate the topologies of an exemplary housing and thermal model for a unitary component, used in the overall modeling process, according to the invention. In general, the electronic systems that can be modeled according to the method of the invention comprise, as illustrated in FIG. 1, a housing B comprising a motherboard Cm and a set of X daughterboards Cfi fixed on the motherboard. Given the conditions of use of the system for a given application, the housing can support a determined maximum dissipated power, corresponding to a global maximum heating temperature.

  In order to optimize the thermal dissipation of the electronic cards, during operation, it is necessary to play on parameters of the inter-card space type or especially of the type of cooling fluid circulation. It is a conventional manner of air that is circulated at variable speeds, it can also be coolant that can be circulated in the housing structure.

  Each of the X cards Cfi comprises a set of Mi unit components corresponding to a given electrical function imposed for the proper functioning of the electronic card and therefore all the cards.

  The fluid flow type environment parameters are pre-adjusted according to the power to obtain temperature differences between the input and the output equal to the predetermined or imposed extreme temperature difference.

  More precisely, a series of fluid flows d1, d2, .dn corresponding in the schematic example of FIG. 1 is determined at air flow velocities v1, v2, v3 between the cards, and possibly V4 and V5 outside.

  2863141 6 Each flow velocity is bordered in a minimum velocity interval and a maximum velocity [Vi min; Vi maxi and the sum of the mass flow rates [qm] of these speeds being equal to a constant.

  In parallel, thermal model operations are performed at each of the electronic cards to define X sets of Mj junction temperatures of the unitary components at the level of each of the cards.

  Each of the XMi junction temperatures is compared with a maximum standard temperature that can not be exceeded, designated Tijextreme o with 1 isXet 1 sjsMj Thus, in the case of the 4 electronic cards of the example, we define: Tl Mj min T2Mj min T3Mj T4Mj min T 1Mj <_ T1Mj max <T 2Mj 5 T2Mj max T 3Mj <T3Mj max T 4yMj <_ T4Mj max The temperatures being defined for the flow velocities VI, V2, V3, possibly V4 and V5, themselves between min and max values

  In the case where for a card a junction temperature higher than the standard temperature value Tijexteme is obtained, the 1 flow rate is modified in accordance with the following condition; the sum of the mass flow [qm] must be constant.

  Thus, if a junction temperature that is too high at the level of the card 1 is obtained, it will be sought to increase the parameter VI, at the expense of the other flow rates, which must nevertheless always lead to obtaining acceptable junction temperatures. (and therefore lower than Tijextreme temperature) on the other cards.

  Thus the process is reiterated until junction temperatures are obtained, all lower than the Tijextreme values.

  In the case where it is not possible to obtain all the junction temperatures, below imposed limits, the method according to the invention provides for modifying the placement, the dissipation, or the type of the unitary components and of the renew thermal modeling by redefining new junction temperatures.

  2863141 7 We will describe in more detail how each of the electronic boards are defined and optimized to optimize the overall process in the entire electronic system: In general, the first step is the selection of individual components that can be used in a specific card whose characteristics were first identified in terms of power constraints and therefore tolerance in terms of heating.

  Typically to develop an electronic card, it is decided to integrate a number of electrical functions, said electrical functions being themselves integrated into housings that can be ceramic, plastic or even metal.

  To carry out the modeling of each of the boxes comprising electrical functions, certain parameters are known and listed with precision: (BI database) These parameters can typically be: the number of tabs, Np the half-length of the box, Lbo the enclosure width, C housing thickness, W2 number of rows of legs, Nrp Other parameters intrinsic to the electrical function or buried chip in the housing are defined by default: (and complement the BI database) These parameters can typically be: the half-length Lpu of the chip, the internal half-length of the metallization under chip Lpa, the half-width A, the half-internal width of metallization under chip B, the thickness of a first layer C1 located between the electrical function and the housing cover, the thickness W1 of said layer, the thickness e of the chip, the thermal conductivities of the materials, Kpuce, Krésine 35 b housing named Kres, Kgrille, Kcolle, Kpattes, 2863141 8 the length Lp of the legs, the surface of the legs Sp, the distance from the chip to the gate Ct the thickness ec of the glue at the chip the thickness eg of the lead frame of the component The topologies of the case and the thermal model are illustrated respectively in FIGS. 2a and 2b.

  From all these parameters it is possible to define a set of thermal resistances and thermal exchange surfaces of the thermal model for each chip integrated to a given housing.

  Rpuce Resistance of the chip R uce = 1000 * e + 1000 * ec p Kpuce * 4 * A * Lpu Kcolle * 4 * A * Lpu Rb1 Resistance branch 1 under the chip Rbl = 1000 * W1 whereSpal = 4 * Lpa * B Kres * 1JS * Spal S- surface under chip Rai Resistance 1 below the chip Rat = 1000 * WO where Spuce = 4 * A * Lpu and WO = W2 (W1 + ec + eg + e) Kres * S + * Spuce S + surface above chip Rb2 Resistance branch 2 upper case Rb2 = 1000 * (W2 W1) Kres * V (4 * C * Lbo S +) * (4 * C * Lbo 4 * Ct * Lpa) S + surface above the puce 2863141 9 Rb3 Resistance branch 3 lower housing 1000 * W l Kres *., jS2 * (4 * C * Lbo 4 * Ct * Lpa) S2 ... bottom surface of the housing Rcl Internal resistance 1 of the housing Rc1 = Elliptic ( A, Lpu, B, Lpa, Kgrille, eg, 100) + Elliptic (B, Lpa, Ct, Lpa + 0.8, Kgrlle eg, 100) + Elliptic (Ct, Lpa + 0.8, C, Lbo, Keq, W2, a ) An integration angle of the elliptic function Calculation of a mathematical function to calculate the elliptical surface considered Rates Resistance of the legs Rattes = Elliptic (Ct, Lpa + 0.8, C, Lbo, Keq, Weq, a) + 1000 * Lp Rpts Kgrille * Sp * Np S- Bottom area of chip S- = r *, / B2 + W12 * VLpa2 + W12) Si- Top surface of chip S + = 7r *. JLpu2 + W02 * - \% A2 + W02oùWO = W2 (W1 + ec + eg + e) S2 (-) Bottom surface of housing S2 = (4 * C * Lbo) (S) S1 (+) Top surface of housing SI = (4 * C * Lbo) (S +) + (4 * W2 * (C + Lbo)) Rb3 = 2863141 10 Then in a second step it is possible to define thermal resistances of environment and interface thermal model circuit for a predetermined printed circuit, taking into account parameters of natural convection and forced convection.

  Heat exchange coefficients Natural convection: h = 10W / m2. C harte = 10W / m2. C Forced convection: h = 10 (2.C.10-3) -0.4 Vo. h = 40.vo.a Report ereport = 0.55 mm 15 Rec Rec = 106 k case Rco 1 Air contact resistance under the chip Rcol = 103 É / ereport + ecarte '2 S _ k report kz) Kreport thermal conductivity of report Kz thermal conductivity of the Rco board 2 Air contact resistance under the case Rco2 = 103 / ereport + board '2 S2 k report kz Reh Thermal exchange resistance of the board under the component Reh = 106/1 + spaced10_3 / 2 \ 4.C.Lbo \ hcard kz & Contact resistance of the tabs spreads 10-3 I2 where S = 2.C. _p.10-6 2 S + (eurte.1 O-3/2) z 7c

_JONCTION-BOX

  Rth JC: _ [r [[(Rgtttes- + Rb2 + Rb3 l l +

_JONCTION-ROOM

  ER: = Rcl + [(Rpa + Rp) 1 + (Rb3 + Rco2) 1 + (Rb1 + Rco1) (Rb1 + Rcc) ERC1 R Tl: =

ER

  (Rpa + Rp) 1 + (Rb3 + Rco2) 1] 1CLl R T2: =

ER

  R TC: = (Rbl + Rcol) E [(Rpa + Rp) 1+ (Rb3 + Rco2) 1] 1 ER RP = 4.

S lt

  + Rbl 1 + Rpuoe + Ra1_Rth_JA = I [R_Tc + 1 (R ca 1 + Reh1)] + (R_T2F Rce2 + Rbi 1 + R Tl + Rpuc + (Rai + Rce) 1

_JONCTION-CARD

  Rth JA Xp Érpuce Xp ÉR_T 1 Rth JB: = (R Ti + Rpuce) ÉXp + R TEE Xp R T2 + Rce2 + Rb2 We then deduce for each box comprising a chip Pj given corresponding to a given electrical function, mounted at level (Rai + Rcel) Rth JA Xp: = 1 2863141 12 of a card on data Cfi, a thermal resistance leading to a given heating temperature Tij.

  According to a first variant of the invention the temperature Tij is defined by considering each integrated housing in isolation from the others and can therefore dissipate heat in an undefined space.

  For the entire board comprising M unitary components consisting of a housing comprising an electrical function, M thermal models are thus defined.

  Each temperature Tij is then compared with a standard operating temperature Tsij.

  If the temperature Tij is greater than the temperature Tsij, the process is reiterated with another housing including the same electrical function, if the optimization of its environment or the card or the power does not allow to lower its temperature.

  Thus from M thermal models it is necessary to select N thermal models compatible with the predefined map.

  According to a variant of the invention each unit component is no longer taken completely isolated from the others but is considered to be constrained in a finite environment as to its space for heat dissipation.

  From the selection that is made previously, a placement step of the N unit components is then performed using a standard tool for placing said ALLEGRO components in combination with a thermal modeling tool of FLOTHERM type.

  The allegro cadence software is a component placement software, it allows to design the electrical design or routing of electronic cards 30 before their launch in manufacturing.

  The FLOTHERM software developed by FLOMERICS is a fluid mechanics software dedicated to the thermal and fluidic modeling of housings and electronic components. This tool conventionally uses elementary mesh operations which make it possible to define local heating temperatures. These temperatures are then compared with manufacturer data to determine whether the chosen architecture is satisfactory given previously determined constraints. The temperature tolerance can indeed be a function of aging accepted in a given type of application. For example, reducing the junction temperature of a component from 150 C to 110 C increases its lifetime by a factor 7.5 for an activation energy of 0.7eV.

  Advantageously, the BI database can be put in a neutral format and made compatible with the simulation tools used throughout the process. The information is structured in the XML file (database file) at specific locations called fields. . When exporting the data to a software in a neutral template format, these fields are then mapped so that the data is organized so that they are compatible with the reading. The operation can be done regardless of the software by adapting the data model to its reading.

Claims (1)

  1. A method of thermal modeling of an electronic system comprising a set of electronic cards, each electronic card having N unit components mounted or integrated in a printed circuit characterized in that it comprises the following steps: The definition of a set of electronic boards (Cfi) each comprising a subset of unitary components having electrical functions leading to a total heat dissipation power A first definition of environment parameters between the different electronic boards (v1, v2, v3) - A first determination a set of thermal modeling operations for each of the electronic boards, leading to a set of junction temperatures for each of the unit components of each of the electronic boards A first comparison of said junction temperatures to standard data The definition steps, of determination n or comparison being reiterated until lower junction temperatures are obtained at standard data temperatures, by varying the environment parameters or placement parameters of the individual components on the printed circuit boards.   2. Thermal modeling method according to claim 1, characterized in that the environment parameters are of fluid flow type circulating between the different electronic cards.   3. Thermal modeling process according to claim 1, characterized in that the fluid is air or a liquid flowing inside a conduit juxtaposed to the electronic cards.   4. Thermal modeling method according to one of claims 1 to 3, each electronic card comprising M unitary components mounted on or integrated in a printed circuit and comprising a step of electrical placement of the M unitary components combined with a modeling step thermal unit of all M unitary components mounted on or integrated in a printed circuit and characterized in that it comprises: a first step of determining N thermal models of N unit components, - a second step of testing the N thermal models N components mounted on one or P printed circuit circuits given in a given environment and - a third step of validating M thermal models corresponding to m components among the N components by comparing the results of the tests with manufacturer data and determination of a margin of use of said N components.   5. A thermal modeling method according to claim 4, characterized in that the unitary components comprising unitary units and electrical functions integrated into the housings, the step of modeling the N unitary components comprises the determination of thermal resistances and surface areas. heat exchanges based on a first set of parameters specific to the housings of the individual components and from a second series of parameters specific to the electrical functions.   6. Thermal modeling process according to claim 5, characterized in that the testing step comprises the determination of the thermal resistances of environment and thermal model interface / printed circuit from M thermal models and printed circuit boards.   7. A modeling method according to claim 4, characterized in that the validation step comprises the determination of junction temperatures between N unit components and P circuits and the comparison of said temperatures at standard operating temperatures of said unit components so as to select M components 2863141 16 adapted, among the N components tested on a given printed circuit among the P circuits.   8. A method of thermal modeling of an electronic card according to one of claims 4 to 7, characterized in that the validation step is performed by considering each unit component taken in connection with a printed circuit, in isolation from other unitary components .   9. A method of thermal modeling of an electronic card according to one of claims 4 to 8, characterized in that the validation step is performed by considering each unit component in relation with a printed circuit, and constrained in a corresponding environment at the heat exchange surface between the component and the unit circuit associated and restricted by the environments of the other unitary components.   10. The method of thermal modeling of an electronic card according to one of claims 4 to 6, characterized in that the test step further comprises taking into account fluid mechanics parameters such as flow velocities. air close to the unit components.   11. Thermal modeling method of an electronic card according to one of claims 4 to 10, characterized in that the step of validating the M unitary components on a given printed circuit is followed by a step of placing the M components units combined with a thermal modeling step M integrated components or mounted on a printed circuit and a step of validating all of said components M by the comparison of the junction temperatures between the M components and a given printed circuit and standard operating temperatures of said components.