FR2856516A1 - Semiconductor component manufacturing method, involves delivering hardening liquid filling material between support-plate and integrated circuit chip so that material partially fills space between plate and chip - Google Patents

Semiconductor component manufacturing method, involves delivering hardening liquid filling material between support-plate and integrated circuit chip so that material partially fills space between plate and chip Download PDF

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Publication number
FR2856516A1
FR2856516A1 FR0307283A FR0307283A FR2856516A1 FR 2856516 A1 FR2856516 A1 FR 2856516A1 FR 0307283 A FR0307283 A FR 0307283A FR 0307283 A FR0307283 A FR 0307283A FR 2856516 A1 FR2856516 A1 FR 2856516A1
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Prior art keywords
electrical connection
chip
plate
front face
filling material
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FR0307283A
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French (fr)
Inventor
Jerome Teysseyre
Xavier Baraton
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STMicroelectronics SA
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STMicroelectronics SA
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Priority to FR0307283A priority Critical patent/FR2856516A1/en
Publication of FR2856516A1 publication Critical patent/FR2856516A1/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
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    • H01L2224/45001—Core members of the connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/48095—Kinked
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
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    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12043—Photo diode
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The method involves fixing an integrated circuit chip (10) on a front side of a support-plate by electrical connection balls (11) fixed on zones of the side and on an electrical bonding pad (12) of a rear side of the chip. A hardening liquid filling material (16) is delivered through a traversing hole between the plate and chip so that, after hardening, the material partially fills a space between the plate and chip. An independent claim is also included for a semiconductor component.

Description

ii

Procédé de fabrication d'un composant semi-conducteur et composant semiconducteur La présente invention concerne le domaine des composants ou boîtiers semi-conducteurs à puces de circuits intégrés.  The present invention relates to the field of semiconductor components or packages with integrated circuit chips.

Un mode de fabrication connu d'un composant semi-conducteur consiste à fixer sur la face avant d'une plaque-support munie de moyens de connexion électrique, une première puce de circuits intégrés par 10 l'intermédiaire de billes de connexion électrique en contact d'une part sur des zones de connexion électrique de la face avant de la plaque et d'autre part sur des plots de la face arrière de la puce, à délivrer par l'avant, dans l'espace séparant la plaque et la puce, une matière de remplissage, à fixer sur la face avant de ladite première puce, une 15 seconde puce de circuit intégré, à relier des plots de connexion électrique de la face avant de la seconde puce à des zones de connexion électrique de la plaque par des fils de connexion électrique et, enfin, à encapsuler, en avant de la plaque, les puces et les fils de connexion électrique dans une matière d'enrobage de façon à obtenir un composant 20 semi-conducteur de forme parallélépipédique présentant des zones de connexion électrique sur la face arrière de la plaque.  A known method of manufacturing a semiconductor component consists in attaching to the front face of a support plate provided with electrical connection means, a first chip of integrated circuits by means of electrical connection balls in contact. on the one hand on the electrical connection zones of the front face of the plate and on the other hand on the pads of the rear face of the chip, to be delivered from the front, in the space separating the plate and the chip , a filling material, to be fixed on the front face of said first chip, a second integrated circuit chip, to connect electrical connection pads of the front face of the second chip to electrical connection areas of the plate by electrical connection wires and, finally, to encapsulate, in front of the plate, the chips and the electrical connection wires in a coating material so as to obtain a semiconductor component 20 of parallelepiped shape having electrical connection zones on the rear face of the plate.

Afin que la matière de remplissage remplissant l'espace entre la plaque et la première puce ne vienne pas recouvrir les zones avant de connexion électrique de la plaque sur lesquelles seront ultérieurement 25 fixés les fils de connexion électrique de la seconde puce, il convient de délivrer cette matière de remplissage au plus près de la périphérie de la première puce et de prévoir ces zones avant de connexion électrique à une distance relativement importante du bord de la première puce.  In order that the filling material filling the space between the plate and the first chip does not come to cover the areas before the electrical connection of the plate on which the electrical connection wires of the second chip will subsequently be fixed, it is advisable to deliver this filling material as close as possible to the periphery of the first chip and to provide these zones before electrical connection at a relatively large distance from the edge of the first chip.

La présente invention a pour but de réduire les inconvénients ci30 dessus.  The object of the present invention is to reduce the above drawbacks.

La présente invention a tout d'abord pour objet un procédé de fabrication d'un composant semi-conducteur qui consiste: à réaliser au moins un trou traversant au travers d'une plaque support munie, autour de ce trou, de moyens de connexion électrique présentant des zones de connexion électrique sur une face avant; à fixer sur ladite face avant de ladite plaque une puce de circuits intégrés par l'intermédaire de billes de connexion électrique fixées d'une part sur des zones de la face avant 5 de cette plaque et d'autre part sur des plots de connexion électrique de la face arrière de cette puce; et à délivrer, au travers dudit trou traversant, une matière de remplissage liquide durcissable entre ladite plaque et ladite puce de telle sorte qu'après durcissement, cette matière de remplissage remplisse au moins partiellement l'espace entre cette 10 plaque et cette puce.  The present invention firstly relates to a method of manufacturing a semiconductor component which consists in: making at least one through hole through a support plate provided, around this hole, with electrical connection means having electrical connection zones on a front face; to fix on said front face of said plate an integrated circuit chip by means of electrical connection balls fixed on the one hand to areas of the front face 5 of this plate and on the other hand to electrical connection pads from the back of this chip; and supplying, through said through hole, a curable liquid filling material between said plate and said chip so that after curing, this filling material at least partially fills the space between this plate and this chip.

Selon l'invention, le procédé peut consister, ultérieurement, à encapsuler, en avant de ladite plaque, au moins la partie périphérique de ladite puce dans une matière d'enrobage.  According to the invention, the method can consist, subsequently, in encapsulating, in front of said plate, at least the peripheral part of said chip in a coating material.

La présente invention a également pour objet un procédé de 15 fabrication d'un composant semi-conducteur, qui consiste: à réaliser au moins un trou traversant au travers d'une plaque-support munie, autour de ce trou, de moyens de connexion électrique présentant des zones de connexion électrique sur une face avant; à fixer sur ladite face avant de ladite plaque une première puce de circuits intégrés par l'intermédaire 20 de billes de connexion électrique fixées d'une part sur des zones de connexion électrique de la face avant de cette plaque-support et d'autre part sur des plots de connexion électrique de la face arrière de cette puce; à fixer par empilage, sur la face avant de ladite première puce, au moins une seconde puce de circuits intégrés; à relier des plots de 25 connexion électrique de la face avant de ladite seconde puce à des zones de connexion électrique de la face avant de ladite plaque par l'intermédiaire de fils de connexion électrique; et à délivrer, au travers dudit trou traversant, une matière de remplissage liquide durcissable, entre ladite plaque et ladite puce, de telle sorte qu'après durcissement, 30 cette matière de remplissage remplisse au moins partiellement l'espace entre cette plaque et cette puce.  The present invention also relates to a method for manufacturing a semiconductor component, which consists in: making at least one through hole through a support plate provided, around this hole, with electrical connection means having electrical connection zones on a front face; fixing on said front face of said plate a first chip of integrated circuits through the intermediary of electrical connection balls fixed on the one hand to electrical connection zones on the front face of this support plate and on the other hand on electrical connection pads on the rear face of this chip; fixing by stacking, on the front face of said first chip, at least one second integrated circuit chip; connecting electrical connection pads on the front face of said second chip to electrical connection areas on the front face of said plate by means of electrical connection wires; and supplying, through said through hole, a curable liquid filling material, between said plate and said chip, so that after hardening, this filling material at least partially fills the space between this plate and this chip .

Selon l'invention, lesdites billes de connexion électrique sont de préférence noyées dans ladite matière de remplissage.  According to the invention, said electrical connection balls are preferably embedded in said filling material.

Selon l'invention, le procédé peut consister, ultérieurement, à encapsuler, en avant de ladite plaque, au moins la partie périphérique desdites puces et lesdits fils de connexion électrique dans une matière d'enrobage.  According to the invention, the method can consist, subsequently, in encapsulating, in front of said plate, at least the peripheral part of said chips and said electrical connection wires in a coating material.

Selon l'invention, ladite encapsulation est de préférence réalisée par surmoulage.  According to the invention, said encapsulation is preferably carried out by overmolding.

La présente invention a également pour objet un composant semi-conducteur qui comprend une plaque-support présentant au moins un trou traversant et munie, autour de ce trou, de moyens de connexion 10 électrique présentant des zones de connexion électrique sur une face avant; une puce de circuits intégrés fixée sur ladite face avant de ladite plaque-support par l'intermédaire de billes de connexion électrique fixées d'une part sur des zones de connexion électrique de la face avant de ladite plaque et d'autre part sur des plots de connexion électrique de 15 la face arrière de cette puce; une matière de remplissage remplissant au moins partiellement l'espace entre cette plaque et cette puce, et une matière d'enrobage encapsulant au moins la périphérie de ladite puce en avant de ladite plaque-support.  The present invention also relates to a semiconductor component which comprises a support plate having at least one through hole and provided, around this hole, with electrical connection means having electrical connection zones on a front face; an integrated circuit chip fixed on said front face of said support plate by means of electrical connection balls fixed on the one hand to electrical connection zones on the front face of said plate and on the other hand on pads electrical connection of the rear face of this chip; a filling material at least partially filling the space between this plate and this chip, and a coating material encapsulating at least the periphery of said chip in front of said support plate.

Selon l'invention, ledit composant peut avantageusement 20 comprendre en outre une seconde puce de circuits intégrés fixée sur ladite première puce et des fils de connexion électrique reliant des plots de connexion électrique de la face avant de ladite seconde puce à des zones de connexion électrique de la face avant de ladite plaque; ladite matière d'enrobage encapsulant, en avant de ladite plaque, au moins la 25 partie périphérique desdites puces et lesdits fils de connexion électrique.  According to the invention, said component may advantageously further comprise a second integrated circuit chip fixed on said first chip and electrical connection wires connecting electrical connection pads on the front face of said second chip to electrical connection areas from the front face of said plate; said coating material encapsulating, in front of said plate, at least the peripheral part of said chips and said electrical connection wires.

La présente invention sera mieux comprise à l'étude d'un composant semiconducteur et d'un mode de fabrication de ce composant, décrits à titre d'exemples non limitatifs et illustrés par le 30 dessin sur lequel: - la figure 1 représente une coupe transversale d'un composant semi- conducteur selon la présente invention; - la figure 2 représente une coupe transversale dudit composant à une première étape de fabrication; - la figure 3 représente une coupe transversale dudit composant à une étape suivante de fabrication; - la figure 4 représente une coupe transversale dudit composant à une étape suivante de fabrication; - la figure 5 représente une coupe transversale dudit composant à une étape suivante de fabrication; - et la figure 6 représente une coupe transversale dudit composant à une étape suivante de fabrication.  The present invention will be better understood from the study of a semiconductor component and a method of manufacturing this component, described by way of nonlimiting examples and illustrated by the drawing in which: - Figure 1 shows a section transverse of a semiconductor component according to the present invention; - Figure 2 shows a cross section of said component in a first manufacturing step; - Figure 3 shows a cross section of said component in a next manufacturing step; - Figure 4 shows a cross section of said component in a next manufacturing step; - Figure 5 shows a cross section of said component in a next manufacturing step; - And Figure 6 shows a cross section of said component in a next manufacturing step.

En se reportant à la figure 1, on voit qu'on a représenté un 10 composant semi-conducteur 1 qui comprend une portion de plaquesupport, ou substrat, 2a carrée munie de moyens de connexion électrique 3 qui comprennent des zones de connexion électrique 4 prévues sur la face avant 5 de la plaquesupport 2a et des zones de connexion électrique 6 prévues sur la face arrière 7 de la plaque-support 2a, les zones avant 4 15 et les zones arrière 6 étant reliées par des lignes de connexion électrique 8.  Referring to Figure 1, we see that there is shown a semiconductor component 1 which comprises a portion of support plate, or substrate, 2a square provided with electrical connection means 3 which include electrical connection areas 4 provided on the front face 5 of the support plate 2a and of the electrical connection areas 6 provided on the rear face 7 of the support plate 2a, the front areas 4 and the rear areas 6 being connected by electrical connection lines 8.

La plaque.support 2a présente, sensiblement en son milieu, un trou traversant 9 de relativement faible diamètre.  The plate.support 2a has, substantially in its middle, a through hole 9 of relatively small diameter.

Le composant semi-conducteur 1 comprend en outre une première 20 puce de circuits intégrés 10 qui est fixée à distance et à plat sur la face avant 5 de la plaque support 2a par l'intermédiaire de billes de connexion électrique 11 qui sont en contact d'une part avec certaines des zones de connexion électrique 4 de la plaque support 2a et d'autre part sur les zones de connexion électrique 12 prévues sur la face arrière de la 25 puce 10.  The semiconductor component 1 further comprises a first integrated circuit chip 10 which is fixed at a distance and flat on the front face 5 of the support plate 2a by means of electrical connection balls 11 which are in contact d on the one hand with some of the electrical connection zones 4 of the support plate 2a and on the other hand on the electrical connection zones 12 provided on the rear face of the chip 10.

Le composant semi-conducteur 1 comprend en outre une deuxième puce de circuits intégrés 13 carrée, plus petite que la première puce 10 et fixée à plat sur la face avant de cette première puce 10, par  The semiconductor component 1 further comprises a second square integrated circuit chip 13, smaller than the first chip 10 and fixed flat on the front face of this first chip 10, by

exemple par collage.example by collage.

La seconde puce 13 présente, sur sa face avant, des plots de connexion électrique 14 qui sont reliés à certaines autres zones de connexion électrique avant 4 situées au-delà de la périphérie de la première puce 10, par l'intermédiaire de fils de connexion électrique 15 qui passent à distance de la périphérie de la première puce 10.  The second chip 13 has, on its front face, electrical connection pads 14 which are connected to certain other front electrical connection zones 4 situated beyond the periphery of the first chip 10, via connection wires electric 15 which pass away from the periphery of the first chip 10.

Le composant semi-conducteur 1 comprend en outre une matière de remplissage durcie 16 qui remplit complètement l'espace entre la plaque support 2a et la première puce 10, en noyant les billes de connexion électrique 11, ainsi qu'au moins partiellement le passage 5 traversant 9. Comme on le voit, cette matière de remplissage 16 recouvre aussi au moins certaines des zones 4 sur lesquelles sont connectés les fils de connexion électrique 15.  The semiconductor component 1 further comprises a hardened filling material 16 which completely fills the space between the support plate 2a and the first chip 10, by embedding the electrical connection balls 11, as well as at least partially the passage 5 passing through 9. As can be seen, this filling material 16 also covers at least some of the zones 4 to which the electrical connection wires 15 are connected.

Le composant semi-conducteur 1 comprend enfin une matière d'enrobage 17 dans laquelle sont complètement encapsulés, en avant de 10 la plaque support 2a, les puces 10 et 13, la matière d'enrobage 16 et les fils de connexion électrique 15, le composant semi-conducteur 1 se présentant alors sous la forme d'un parallélépipède dont la partie est constituée par la plaque support 2a.  The semiconductor component 1 finally comprises a coating material 17 in which are completely encapsulated, in front of the support plate 2a, the chips 10 and 13, the coating material 16 and the electrical connection wires 15, the semiconductor component 1 then taking the form of a parallelepiped, the part of which is constituted by the support plate 2a.

En se reportant aux figures 2 à 6, on va maintenant décrire les 15 différentes étapes de fabrication du composant semi-conducteur 1.  Referring to FIGS. 2 to 6, a description will now be given of the 15 different stages of manufacture of the semiconductor component 1.

Comme le montre la figure 2, on part d'une plaque support 2 préfabriquée, présentant une multiplicité d'emplacements espacés 18 correspondant chacun à la portion de plaque support 2a, disposée selon une matrice rectangulaire régulière, dans lesquels sont prévus 20 respectivement des moyens de connexion électrique 3 et un trou traversant 9.  As shown in FIG. 2, we start from a prefabricated support plate 2, having a multiplicity of spaced locations 18 each corresponding to the support plate portion 2a, arranged in a regular rectangular matrix, in which means 20 are provided respectively electrical connection 3 and a through hole 9.

Une première étape consiste à fixer sur chaque emplacement 18 une première puce de circuit intégré 10 par l'intermédiaire de billes de connexion électrique 1 1 comme décrit précédemment.  A first step consists in fixing on each location 18 a first integrated circuit chip 10 by means of electrical connection balls 11 as described above.

Comme le montre la figure 3, une étape suivante consiste à fixer à plat, sur la face avant de chaque première puce 10, une seconde puce 13 comme décrit précédemment.  As shown in FIG. 3, a next step consists in fixing flat, on the front face of each first chip 10, a second chip 13 as described above.

Comme le montre la figure 4, une étape suivante consiste, sur chaque emplacement 18, à installer les fils de connexion électrique 15 30 comme décrit précédemment.  As shown in FIG. 4, a next step consists, on each location 18, of installing the electrical connection wires 15 as described above.

Comme le montre la figure 5, l'opération suivante consiste à placer la plaque support 2 à l'envers sur l'extrémité supérieure de colonne 19 d'un réceptacle 20, dans une position telle que les trous traversants 9 sont ouverts vers le haut et que les puces 10 et 13 sont en- dessous de la plaque 2, les colonnes 20 étant placées de façon à ne pas entrer en contact avec les fils de connexion électrique 15.  As shown in FIG. 5, the following operation consists in placing the support plate 2 upside down on the upper column end 19 of a receptacle 20, in a position such that the through holes 9 are open upwards and that the chips 10 and 13 are below the plate 2, the columns 20 being placed so as not to come into contact with the electrical connection wires 15.

Dans cette position renversée, l'opération suivante consiste, à l'aide d'au moins une aiguille 21, à délivrer une quantité calibrée de la 5 matière de remplissage 16, à l'état liquide, successivement au travers de chaque trou traversant 9 de façon à remplir successivement les espaces entre chaque première puce 10 et la plaque 2, la matière liquide se propageant par capillarité.  In this inverted position, the following operation consists, using at least one needle 21, of delivering a calibrated quantity of the filling material 16, in the liquid state, successively through each through hole 9 so as to successively fill the spaces between each first chip 10 and the plate 2, the liquid material propagating by capillarity.

Lorsque la matière de remplissage 16 est durcie, l'opération 10 suivante consiste, comme le montre la figure 6, à placer l'ensemble obtenu précédemment dans la cavité d'un moule d'injection 22 et à injecter, en avant de la plaque 2, une matière d'enrobage 17 de façon à constituer un bloc d'encapsulation unique 17.  When the filling material 16 is hardened, the following operation 10 consists, as shown in FIG. 6, of placing the assembly obtained previously in the cavity of an injection mold 22 and of injecting, in front of the plate 2, a coating material 17 so as to constitute a single encapsulation block 17.

La dernière opération consiste, comme également représenté sur 15 la figure 6, à effectuer une opération de sciage de l'ensemble obtenu après injection, suivant des lignes 23, pour ainsi obtenir autant de composants semi-conducteurs 1, tels qu'individuellement décrits en référence à la figure 1, que la plaque- support 2 présentait d'emplacements 18.  The last operation consists, as also shown in FIG. 6, in performing a sawing operation of the assembly obtained after injection, along lines 23, so as to obtain as many semiconductor components 1, as individually described in reference to FIG. 1, that the support plate 2 had locations 18.

Dans un exemple, la première puce 10 pourrait contenir des éléments électroniques passifs ou radio-fréquence et la seconde puce 13 pourrait contenir des mémoires.  In one example, the first chip 10 could contain passive electronic or radio frequency elements and the second chip 13 could contain memories.

La présente invention ne se limite pas à l'exemple ci-dessus décrit. Bien des variantes de réalisation sont possibles sans sortir du 25 cadre défini par les revendications annexées.  The present invention is not limited to the example described above. Many alternative embodiments are possible without departing from the scope defined by the appended claims.

Claims (9)

REVENDICATIONS 1. Procédé de fabrication d'un composant semi-conducteur, caractérisé par le fait qu'il consiste: - à réaliser au moins un trou traversant (9) au travers d'une plaque- support (2a) munie, autour de ce trou, de moyens de connexion 5 électrique présentant des zones de connexion électrique (4) sur une face avant; - à fixer sur ladite face avant de ladite plaque-support une puce de circuits intégrés (10) par l'intermédaire de billes de connexion électrique (11) fixées d'une part sur des zones de la face avant de cette 10 plaque et d'autre part sur des plots de connexion électrique (12) de la face arrière de cette puce; - et à délivrer, au travers dudit trou traversant, une matière de remplissage liquide durcissable (16) entre ladite plaque et ladite puce de telle sorte qu'après durcissement, cette matière de remplissage 15 remplisse au moins partiellement l'espace entre cette plaque et cette puce.  1. Method for manufacturing a semiconductor component, characterized in that it consists: - in making at least one through hole (9) through a support plate (2a) provided around this hole , electrical connection means 5 having electrical connection zones (4) on a front face; - To fix on said front face of said support plate an integrated circuit chip (10) by means of electrical connection balls (11) fixed on the one hand on areas of the front face of this plate and d 'other hand on electrical connection pads (12) of the rear face of this chip; - And to deliver, through said through hole, a curable liquid filling material (16) between said plate and said chip so that after hardening, this filling material 15 at least partially fills the space between this plate and this chip. 2. Procédé selon la revendication 1, caractérisé par le fait que lesdites billes de connexion électrique (11) sont noyées dans ladite matière de remplissage (16).  2. Method according to claim 1, characterized in that said electrical connection balls (11) are embedded in said filling material (16). 3. Procédé selon l'une des revendications précédentes, caractérisé par le fait qu'il consiste, ultérieurement, à encapsuler, en avant de ladite plaque, au moins la partie périphérique de ladite puce dans une matière d'enrobage (17a).  3. Method according to one of the preceding claims, characterized in that it consists, subsequently, in encapsulating, in front of said plate, at least the peripheral part of said chip in a coating material (17a). 4. Procédé de fabrication d'un composant semi-conducteur, 25 caractérisé par le fait qu'il consiste: - à réaliser au moins un trou traversant (9) au travers d'une plaque- support munie, autour de ce trou, de moyens de connexion électrique présentant des zones de connexion électrique (4) sur une face avant; - à fixer sur ladite face avant de ladite plaque une première puce de circuits intégrés (10) par l'intermédaire de billes de connexion électrique (11) fixées d'une part sur des zones de connexion électrique (4) de la face avant de cette plaque-support et d'autre part sur des plots de connexion électrique (12) de la face arrière de cette puce; - à fixer par empilage, sur la face avant de ladite première puce, au moins une seconde puce de circuits intégrés (13); - à relier des plots de connexion électrique (14) de la face avant de ladite seconde puce à des zones de connexion électrique de la face avant de ladite plaque par l'intermédiaire de fils de connexion électrique (15); - et à délivrer, au travers dudit trou traversant (9), une 10 matière de remplissage liquide durcissable (16), entre ladite plaque et ladite puce, de telle sorte qu'après durcissement, cette matière de remplissage remplisse au moins partiellement l'espace entre cette plaque et cette puce.  4. A method of manufacturing a semiconductor component, characterized in that it consists in: - making at least one through hole (9) through a support plate provided, around this hole, with electrical connection means having electrical connection areas (4) on a front face; - to fix on said front face of said plate a first integrated circuit chip (10) by means of electrical connection balls (11) fixed on the one hand to electrical connection areas (4) of the front face of this support plate and on the other hand on electrical connection pads (12) of the rear face of this chip; - fixing by stacking, on the front face of said first chip, at least one second integrated circuit chip (13); - connecting electrical connection pads (14) of the front face of said second chip to electrical connection areas of the front face of said plate by means of electrical connection wires (15); - and to deliver, through said through hole (9), a curable liquid filling material (16), between said plate and said chip, so that after hardening, this filling material at least partially fills the space between this plate and this chip. 5. Procédé selon la revendication 4, caractérisé par le fait que 15 lesdites billes de connexion électrique (11) sont noyées dans ladite matière de remplissage.  5. Method according to claim 4, characterized in that said electrical connection balls (11) are embedded in said filling material. 6. Procédé selon l'une des revendications 4 et 5, caractérisé par le fait qu'il consiste, ultérieurement, à encapsuler, en avant de ladite plaque, au moins la partie périphérique desdites puces et lesdits fils de 20 connexion électrique dans une matière d'enrobage (17a).  6. Method according to one of claims 4 and 5, characterized in that it consists, subsequently, in encapsulating, in front of said plate, at least the peripheral part of said chips and said electrical connection wires in a material coating (17a). 7. Procédé selon l'une des revendications 3 et 6, caractérisé par le fait que ladite encapsulation est réalisée par surmoulage.  7. Method according to one of claims 3 and 6, characterized in that said encapsulation is carried out by overmolding. 8 Composant semi-conducteur, caractérisé par le fait qu'il comprend une plaque-support (2a) présentant au moins un trou 25 traversant (9) et munie, autour de ce trou, de moyens de connexion électrique présentant des zones de connexion électrique (4) sur une face avant; une puce de circuits intégrés (10) fixée sur ladite face avant de ladite plaque par l'intermédaire de billes de connexion électrique (11) fixées d'une part sur des zones de connexion électrique (4) de la face 30 avant de ladite plaque-support et d'autre part sur des plots de connexion électrique de la face arrière de cette puce; une matière de remplissage (16) remplissant au moins partiellement l'espace entre cette plaque et cette puce, et une matière d'enrobage encapsulant au moins la périphérie de ladite puce en avant de ladite plaque-support.  8 Semiconductor component, characterized in that it comprises a support plate (2a) having at least one through hole (9) and provided, around this hole, with electrical connection means having electrical connection areas (4) on a front face; an integrated circuit chip (10) fixed to said front face of said plate by means of electrical connection balls (11) fixed on the one hand to electrical connection zones (4) of the front face of said plate -support and secondly on electrical connection pads of the rear face of this chip; a filling material (16) at least partially filling the space between this plate and this chip, and a coating material encapsulating at least the periphery of said chip in front of said support plate. 9. Composant selon la revendication 8, caractérisé par le fait qu'il comprend en outre une seconde puce de circuits intégrés (13) fixée sur ladite première puce (10) et des fils de connexion électrique (15) reliant des plots de connexion électrique (14) de la face avant de ladite 5 seconde puce à des zones de connexion électrique (4) de la face avant de ladite plaque; ladite matière d'enrobage (17a) encapsulant, en avant de ladite plaque, au moins la partie périphérique desdites puces et lesdits fils de connexion électrique.  9. Component according to claim 8, characterized in that it further comprises a second integrated circuit chip (13) fixed on said first chip (10) and electrical connection wires (15) connecting electrical connection pads (14) from the front face of said 5 second chip to electrical connection zones (4) of the front face of said plate; said coating material (17a) encapsulating, in front of said plate, at least the peripheral part of said chips and said electrical connection wires.
FR0307283A 2003-06-17 2003-06-17 Semiconductor component manufacturing method, involves delivering hardening liquid filling material between support-plate and integrated circuit chip so that material partially fills space between plate and chip Pending FR2856516A1 (en)

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FR0307283A FR2856516A1 (en) 2003-06-17 2003-06-17 Semiconductor component manufacturing method, involves delivering hardening liquid filling material between support-plate and integrated circuit chip so that material partially fills space between plate and chip

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FR0307283A FR2856516A1 (en) 2003-06-17 2003-06-17 Semiconductor component manufacturing method, involves delivering hardening liquid filling material between support-plate and integrated circuit chip so that material partially fills space between plate and chip

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0684644A1 (en) * 1994-05-25 1995-11-29 Nec Corporation Method for manufacturing bump leaded film carrier type semiconductor device
US20020125561A1 (en) * 1997-01-23 2002-09-12 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument
US20020130404A1 (en) * 2001-03-19 2002-09-19 Toshihiro Ushijima Semiconductor module in which plural semiconductor chips are enclosed in one package
US6544814B1 (en) * 1999-07-27 2003-04-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0684644A1 (en) * 1994-05-25 1995-11-29 Nec Corporation Method for manufacturing bump leaded film carrier type semiconductor device
US20020125561A1 (en) * 1997-01-23 2002-09-12 Seiko Epson Corporation Film carrier tape, semiconductor assembly, semiconductor device, and method of manufacturing the same, mounted board, and electronic instrument
US6544814B1 (en) * 1999-07-27 2003-04-08 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a packaged semiconductor device, and a semiconductor device manufactured thereby
US20020130404A1 (en) * 2001-03-19 2002-09-19 Toshihiro Ushijima Semiconductor module in which plural semiconductor chips are enclosed in one package

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