FR2855308A1 - Non-volatile memory cell e.g. electrically EPROM, analog parameter controlling method for integrated circuit, involves determining value of intrinsic analog parameter of system, when magnitude of system attains threshold - Google Patents

Abstract

The method involves positioning a multi-level system of a non-volatile memory cell in operating conditions to which the magnitude of the system follows a determined threshold value. The operating conditions of the system are evaluated in a manner to allow the magnitude to attain the threshold value. A value of an intrinsic analog parameter of the system is determined, when the magnitude attains the threshold value. Independent claims are also included for the following: (a) an integrated circuit having a programmable memory (b) a control apparatus cooperating with a device of controlling a non-volatile memory cell.

Description

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Method and device for controlling an analog parameter conditioning the level of an output of a multi-level system, for example a non-volatile memory cell such as an EEPROM
The invention relates to systems intended to present a quantity to be identified at one of a finite number of preset levels, the identification being conditioned by at least one intrinsic analog parameter of the system. An example of such a system is a memory cell, in particular a non-volatile memory, such as an electrically erasable programmable memory, known by the acronym EEPROM (from the English "electrically erasable read-only memory) .

 For a memory with binary output, the levels are two in number and correspond to a logic state 1 or 0. The identification of the level within the cell depends on an analog voltage (or electric charge) stored in a so-called transistor "storage".

 In the case of an EEPROM memory, each cell is programmable to store binary data 0 or 1 by playing on the analog characteristics of a storage transistor of the floating gate transistor type of the programmed cell (this transistor is also designated by the acronym FGT from English "floating gate transistor").

 More particularly, the programming consists in fixing the threshold of the gate-source bias voltage Vgc of the transistor FGT from which this transistor becomes conductive. The transistor is considered to be in the conducting state when it conducts a current designated ID, which is beyond a

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 nominal threshold, called Ilect read current, determined by a reference transistor outside the memory plane and associated with a read amplifier.

 This threshold of the bias voltage of the transistor FGT, known as the threshold voltage, is programmed by injecting electrical charges (electrons or holes) at the level of the channel under the floating gate. This injection is carried out during a programming operation, by applying an appropriate programming voltage to the gate connection of the FGT transistor. a cell can thus have one of three possible thresholds: - cell threshold in the virgin state (designated VTvierge) - cell threshold in the state programmed by writing (designated VTinscr 'of "registration", synonymous term "write"), and - cell threshold in the programmed state in the erased state (designated VTeff).

(These Virgin thresholds 'VTinscr' and VTeff are collectively designated by the abbreviation VT.)
Typically, the coding and reading of binary data takes place as follows: - logic state 0: - programmed by applying a programming voltage to the floating grid of the cell, positioning the threshold voltage at VTinscr '- identified in reading by the conductive state of transistor FGT (ID> Ilect) for a predetermined bias voltage Vgs of the read mode; - logical state 1:

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 - programmed by applying a programming voltage to the floating gate of the cell, positioning the threshold voltage at Veff, - identified in reading by the non-conductive state of transistor FGT (ID <Iiect.) for this bias voltage Vgs reading mode.

 It is therefore understood that the thresholds VT are critical for correctly establishing the data stored by a cell. These VT thresholds are analog quantities conditioned by intrinsic parameters of the storage transistor (in this case the FGT transistor), which are themselves analog or subject to manufacturing variability.

 The reading amplifier and its reference transistor which fixes the reading current Ilect being common to a plane containing many cells, it is important to ensure that each of them is homogeneous in its behavior, and in particular that the cells of the plan do not show significant variations in their individual threshold voltage value.

 However, until now, there is no means of internal test which makes it possible to clearly determine the values of individual thresholds of the cells.

 The evolution of the market for portable devices, such as smart cards or mobile communication media directly influences the use of memories, in particular EEPROM memories. In this context, EEPROM memories have become essential in recent years for any application which requires non-volatile semiconductor memory.

 To better locate the factors which influence the threshold voltage of an FGT transistor, the mechanisms and

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 the operating context of this transistor will now be explained in more detail.

 As shown in FIG. 1, the architecture of an EEPROM memory 1 is generally similar to that of a RAM type RAM (acronym for "random access memory"). It includes a plan 2 of memory cells, each identified by its position in a row and in a column. This plan is surrounded, in a conventional manner, with the following elements: - a control logic with register 4, - a line decoder 6 for the selection of an active line, - a column decoder 8 ("bit line" in English) ) for the selection of the active column, - high-voltage flip-flops 10 for storing data to be programmed in the words of the memory, - a sense amplifier 12 ("sense amplifier" in English) for the read operation, and - a high voltage generator 14.

It should also be noted that the architecture of the EEPROM memory also has specific features directly linked to its programming mode. In order to be able to carry out a data storage operation, the EEPROM structure includes in its chip a high voltage generator, such as a charge pump.

 Typically, the plan 2 of memory cells can be organized according to either an exclusive OR logic or an exclusive AND logic (NOR and NAND respectively in English).

 FIG. 2 illustrates the case of an exclusive OR organization of the memory plane 2, showing a block of four cells 16a-16d arranged on two word selection lines WLi and Wi + 1 and two columns BLj and BLj + 1.

Each cell (generically designated 16) is also connected to the drain of an SST transistor of the memory plane 2,

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 the source of this transistor being connected to ground and its control gate connected to an input CS.

 FIG. 3 represents the elementary structure of a cell, the example being taken for cell 16a (CELL i. J) of FIG. 2, connected to the selection line WLi and the column BLj. This cell includes two MOS transistors in series: - a first transistor STij, called the selection transistor, having its source connected to its column line BLj, its drain connected to a common node Dij, and its gate connected to the selection line WLi. This transistor essentially serves as a logic switch for activating the cell in response to the addressing BLj and WLi; and a second transistor FGTij, called a reading transistor, of the floating gate type, having its source connected to the common node Dij, its drain connected to the source S of the transistor STij, and its control gate CG selectively connected to the output CG: either from a high voltage generator during programming, or at the output of a constant nominal value voltage source during reading.

 Depending on the memory plan configuration, different procedures can be used for data storage. In the example considered, the procedure consists in erasing the word which includes the bits to be changed and then in rewriting the new information in their respective cells. With such a procedure, only one write operation can be performed one bit at a time.

 The (puer of the EEPROM memory cell is the floating gate FGT storage transistor. The threshold voltage VT transistor of an FGT can be changed respectively from a high state to a low state, or vice versa, in correspondence with two logical values of the memory cell. The value of VT of a

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 transistor FGT changes when the cell is programmed by a write or erase operation. When a negative electrical charge is stored on the floating grid, the value of VT increases: the cell is then considered to be erased, and its logical value is equal to "1". Conversely, when the charge on the floating gate is positive, the value of VT decreases: the cell is then considered to be written, and its logical value is equal to "0". To program a cell, a high voltage Vpp is applied to: the bit line node BL1 ("bit line node" in English) of cell 16 for a write operation, the control grid node (CG) for an erase operation.

 To carry out a read operation, a predetermined potential VCgref is applied to the control gate of the transistor FGT of a selected cell, by activating the transistor STij, linked to the read amplifier, which applies the read current Ilect . on the bit line.

 If the cell read is in the written state, the write current Ilect. scans the cell and the amplifier switch.

 If the cell is in the erased state, the transistor FGT is blocked, the cell is not traversed by a current, and there does not occur any switching at the output of the sense amplifier.

 In the case of an EEPROM of so-called "Flotox" technology, which has now become the industry standard, the transfer of electrical charge from the drain node to the floating gate node is due to the Fowler-Nordheim tunnel effect. This tunnel effect is entirely dependent on the following factors:

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 - the geometry of the cell, - the high voltage applied to program the cell, and - the quality of the manufacturing process.

 All of these elements lead to critical problems in the design and control of industrial processes in the field of non-volatile memories.

A variation, even small, of any of these factors from one cell to another of a memory plane has the direct effect of widening the distribution of the threshold voltages, which results in a decrease in the both overall memory performance and manufacturing performance. Knowing that the improvement of the manufacturing yield conditions the success of a production unit, it is important to be able to have diagnostic techniques which are specific to the product and which allow a saving of time. With regard to the EEPROM memories, it clearly appears that the knowledge of the threshold voltage of all the cells of a memory plane is a key parameter in the development of a precise diagnostic methodology.

 The conduct of functional tests of an EEPROM memory involves more critical constraints than that of a conventional random access memory (RAM). Indeed, the programming operation is far too costly in time to allow the use of a test algorithm based on a write-erase sequence, such as the March test. In this way, simple test sequences are adopted for the EEPROM memories, such as - all the cells at "1", all the cells at "O", - a "checkerboard" pattern, - a line bar and a bar column,

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 - a diagonal pattern, - etc.

 More information on these techniques is given in the publication "Flash Memories", author M.

Cappelletti, publisher Kluwer Academic Publishers, 1999.

 All of these simple test algorithms require only an erase / write operation followed by a read operation.

 Furthermore, it is important to remember that the reading time represents less than 0.1% of the programming time. In terms of diagnosis, a logical bitmapping ("digital bitmapping" in English) is performed for each of these test algorithms.

 With regard to the analysis of dysfunctions of repetitive structures, such as with memory cells, various methods have been proposed. By way of example, the article by D. Lepejian et al "An automated failure analysis" (AFA) methodology for repeated structures ", Proc. 12th IEEE VLSI Test Symp., IEEE Computer Society Press, Los Alamitos, Calif. Pp .319., 1994. Studies the case of repetitive structures and relates to a dysfunction analysis program known by the term "CARAFE". The latter is described in the article by A.Jee et al., "Carafe: A software tool for failure analysis ", Proc.

Of Int'l Symp. On Testing and Failure Analysis, pp. 143-149, 1993.

 Other methods aimed at improving performance are based on digital memory bit mapping, such as that proposed in the article by J. Segal et al., "Using Electrical bitmap results from Embedded memory to enhance yield", IEEE Design & Test of Computer, Vol.18, No.3, pp.28-39, MayJune 2001.

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 These methods are of general application and can be used successfully with non-volatile memories. However, they do not take into account the analog storage mechanism, namely the switching of threshold voltage, of an EEPROM memory.

 In summary, the EEPROM memories have an analog type storage mechanism using a threshold voltage switchover, but are tested using conventional random access memory (RAM) algorithms, and are diagnosed by means of a mapping. logical bit.

 It appears from this state of facts that the conventional functional tests applied to EEPROM memories do not provide any information of analogical nature, in particular of threshold voltage values VT of the individual cells, whereas such information would make it possible to improve the test phase. /diagnostic.

 In view of the above, the invention proposes, according to a first aspect, a method of controlling a system, this system being intended to present a quantity to be identified with one of a finite number of preset levels, l the identification being conditioned by at least one intrinsic analog parameter of the system, characterized in that it comprises a determination of the value of said intrinsic analog parameter.

 Advantageously, the value of the intrinsic analog parameter is determined internally by a device in which the system is integrated and is presented at the output of this device for external control.

 Preferably, the value of the intrinsic analog parameter is presented at the output of the device in digital form.

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 In a possible application, the or each intrinsic analog parameter conditions a threshold by which a preset level is identified under determined operating conditions, the method comprising the steps of: - positioning the system under operating conditions at which the quantity is located a determined side of said threshold, - changing the operating conditions of the system in the direction bringing said quantity towards the threshold, - when said quantity reaches or crosses the threshold, determining the value of an identifiable parameter or linked to said intrinsic analog parameter.

 The method can advantageously be implemented in a device comprising a set of individually identifiable systems, where said determination of the said parameter is carried out individually for each system being checked.

 The value of said determined parameter can be listed with an identification of the individual system from which it was determined, for example in the form of a map.

 The system can be a cell of a non-volatile memory, the method being carried out on at least one cell of said memory.

 The memory can be of the electrically erasable programmable type, known by the acronym EEPROM (from the English electrically erasable programmable read only memory).

 The intrinsic analog parameter can then be the threshold value of a memory cell, for a written, blank or erased cell, and said quantity can be the current passing through the cell or

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 the bias voltage of a storage transistor in read mode.

 In one embodiment, the threshold value is assimilated to the value of the bias voltage of a storage transistor of the cell in read mode, at which this storage transistor passes a determined current.

 The threshold value can also be assimilated to the value of the current passed by a cell storage transistor in read mode when this transistor is biased at a voltage positioned at a reference value.

 Preferably, - to determine the threshold of a blank or erased cell, the bias voltage of the storage transistor to which this transistor conducts a current is determined, the value of which crosses a substantially fixed threshold, - to determine the threshold of a written cell, the limit value of the current which the storage transistor can conduct for a substantially fixed bias voltage (Vcg) thereof is determined.

 The threshold may correspond to a threshold of the storage transistor, which is determined by the logic state switching condition of a sense amplifier to which said cell is functionally connected, where: - to determine the threshold of a blank cell or erased, a reading current of the reading amplifier is maintained substantially constant and the bias voltage of the transistor is changed so as to bring the current passed through it to this reading current, until a tilting of d logic state of the sense amplifier, and the value of this voltage is determined

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 polarization at which the read amplifier switches logic state, this bias voltage being assimilated to the threshold voltage of the blank or erased cell; and to determine the threshold of a written cell, the bias voltage of the transistor is kept substantially constant and said current flowing through the cell is changed until the logic amplifier of the read amplifier switches, the switch point corresponding to the crossing of the current limit value that the cell can conduct for said bias voltage of the transistor, this current limit value passing through the cell being assimilated to the threshold of the written cell.

 To determine the threshold of a cell, whatever its state: blank, erased, or written, it is possible to determine the value of the current passed by the storage transistor for a substantially fixed bias voltage thereof.

 The switching threshold of the storage transistor can then be determined by the logic state switching condition of a sense amplifier to which said cell is functionally connected, where: - to determine the threshold of a cell whether it is its state: blank, erased, or written, the bias voltage of the transistor is kept substantially constant and the said current flowing through the cell is changed until the logic state of the read amplifier changes, the switching point corresponding to the crossing of the limit value of said current which the cell can conduct for said bias voltage of the transistor, this current limit value passing through the cell being assimilated to the threshold of the cell.

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 The bias voltage applied to the cell storage transistor and / or the reference current can be changed over a range of variation which covers the range of values accepted by the memory specification for the threshold voltage and / or the threshold current considered.

 The bias voltage applied to the cell storage transistor and / or the current flowing through the cell can be changed incrementally by means of a programmable voltage source and / or a programmable current source, the or each source, respectively. being controlled digitally by programming means, the latter being also used to provide an output to the outside, in digital form, an expression of the value of the threshold considered, the values of the bias voltage or of said current flowing through the cell giving the voltage or current causing said change in logic state of the sense amplifier to the nearest increment.

 The programming means may include a shift register, the parallel outputs of which serve to control, by their logic state, respective parts of the current source and / or of the voltage source, so as to produce a range of reference current values. evolutionary and / or a range of bias voltage values applied to a cell storage transistor, as a function of the bit pattern loaded in the register, during the evolution of the values produced, this pattern controlling a current value or of voltage, and in that this bit pattern is extracted, when that programs the current value or the voltage value causing a crossing of threshold in reading, as

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 as information on the programmed current or voltage value.

 The bit pattern can control coefficients of an elementary value of current or voltage produced by internal circuits of the memory used in its normal operating mode.

 At least one of: - the programmable voltage generator, in particular a reference voltage source thereof, - the programmable current generator, in particular a reference current source thereof, - the programming means, can be realized with circuit elements used by the memory in normal operating mode.

 The method can be carried out with means embedded in said memory.

 The method can be managed, at least in part, by a memory state machine.

 The method can advantageously include a step of selecting an individual cell from the memory, said determination of the value of the intrinsic analog parameter applying specifically to this cell.

 The method can be used to control said intrinsic analog parameter relating to each of a designated set of listed points, each point comprising a said system, characterized in that the results of the control obtained from the points are produced under a corresponding listed form for analysis or diagnostic purposes.

 The method can be applied to a memory, the points listed being at least part of the set of memory cells, the intrinsic analog parameter being a threshold value, the

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 indexed form of the control results in the form of a mapping of the threshold values like the mapping of the cells in their memory plane, thus defining an analog bit mapping usable in addition to a conventional binary bit mapping.

 It is thus possible to produce a statistical distribution of the values of the intrinsic analog parameter obtained on the controlled points, for example in the form of a histogram, in order to carry out a statistical analysis of the variations of this parameter on the set of controlled points.

 According to a second aspect, the invention relates to a follow-up of the control method to the first aspect, for the acquisition of values of said analog parameter within the framework of a test of devices integrating at least one said system, such as programmable memories. , the control being carried out on at least some of said devices on manufacturing batches, so as to produce at least one history relating to the manufacturing process of the device, for example, in the case of a programmable memory, of the different states of certain at least cells: blank, erased, or written, in order to obtain monitoring and manage information on possible drifts and dispersion of parameters.

 According to a third aspect, the invention relates to a covering of the control method according to the first aspect for the acquisition of values of said analog parameter within the framework of a diagnosis on a faulty device or in the process of development, such as a programmable memory, in which at least one value of said parameter from a faulty system is extracted for analysis, for example from an analog bit mapping.

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 According to a fourth aspect, the invention relates to a copper setting of the control method according to the first aspect, for the acquisition of values of said analog parameter within the framework of a study of systems, for example cells, of a memory. programmable, so as to establish whether the systems as a whole are healthy or, more generally, different.

 According to a fifth aspect, the invention relates to a device for controlling a system, this system being intended to present a quantity to be identified with one of a finite number of preset levels, the identification being conditioned by at least one intrinsic analog parameter of the system, characterized in that it comprises means for determining the value of said intrinsic analog parameter.

 The aspects presented within the framework of the process apply mutatis mutandis to this device.

 The device can be connected to a set of individually identifiable systems, the means for determining the value of said parameter operating individually on each system being checked.

 The device can include means for listing the value of said determined parameter with an identification of the individual system from which it was determined, for example in the form of a map.

 In the preferred embodiment, the system is a cell of a non-volatile memory, the device being configured to perform control on at least one cell of said memory.

 In this case, the device can advantageously include means for selecting an individual memory cell, said determination of the

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 value of the intrinsic analog parameter applying specifically to this cell.

 The invention also relates to a memory, in particular a programmable memory, such as a so-called EEPROM memory, characterized in that it includes means for carrying out at least part of the method according to the first aspect and / or the device according to the second aspect.

 According to a sixth aspect, the invention relates to a device according to the fifth aspect, programmed to carry out the method according to the first aspect.

 According to a seventh aspect, the invention relates to programmable memory, characterized in that it embeds a device according to the fifth aspect.

 According to an eighth aspect, the invention relates to an integrated circuit comprising a programmable memory, characterized in that it embeds a device according to the fifth aspect.

 According to a ninth aspect, the invention relates to a control device intended to cooperate with the device according to the fifth aspect, characterized in that it comprises an input intended to functionally connect to an output of the device producing an expression of the value of the intrinsic analog parameter.

 The input may be a digital input intended to receive a bit pattern which encodes the expression of the value of the intrinsic analog parameter, the apparatus comprising data storage means making it possible to extract exploitable information from this expression. encoded.

 According to a tenth aspect, the invention relates to an electronic medium characterized in that it contains result data for the values of said intrinsic analog parameter, listed at the end.

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 an inspection carried out on a listed set of inspection points in accordance with the first, second, third or fourth aspect.

 The data can constitute at least an analog bit map of the cells of a programmable memory having at least one threshold parameter of a set of said cells.

 The electronic medium can also comprise data of a statistical distribution of the values of the intrinsic analog parameter, for example in the form of a histogram, making it possible to perform a statistical analysis of the variations of this parameter on all of the points checked.

 The invention and the advantages which ensue from it will appear more clearly on reading the preferred embodiments, given purely by way of nonlimiting examples, with reference to the appended drawings, in which: - Figure 1, already described, is a diagram block representing the functional arrangement of a conventional EEPROM memory, - Figure 2, already described, is a diagram showing the arrangement of a block of four cells in a memory plane of an EEPROM memory, such as that of the FIG. 1, FIG. 3, already described, is an electrical diagram of a memory cell of FIG. 2, - FIG. 4, represents a curve of the evolution of the current ID passed by a memory cell in read mode in function of the bias voltage of the control gate of its storage transistor, on axes where the ordinate indicates the current ID passed by the cell and the abscissa represents the bias voltage of the (floating) gate of the trans storage istor, and the logical states 0 and 1 at the output of

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 the read amplifier as a function of this development, further showing the level of the read current Ilect, - Figure 5 is a block diagram showing the functional arrangement of an EEPROM memory in accordance with a first embodiment of the invention, FIG. 6 is an electrical diagram of a programmable current generator implemented in the memory of the first embodiment, - FIG. 7 is a diagram showing a shift register and its input and output signals, used for programming the programmable current generator of FIG. 6, FIG. 8 is an electrical diagram of a programmable voltage generator additionally stored in the memory of the first embodiment, - FIG. 9 is a diagram showing a register at offset and its input and output signals, used for programming the programmable voltage generator of Figure 8, Figure 10 shows, on the same axes as used for the FIG. 4, two curves of the evolution of the current ID passed by a memory cell in read mode, respectively for a blank cell and an erased cell, with for each of the curves the threshold voltage windows, on the one hand conforms to a specification and on the other hand provided for the measurements during the control, FIG. 11 represents, on the same axes as used for FIG. 4, a curve of the evolution of current ID passed by a memory cell in read mode, further showing the successive values of bias voltage of the control gate of the storage transistor during checking and their coding

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 respective at the level of the shift register of FIG. 9, FIG. 12 represents, on the same axes as used for FIG. 4, a curve of the evolution of current ID passed by a memory cell in read mode, showing the threshold current windows on the one hand conforms to a specification and on the other hand provided for measurements during the control, - figure 13 represents, on the same axes as used for figure 4, a curve of the evolution of current ID passed by a memory cell in read mode, further showing the successive values of read current Ilect of the read amplifier during control and their respective coding at the level of the shift register of FIG. 7, - FIG. 14 is a block diagram showing the parts of the memory according to the first embodiment involved in the control of the threshold parameters and the connection of this memory with a control device, in this case test and dia gnostic, - Figure 15 is a block diagram representing the functional arrangement of an EEPROM memory according to a second embodiment of the invention, Figure 16 shows, on the same axes as used for Figure 4, a curve of the change in current ID passed by a memory cell in read mode as a function of the bias voltage of its storage transistor, and the logic states 0 and 1 at the output of the read amplifier as a function of this change, further showing the level of the threshold current IT, - figure 17 represents, on the same axes as used for figure 4, a curve of the evolution of current ID passed by a memory cell in mode

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 reading as a function of the bias voltage of its storage transistor, and the equivalence between the specification and measurement windows, respectively in terms of said current ID and in terms of said bias voltage, - Figure 18 is a block diagram showing the parts of the memory according to the second embodiment intervening in the control of the threshold parameters and the connection of this memory with a control device, in this case test and diagnostic, - Figure 19 represents the evolution of the programming voltage of a memory cell on different phases: cell initially blank, erased, written and read, - Figure 20 represents the evolution of the threshold voltage VT, for the same cell and on the same window than in Figure 19, - Figure 21, represents the changes in current ID of a cell during incremental steps applied by the current generator to determine r its current threshold, FIG. 22 represents the evolution of the logic states of the sense amplifier for the same cell and over the same time window as for FIG. 19, FIGS. 23a, 23b and 23c schematically represent plans of 4x4 cells in an analog bit mapping, where each cell is listed with its threshold value in the example in terms of threshold current respectively for the case of blank cells, written and erased, and Figures 24a, 24b and 24c are statistical distributions in the form of a histogram showing the percentages of cells in a memory map

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 presenting a given threshold current value, these three figures respectively corresponding to blank, erased and written cells.

 The embodiments of the invention provide a methodology dedicated to the diagnosis of EEPROM memories. This methodology is based on integrated means, that is to say embedded in the memory, for extracting the threshold voltage and the test sequence, executed outside the memory, which is related thereto.

Thanks to the use of these additional means, it is possible to quickly and precisely extract the threshold voltages from all the cells of a memory.

 The conventional diagnostic methodology is then modified to take into account the threshold values delivered by the memory tested or analyzed in the case of a diagnosis.

 In the description which follows, the aspects of the introductory part which are relevant to the embodiments, in particular in the explanations of FIGS. 1 to 3 are incorporated by reference therein and will not be repeated for the sake of brevity. In all the figures which follow, the same references designate the same elements.

 As explained in the introductory part with reference to FIGS. 2 and 3, the memorization mechanism of an EEPROM memory is directly controlled by the programming of the threshold voltage VT of the floating gate transistor FGT. In this way, to improve the diagnostic process of an EEPROM memory, the embodiments provide for extracting these threshold voltage values from the memory, during the functional tests.

 First, the threshold voltage value must be defined under the conditions of the component.

 Figure 4 shows:

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 on the one hand the curve 4-1 of the current flowing through the transistor FGT, that is to say the drain current ID, as a function of its gate-drain bias voltage Vcg, bias where the abscissa represents the voltage Vcg applied to the control gate of the FGT transistor (see Figure 3), and the ordinate represents the drain current ID. This curve corresponds to the internal characteristics of the isolated cell, apart from its behavior seen from the output of the read amplifier; - for the same cell in the component, seen from output 4-2 of the read amplifier against the voltage applied to the control gate Vcg for a read current Ilect. given from this amplifier.

 From these curves, the following observations make it possible to define the threshold voltage: - when the voltage Vcg of the control gate is below the threshold voltage VT (whether it is the threshold of a blank cell , written or deleted) for an Ilect reading current. given, the cell is not capable of conducting the reading current, and the output of the amplifier has a high state (logic 1), - when the voltage Vcg is above the threshold voltage VT for a current Ilect read signal, the cell lets the read current flow, and the output of the read amplifier then goes low (logic 0). As an indication, the reading current passed through the cell is of the order of a few microamps, typical values being between 5 and 10 microamps. Some memories may have a higher reading current, of the order of 25 microamps.

 Consequently, the threshold voltage is given by the voltage Vcg applied to the control grid at

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 moment when the output of the sense amplifier switches, for a given Ilect read current thereof.

 The Ilect read current produced by the read amplifier is injected into the cell, by means of a current mirror; the current ID flowing through the cell and therefore the storage transistor FGT is then equal to this reading current (ie ID = Ilect).

It is noted that the value of the threshold voltage VT is given by the intersection of the aforementioned reading current Ilect and the drain current ID in its evolution 4- 1. We can then obtain a threshold voltage value VT in two ways : - way i), by fixing a reading current Ilect to a chosen value, and by varying the voltage Vcg at the control gate of the transistor FGT, - way ii) by keeping this voltage Vcg fixed at a given value, and varying the reading current Ilect-
A first embodiment of the invention will now be described, where the threshold voltage values are obtained using the two aforementioned ways, in particular: - way i) to obtain the threshold value VTvierge of a cell 16 blank and to obtain the threshold value VTeff of an erased cell, and the method ii) to obtain the threshold value VTinscr of a written cell.

 As shown in FIG. 5, the EEPROM memory 110 integrating this first embodiment implements at the same time: - a programmable voltage generator 18 to allow the extraction of the threshold voltage value VTvierge from a blank cell and of the threshold voltage

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 VTeff of an erased cell, ie the extraction of a positive threshold voltage. This generator 18 is advantageously integrated with the circuits of the high voltage generator 14 conventionally used, with which it can share common elements, and - a programmable current generator 20 to allow the extraction of the threshold voltage value VTinscr from a written cell, ie the extraction of a negative threshold voltage. Likewise, this generator 20 is advantageously integrated with the circuits of the sense amplifier 12, with which it can also share common elements. Note that any conventional EEPROM memory follows a reference current source; this source can be used to supply the reference current IREF used by this generator 20.

 The memory 110 also integrates: - circuits 22 for routing an overvoltage, designated Vboost, whose role will appear below, and - circuits 24 for routing the read voltage Vlect.

 FIG. 6 illustrates the programmable current generator 20. That is based on a number N of identical elementary circuits 26-1 to 26-N (generically designated by the reference 26) comprising two transistors in series: - a first transistor 28 associated with a current mirror, having the drain connected to a supply voltage Vdd and the source connected to the common node 30 of the two transistors, and - a second transistor 32 of PMOS type, serving as a switch, having the drain connected to the common node 30 and the source connected to a common output 34 which produces the programmed current.

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 The dotted lines connecting different points of these transistors correspond to lines of connection to the substrate of the integrated circuit forming the memory; the same is true for the programmable voltage generator circuit of FIG. 8.

 Each first transistor 28 receives on its control gate a reference current IREF coming from a current generator 36, which constitutes a part of the sense amplifier 12 moreover used in normal operating mode of the memory 110. The generator current 36 comprises, conventionally, a constant current source 38 connected on the one hand to ground and on the other hand to the gate and to the drain of a MOS transistor 40, the latter being mounted as a diode. The source of this transistor is connected to a supply voltage and constitutes the transistor symmetrical with respect to the first transistors 28. The output of the current IREF is taken at the common node between the transistor 40 and the current generator 38.

 In this way, each of the N elementary circuits constitutes a current generator capable of contributing a current of IREF to the output 34 of the reading current Ilect. The activation of the IREF output of an elementary circuit 26-i (for 1 # i # N) is controlled by the logic level of a signal EPIi presented to the gate of its switching transistor 32. As regards a PMOS transistor, the IREF output will be active when the signal EPIi = 0 and blocked when EPIi = l.

 As shown in FIG. 7, the N signals EPIi are supplied on N parallel (parallel) outputs of the respective stages of a shift register 42 to N stages, respectively ED1 to EDN. This register also includes an Eser serial input, a Ser serial output for a FIFO type register function, as well as a Clk clock input for timing.

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 the advancement of the digital data along the successive stages ED1 to EDN of the register 42.

 As shown in FIG. 8, the programmable voltage generator 20 is designed as the counterpart, in terms of voltage, of the programmable current generator 18.

 It comprises two main blocks: a block 46 of generators of reference voltages, which comprises M identical stages, respectively 48-1 to 48-M, each stage having an output, respectively 50-1 to 50-M which supplies a voltage which is specific to him. This voltage is equal to a reference voltage VREF multiplied by an integer ranging from 1 to M, so that each stage 48-j (for 1 # j # M) produces at output 50-j a voltage equal to j. VREF.

 a block of programmable switches 52, which includes M individual switches, respectively 54-1 to 54M. Each switch 54-j has an input connected to the output 50-j of a respective stage 48-j of the block 46 of voltage generators and an output 56, shared with all the other switch outputs. This common output 56, which constitutes the output of the programmable voltage generator 44, is selectively connected to the gate of an FGT transistor of a cell via the routing circuit.

 Each stage 48-j of the block of voltage generators 46 comprises a first and a second transistors in series 58 and 60, the source of the first being connected to the drain of the second to a common neud which constitutes the output 50-j of the stage . These two transistors 58 and 60 are also connected to each other by their gate. The drain of the first transistor 58 is connected to an input voltage VEN and the source of the second transistor 60 is connected to a predetermined potential.

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 This configuration is dimensioned so that each stage 48-j produces its aforementioned specific voltage of j. VREF.

 Each individual switch 54-j of the block of programmable switches 52 comprises a first and a second parallel transistors 62 and 64, of opposite polarity, each connected by its source / its drain to the respective output 50-j of a stage 48- j of the voltage generator and by its drain / source at common output 56. The first and second transistors 62 and 64 of a switch 54-j operate in complementary logic so as to open the connection between output 50-j and the common output 56 when their gates this command are at a logic voltage 1 and close this connection otherwise.

 The gates of the first and second transistors 62 and 64 of the programmable switch block 52 are connected to respective parallel outputs EPV1 to EPVM of a shift register 66 with M stages, respectively EU1 with EUM.

 As shown in FIG. 9, this register comprises a clock input Clk for the timing of the propagation of the data, a serial input EVser and a serial output SVser, in a similar manner to the register 42 of FIG. 7. Of course, the shift registers 42 and 66 can be physically the same register to be reconfigurable to output either the EPI1EPIN signals or the EPV1-EPVM signals.

 The operation of the first embodiment will now be described.

 Under normal operating conditions of the component, the gate control voltage of the transistor FGT is fixed at a value in a range between OV and the cell threshold voltage erased so as to distinguish between a write state (where the

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 cell conducts read current) and an erase state (where the cell does not conduct read current).

Now, under the functional test conditions, the gate voltage must be variable in order to reproduce, one by the virgin cell threshold voltage, designated VTvierge, and on the other hand the erased cell threshold voltage, designated VTeff '
It should be noted that the same structure is partially used to extract both the threshold voltage VTvierged from a blank cell and the threshold voltage VTeff from an erased cell. The only differences concern the bias voltage Vin, which can be positioned at two different values: - an overvoltage value Vboost, produced by the overvoltage generator 22 (cf. FIG. 5), to extract the threshold voltage value from a cell deleted VTeff 'For more information concerning this overvoltage value, reference may be made to the article by T. Tanzawa et al. "Optimization of wordline booster circuits for single power supply flash memories", IEEE J. of Solid State Circuits, Vo1.32, No.8, pp.1091-1098, August 1999; - the supply voltage Vdd to extract the threshold voltage value VTvierge from a blank cell.

 To this end, two voltage variation ranges are provided, each corresponding to a respective measurement window, namely: - one which covers the voltage specification window VTvierge, and - one which covers the voltage specification window VTeff.

 The above-mentioned ranges are represented in FIG. 10, which represents the evolution of the drain current ID (on the ordinate) of an FGT transistor against the

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 voltage applied to its control grid Vcg (on the abscissa). It is noted that, both for the voltage VTgegeque and for the voltage VTeff, the measurement range sufficiently exceeds the limits of the tolerance range provided for by the specification, in order to allow cells clearly outside of the latter to be analyzed.

 The evolution of the voltage Vcg over the measurement ranges is obtained by programming successive incremental values of Vcg by means of the programmable voltage generator 44, the output 56 of the latter being routed to the control gate of the cell's FGT transistor. to analyze. It is thus possible to extract precisely the blank threshold voltages VTvierge and erasure VTeff for a constant value of the reading current Ilect. : These voltages correspond to the voltage Vcg at which the drain current ID is equal to the read current Ilect, fixed by the read amplifier.

 For the two measurement windows, the respective threshold voltage value Virgo and VTeff is given by the value of the gate control voltage Vcg when the sense amplifier 12 switches.

 The process of extracting the value of VTvierge or VTeff for checking a given cell 16 is carried out by the following steps: li) selecting the individual cell to be checked, by addressing on its BL lines and corresponding WL; if cells are to be read in parallel, each will be associated with its respective amplifier l.ii) set the reading current of the reading amplifier 12 to a nominal value Ilect.

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l.iii) fill the shift register 66 (FIG. 9) with logic values 0. In this way, each of the M outputs EPV1 to EPVM is initially at state 0. These outputs, each connected to the two control gates of the transistors 62 and 64 of their respective switch 54-1 to 54-M, block these (keep them open) by their logic value 0. No output 50-1 to 50-M of voltage generator 48-1 to 48-M is therefore not present at the common output 56 which produces the voltage Vcg; l.iv) switch, via the routing circuits, the common output 56 of the voltage generator to the gate CG of the transistor FGT of the cell 16 considered
1.v) introduce a logic bit 1 in the first stage EV1 of the shift register 66, via the input EVser. This bit positions the corresponding parallel output EPV1 of this stage in logic state 1.

This output EPV1, which is connected to the gates of the transistors 62 and 64 of the switch 54-1, makes the latter passing through its logic state 1. The output of the voltage 1. VREF of the generator 48-1 then passes to the common output 56 The other switches remain blocked; l.vi) determining whether the output of the sense amplifier 12 switches from logic state 1 to logic state 0; l.vii) if there is no logic state changeover observed in step l.vi), shift the logic bit 1 to the next stage EV2 and return the stage EV1 to the state 0 (by entering a bit 0 at the register entry before the shift). In this way, and in a similar manner, it is switch 54-2 which becomes the only passing switch; it transmits the voltage 2.VREF from its generator 50-2 to the common output 56;

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 l.viii) determine whether the output of the sense amplifier 12 switches logic state 0 to logic state 1.

 As long as there is no logical state switching, steps l.vii) and l.viii) are repeated in a loop, these taking the more general form, starting with step l.viii ) from: l.viii ') shift logic bit 1 to the next stage EVk + 1, bring the stage EVk back to state 0, so that the switch 54-k + l becomes the only passing switch and produce the voltage (k + 1). VREF on common output 56, where k takes successive values from 1, and return to step l.vi 'l.vii') determine if the output of the sense amplifier 12 switches from logic state 1 in logic state 0: if there is no switching, increment k by one unit, and return to step l.viii '); - if there is a changeover, identify the value k and output its digital value in binary form.

 Advantageously, this binary form is obtained directly from the output SVser of the shift register 66, for example by analyzing its content: the position of bit 1 directly indicates the corresponding coefficient k in the relation VTvierge - k. VREF or VTeff k.VREF (of course, the values of k will be specific to each evaluated threshold voltage). It can also be obtained by counting down, from the time of switching, the number p of offsets necessary for bit 1 to appear at this output, the coefficient of VREF in this case being (M-p). Other approaches are of course possible.

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 The output of SVser from the shift register 66 can be directed to a terminal of the memory 110 accessible in test mode, according to known techniques.

 This threshold voltage value extraction process is applied for the blank cell (giving VTvierge) and for this same cell in the programmed erasure state (giving VTeff).

 Thus, a digital datum is obtained at the output of the memory 110 which indicates each of the threshold voltages VTvierge and VTeff in terms of the respective coefficient of the elementary incremental value VREF.

 This process is repeated for each cell to be checked.

FIG. 11 illustrates the principle of the use of the shift register 66 according to the process just described, in the case of the determination of the threshold voltage VTvierge for a given cell subjected to a test. This figure reproduces the left curve of Figure 10, on the same axes. It also indicates, by vertical projection lines on the abscissa, the input voltage values Vcg applied to the transistor FGT. These are successively from VREF, 2.VREF, 3.VREF until reaching 7.VREF. At this value Vcg = 7.VREF, the value of the current ID passing through the transistor FGT exceeds the reading current Ilect used. (More precisely, the condition ID> Ilect takes place for a voltage value 6. VREF <Vcg # 7. VREF. The process then ceases to increase the voltage Vcg and outputs the current value of the shift register 66 in the form of the binary word
0000 0010 0000 0000. This value, presented at a point in the memory, is loaded directly into a register of a test or measurement device. This is programmed to interpret this binary word as coding the value 7, which is interpreted as the

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 coefficient of the reference voltage VREF, the value of which is also stored in the device.

The values of the binary words stored in the shift register 66 are indicated under the abscissa for each value applied for the voltage Vcg, going from VREF to 7.VREF
As regards the writing threshold voltage VTinscr, the first embodiment determines it indirectly, by changing the reading current Ilect, and therefore the current ID flowing through the cell. Indeed, the value of VTinscr cannot be extracted directly, because it is negative, and that a negative voltage cannot normally be applied to the control gate.

 The process for determining the value of VTinscr is analogous to that for determining the values of VTvierge and VTeff 'except that the stepwise variation takes place this time on the reading current Ilect, the voltage Vcg being kept fixed.

 The principle of this approach for the measurement of VTinscr is illustrated by the curve of FIG. 12, which shows the evolution of the current ID of an FGT transistor analyzed, using the same axes as for FIG. 10.

 Only, in this case, a current measurement window is defined on the current specification window ID and a current measurement window ID, the latter extending beyond the specification window for this current, at both ends, to allow analyze faulty conditions, like the measurement window for the programmable voltage of Vcg.

 During the measurements made, the control gate of the floating gate transistor FGT is grounded, and the reading current Ilect is increased by

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successive steps of IREF in the measurement window, until the sense amplifier 12 switches and produces the image, in the form of current, of the threshold voltage. This switching point corresponds to the point where the storage transistor FGT can no longer allow the current value ID imposed on it by the sense amplifier to pass, otherwise known as the current Ilect
To this end, the programmable current generator 20 (FIG. 5) is used, controlled using the shift register 42 (FIG. 9).

The steps in the process of extracting the value of VTinscr for a given cell 16 is carried out by the following steps:
2.i) select the individual cell to be checked, by addressing on its corresponding BL and WL lines,
2.ii) grounding of the gate of the floating gate transistor FGT (ie Vcg = OV);
2. iii) fill the shift register 42 (FIG. 9) with logic values 1. In this way, each of the N outputs EPI1 to EPIM is initially in state 1. These outputs, connected to the control gates of the transistor 32 of switching stages 26-1 to 26N respectively, block these (keep them open) by their logic value 1 (in the case of PMOS transistors). No current is then present on the Ilect current output 34 at this stage;
2.iv) switch, via the routing circuits, the output 54 of the programmable current generator to the cell 16 considered;
2.v) introduce a first logic bit 0 in the first stage ED1 of the shift register 42, via the input EVser. This bit positions the corresponding parallel output EPI1 of this stage in logic state 0.

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This output EPI1, which is connected to the gate of the switching transistor 32 of stage 26-1 of the programmable current generator 20, makes this transistor passing through its logic state 0. Stage 26-1 can thus transmit a current from IREF to output 34 of Ilect, which is the only current contribution, the switching transistors 32 of the other stages remaining blocked;
2. vi) determining whether the output of the sense amplifier 12 switches from logic state 0 to logic state 1 (corresponding to the write state);
2. vii) if there is no logic state switchover noted in step 2. v), introduce a new bit 0 at the EIser input of the shift register, perform an shift cycle so that bit 0 of stage ED1 passes to stage ED2, and that the new bit 0 passes to stage ED1. In this way, the switching transistor 32 of stage 26-2 of the programmable current generator also becomes on, and contributes a current of IREF on output 34 of Ilect, in addition to that of stage 26-1. The total current on this output then goes to 2.IREF;
2. viii) determine whether the output of the sense amplifier 12 switches logic state 0 to logic state 1.

As long as there is no logical state switching, steps vii) and viii) are repeated in a loop, these taking the more general form of (starting with step 2.viii):
2.viii ') add a new bit 0 to the input EIser of the shift register 42, carry out an shift cycle, so that the r first stages ED1 to EDr of the register are in state 0 and therefore that the r first stages 26-1 to 26-r each contribute a current of IREF, bringing a total current of (r). IREF at

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the output 34 of Ilect, where r is an incremental integer starting with 2 (the case of r = l being already covered by steps 2. vi) and 2. vii) above);
2.vii ') determine whether the output of the sense amplifier 12 switches from logic state 0 to logic state 1: - if there is no switching, increment r by one, and return to step 2.viii '); - if there is a changeover, identify the value of r and output its digital value in binary form.

The value of Ilect produced at the output 34 of the programmable current generator 20 is obtained directly from the value of the binary pattern contained in the shift register 42. In this case, the total number of bits 1 in the register corresponds to the r value of the coefficient r.IREF-
As for the extraction of the threshold voltages VTvierge and VTeff. the bit pattern of the shift register 42 is transmitted to a test or measurement device by routing the SserI output of the register to a connection point of this device and by discharging its contents. The device contains in memory the value of IREF and can therefore determine the value of the reading current by the relation: Ilect = r. IREF. This value indicates that the sense amplifier has switched logic state for a read current (r - 1). IREF <Ilect # r.

IREF 'The threshold current ID is assimilated to this value of Ilect at which the tilting occurs.

 This process is repeated for each cell to be checked.

 FIG. 13 shows an example of a curve obtained for successive read current values Ilect from IREF to 11. IREF, the switching of the logic state of the read amplifier 12 having been detected on

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 continuation of the application of the current of 11.IREF by the programmable current generator.

 FIG. 14 is a block diagram showing the parts of the EEPROM memory 110 which are involved in the extraction of the threshold voltage values VT and the interface of the memory with a test or diagnostic apparatus 200 used to collect these values.

 There are: - the programmable voltage generator 18 controlled by the outputs EPV1..EPVM of the shift register 66, the output 56 of the generator being transmitted to the control grid CG of a cell 16 according to the routing established by the circuits memory routing, and - the programmable current generator 20 controlled by the outputs EPI1..EPIN of the shift register 42, the output 34 of the generator being transmitted as Ilect read current. of the sense amplifier 12, the cell under test being selected by the memory routing circuits.

 The operation of the voltage and current generators and of the loops which controls the evolution of their output values is controlled by a state machine 112 of a PLA unit of the control logic 4.

 The respective outputs SIser and SVser of the two shift registers 42 and 66 are routed to a connection point 114 which can be connected to a suitable digital input 210 of the test / diagnostic apparatus 200. This connection point can be an internal pad , accessible in test mode, or an external pin of a box in which the memory is housed. In the example, its outputs SIser and SVser are presented upstream to two respective inputs of a multiplexer 116, the output of which selectively connects one or the other of these two inputs to the connection point 114.

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This multiplexer 114 is controlled by the state machine 112 according to the threshold voltage to be determined.

 The interface between the connection point 114 of the memory 110 and the digital input of the test / diagnostic apparatus 200 can be carried out by a digital link cable LS, for example of the serial type.

 The test / diagnostic apparatus 200 stores in memory 220 the values of IREF and VREF, as well as decoding data of the digital outputs produced on its input 210, to obtain the value of threshold voltage or current in an intelligible form. from the digital data on input 210.

 A second embodiment of the invention will now be described which differs from the first essentially by the fact that the extraction of the threshold voltage VTvierge for a blank cell and the threshold voltage VTeff (or their equivalent form in terms of current threshold) for an erased cell is obtained by means of the programmable current generator 20 in association with the shift register 42. This solution is advantageous insofar as it makes it possible to dispense with additional circuit elements to be provided for the programmable voltage generator 44 and its shift register 66.

 The corresponding architecture of an EEPROM memory 120 based on this second embodiment is shown in FIG. 15. For the sake of brevity, only the differences of this architecture compared to that of the first embodiment presented in FIG. 5 will be specified: - absence of the programmable voltage generator 18, - absence of the routing circuits of the variable voltage Vlect, and - presence of the routing circuits of the voltage Vboost integrated in the decoder line 6, (and not

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 in the high-voltage generator 14), these circuits being used moreover for reading the voltage of an erased cell 16.

 In the second embodiment, the threshold voltage VTinscr in read mode is extracted in an identical manner, and with the same means, as for the first embodiment. The description already made on this aspect therefore implicitly applies to the description of this second embodiment, and will not be repeated for the sake of brevity.

 It is recalled, however, that a threshold current is defined as the image of the threshold voltage to which it corresponds.

 To help understand the link between the threshold current and the threshold voltage, FIG. 16 represents a curve similar to that of FIG. 4, but taking the case of a fixed polarization of the drain of the transistor FGT, this polarization being given by the context of the product in which it is integrated. Compared to the curve of FIG. 4, the shapes remain substantially identical, the threshold voltage VT indicated in FIG. 4 becoming in FIG. 16 the voltage of Vlect, and the reading current becoming the threshold current ID. We then note that the context is given by: - for a single isolated cell 16, by the curve of the drain current ID as a function of the voltage applied to the control gate of the FGT transistor, - for the same cell integrated in its product , by the output of the reading amplifier 12, with the current applied to the drain for a given value of reading voltage Vlect at the control gate.

 It is also noted, with regard to the definition of the threshold current IT that:

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 - when the current ID is below the threshold current IT for a given reading voltage Vlect on the control gate CG of the transistor FGT, the cell 16 is no longer able to conduct the current ID, and the output of the sense amplifier 12 is in the high state; when the current ID is greater than the threshold current IT for a given reading voltage Vlect applied to the control gate CG, the cell 16 lets all the current ID pass, and the output of the reading amplifier 12 is at low state.

 It follows that the threshold current ID is given by the current applied to the drain of cell 16 at the time when the read amplifier switches, and this for a given read voltage Vlect applied to the control gate CG.

 By definition, the threshold current provides information on the characteristics of the cell which is equivalent to that provided by the threshold voltages. Thus, the threshold current can be used in an equivalent manner to the threshold voltages VT. This notion is exploited by the second embodiment for all of the blank, deleted or written cell thresholds; it is also used in the first embodiment with regard to the threshold of a written cell. The equivalence between a threshold voltage VT and the threshold current IT for the same cell state is managed in particular by the test / diagnostic apparatus 200.

 When the product integrating the EEPROM memory 120 is in its normal operating state, in accordance with the second embodiment, the following is extracted: - the current IT virgin from a blank cell, - the current IT eff from a deleted cell, and - the current ITinscr of a written cell.

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 To perform these extractions, the reading process is transformed into a reading test process, with a constant reading voltage Vlect and a variable drain current, as illustrated in Figure 17. This figure expresses, in the form of current curves drain ID against the voltage Vcg, the possible transformation of a threshold voltage into a threshold current. The example illustrated is applied to the voltage and current thresholds VTeff / ITeff for an erased cell 16; of course, it is applicable mutatis mutandis to similar thresholds for a blank or written cell. As in the case of FIG. 10, FIG. 17 also presents the ranges or windows for specification and measurement, the latter covering the former for the same reasons. These ranges are expressed in terms of voltage, as in the case of FIG. 10, and in addition they are converted into ranges in terms of threshold current IT, joining the concept applied for the first embodiment in the case of a written cell (see Figure 12).

 The transformations implemented in this context include: - the range of specification of the threshold voltage VT, which becomes a range of specification of threshold current IT, and - the range of measurement of the threshold voltage VT relative to the range of threshold voltage specification, which becomes the threshold current measurement range IT relative to the threshold current specification range.

 The extraction of the threshold current IT is generally carried out under the following conditions: the control gate is positioned at a constant reading value Vlect,

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 - the reading current is increased step by step over the measuring range, until the reading amplifier 12 switches and produces a threshold current.

 To do this, the programmable current generator 20 and the shift register 42 are used, and the same steps (2.i) to 2.viii ')) are carried out as described in the context of the first embodiment, with the adaptations that are necessary depending on whether the thresholds for a blank, erased or written cell are extracted.

 Thus, it will be understood that according to the threshold voltage to be extracted, the potential Vcg of the control gate CG of the transistor FGT will be fixed at different voltage values: - in the case of obtaining the threshold current ITlect of a cell written, we put this control grid CG to ground, - in the case of obtaining the ITvierge threshold current of a blank cell, we put this control grid CG to a positive potential, designated VBOST1, delivered by the routing circuit 22, - in the case of obtaining the threshold current ITeff of an erased cell, this control gate CG is set to a positive potential, designated VBOOST2, higher BOOST1.

 The threshold current conversion (generically designated IT) => threshold voltage (generically designated VT) can be carried out either: internally from the memory, by stored conversion tables, based on the curves as presented in FIG. 17, - either carried out at the level of the test or diagnostic apparatus 200, this comprising the necessary conversion tables in its memory 220.

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 FIG. 18 is a block diagram showing the parts of the EEPROM memory 120 according to the second embodiment which are involved in the extraction of the threshold voltage values VT and the interface of the memory with a test or diagnostic apparatus 200 used to collect these values.

 This figure is similar to FIG. 14 for the case of the first embodiment, and only the differences will be described for the sake of brevity, the common parts having the same references and having the same roles.

 Note that the absence in the second mode of the programmable voltage source and its shift register makes it possible to connect the output SIser of the shift register 42 directly to the connection point 124 (analogous to that 114 in FIG. 14) , without multiplexing.

 The test / diagnostic apparatus 200 is identical to that of FIG. 14, except that its memory 220 does not have to store the value of VREF, nor of decoding data of the digital input specific to the extraction of the thresholds in the form of voltage, all the thresholds will first be considered in the form of threshold currents, then, if necessary, converted into threshold voltages using the aforementioned tables, according to the equivalence principles described.

 In the practical implementation of the extraction of the three threshold voltages Vierge'VTeff and VTinscr, either directly or by means of a threshold current measurement, the two embodiments retain the following constraints: - the additional , in terms of chip area, linked to the extraction of the threshold voltage VT or to the threshold current IT must be relatively small,

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 - the excess, in terms of test duration, linked to the extraction of the threshold voltage VT or of the threshold current IT must be limited as much as possible, - the specification or specifications of the operation of the memory in normal mode must be maintained, and - the value of the threshold voltage VT or of the threshold current IT must be supplied to the memory test means in a compatible digital format or easily observable using random logic in the case of a buried EEPROM (embedded EEPROM in English terminology).

 In order to validate the extraction of the threshold voltages, according to the first or the second embodiment, the applicant carried out electrical simulations, by means of the ELDO tool, on an EEPROM memory with a design rule of 0.25m, produced by STMicroelectronics, with Vdd = 3.3V. For more information on the ELDO tool, one can refer to the documentation "ELDO User's Manual", from the company Mentor Graphics Corp. 1998.

 The elements taken into account in the simulation, integrated into a so-called "netlist", include: - a memory map in 4X4 format with 4-bit words, - the line decoder and the row (word) decoder, - the read amplifiers for each bit, - storage flip-flops ("latches" in English terminology), and - the structure for extracting threshold voltages.

 The simulation model of the floating gate transistor FGT is based on a MM9 type kernel, and it is described in HDLA language. For more information on the MM9 kernel, we can refer to

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 the article by J.M. Portal et al. "An automated methodology to diagnose geometric defects in the EEPROM Cell", Proc. IEEE International Test Conférence (ITC), pp.31-36, October 2002.

 FIGS. 19 to 22 show timing diagrams of signals, in the form of inputs on a monitor, of a capture window during the simulation, each on a time scale represented on the abscissa, during different operations intervening on the EEPROM memory 110 or 120.

 FIG. 19 represents the evolution of the programming voltage, designated Vpp, applied to a blank cell of the memory successively to program therein an erased state and a written state, and then pass to a reading phase. In known manner, this voltage is produced by the high voltage generator 14 and is applied to different points of the cell according to whether it programs an erasing or writing state.

 The programming of the two states first goes through a ramp of the voltage Vpp, followed by a plateau.

The variations in this voltage, up and down, are managed by internal timing circuits.

 FIG. 20 represents the evolution of the threshold voltage VT (represented on the ordinate) of a blank cell, on the same time scale as for FIG. 19, and for the same cell, thus making it possible to visualize this threshold voltage successively when erasing, writing and reading.

 The flat part of the left of the curve corresponds to the virgin initial state of the cell, located at a little more than 1 volt. In the erased state, the voltage VT gradually rises to a level between 2 and 3 volts. During the erasure phase, the voltage VT

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 remains stable on an upper shelf, before rapidly falling to a negative value during the writing phase.

 It is noted that there is a latency between the control of a state by the high voltage and the positioning of the threshold voltage VT at the corresponding value, this latency being substantially equal to the duration of the plates.

 FIG. 21 represents the evolution of the current ID flowing through a cell, showing the incremental steps produced by the source of this current in response to the corresponding increments of the reading current produced by the programmable current generator 20 during the search for the threshold current IT of this cell. When the current ID forced to pass through the cell can no longer increase, reaching the limit of the storage transistor FGT for the gate polarization Vcg which is fixed to it, there is a change of logic state at the level of the sense amplifier . We observe the presence of initial current peaks, typical of cell erasure phases.

 FIG. 22 represents the evolution of the logic output (on the ordinate) at the level of the output voltage of the sense amplifier, on the same time scale as for FIG. 21, and for the same cell, thus making it possible to visualize the tipping points relative to the current ID of figure 21.

There is an initial logic state 1, ending after a second of the aforementioned peaks by switching to logic state 0. This logic state remains until the current ID and the reading current Ilect coincide, the amplifier of reading then switches to logical state 1.

 In summary, the additional, chip surface implied by the voltage extraction structure or

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 threshold current is relatively low given the memory area. Indeed, the extraction structure is mainly composed of: - a configurable shift register (allowing a mode for writing extraction and another mode for extraction on blank cell and erasing), a multiple current source programmable (using two PMOS transistors per source), - (in the case of the first embodiment only) a programmable multiple voltage source (using four MOS transistors per reference voltage), and - a modified control logic for the test mode .

 The increase in time also remains low. The reading operation time in test mode increases to occupy 0.5% of the programming operation time. Furthermore, the normal operating mode of the memory is maintained.

 The values of the threshold voltages VT are supplied in a digital format, so that the extraction process does not require an analog terminal at the level of the test means. The component thus remains compatible with the entirely digital test means, or easily observable via random logic in the case of a nested EEPROM memory.

 A diagnostic methodology will now be described making it possible to judiciously exploit the information extracted concerning the threshold voltages and / or currents of a set of cells of a memory plane.

 A classic approach for the diagnosis and debugging of a memory consists in carrying out a digital "bitmap" mapping of the memory plane. This cartography is built during

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 functional tests to verify, at the topology level, the state of each cell. From the overview provided by this mapping, the significant signatures are cataloged: isolated bit, column, line, partial column, etc., to help determine the cause underlying a failure (cf. article by Segal et al cited above).

 However, it may be that several failure mechanisms appear with the same signature. In order to minimize this limiting factor, one solution would be to extract other significant electrical parameters.

 This solution is particularly relevant when the diagnostic method targets analog cells, such as EEPROM memory cells.

The most informative electrical parameter in the case of an EEPROM cell is the threshold voltage value VT or its threshold current IT.

 In view of these considerations, it is proposed to produce, during functional tests, an "analog" bit mapping. In the case of an EEPROM memory cell, the analog bit mapping comprises three representations in bit mapping: - one for the threshold voltage VTvierge or the threshold current ITvierge of a blank cell, - one for the threshold voltage VTeff or the threshold current ITeff of an erased cell, and - one for the threshold voltage VTinscr or the threshold current ITinscr of a written cell.

 Each of the monitored cells is individually identified in its memory plan (2), for example by its address.

 The resulting analog bit maps can be used in the same way as a

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 digital bit mapping, with signature classifications based on VT or IT threshold voltage values.

 These classification signatures are potentially very useful for characterizing a process and for evaluating its impact on a memory plane.

 To carry out such analog bit mapping, the data from the above-mentioned shift register is converted. The conversion of the value of the register into an analog value of threshold of tension is simple for the cells, being coded by the pattern of bits in the shift register 42 or 66 at the time of the state switching of the sense amplifier, as described above.

 FIGS. 23a, 23b and 23c schematically represent an analog bit map obtained for the simulation of the 4X4 memory plane with 4-bit words, defined above, respectively for a plane of cells in the blank state, in the written state, and in the erased state.

The values express, for these three states, the extracted threshold currents (A), in accordance with the second embodiment. (In the figures, only the four values for the first row are written; it will of course be understood that each cell will have its own value assigned in practice.)
In the case of the first embodiment, there would be threshold voltage values for the blank and erased cells, and threshold current values for the cells written in place of the current values.

 Note that the values thus listed in FIGS. 23a-23c are organized according to a topography like that of the cells 16 of the memory plane 2 that they represent. These analog values

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 thus constitute an analog bit mapping giving precious information on the analog threshold values of each of the cells individually considered.

 As a variant, the measurements and / or the mapping may be carried out only on / for certain cells of the plan, in order to obtain a representative sample; this variant makes it possible to reduce the control time and the resources in storage analysis of the results.

 In the plans, half of the cells are designed with the target geometry of the technology, while for the other half they are dimensioned randomly with geometric parameters which show a variation of between 5% and 50% of the target.

 In the present example, the digital bit mapping does not show any defective bits.

However, analog bit mapping reveals the existence of cells for which at least one of their threshold voltages / currents is out of specification, and also makes it possible to locate these cells. From these failures at the threshold currents / voltages, it is possible to implement specific diagnostic tools which can be used to identify the causes of origin of the defective geometric parameters. For more information on this aspect, one can refer to the article by J.M. Portal et al. "An automated methodology to diagnose geometric defects in EEPROM Cells", Proc. IEEE International Test Conference (ITC), pp.31-36, October 2002.

 In addition, like a digital bit mapping, the signatures are cataloged (cell write, cell erase, blank cell, write

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 column, etc. ), also to help determine the basic mechanism involved.

 To complete the diagnosis, we can generate the distribution of threshold voltages / currents for the evaluated memory plane, so as to estimate the correlation of its values with the specifications for the threshold voltages.

 FIGS. 24a, 24b and 24c constitute examples of distributions applied to the aforementioned memory, for a plan of 64 elements respectively written, blank and erased.

 These distributions are represented here in the form of histograms. Each histogram is made up of columns, each corresponding to a threshold current value (of blank cell, erased or written, depending on the histogram); the height of each column indicates on a scale the percentage of cells checked having the corresponding threshold current value.

 The distributions give information concerning the control of the manufacturing processes and the distribution of the defects on the whole of the memory plan.

 The data making it possible to constitute the analog bit maps, for example as presented in FIGS. 23a to 23c and / or statistical distributions for example as presented in FIGS. 24a to 24c, can be stored in a suitable electronic medium, possibly with data. other related data (manufacturing batches, measurement conditions, other test results, traceability information, etc. This support can be integrated into the control device 200 or outside it.

 From the above, it will be understood that the non-volatile memories, based on analog cells,

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 leads to critical manufacturing and design process control problems. The structure integrated into the component, according to the embodiment, makes it possible to extract the analog signatures of each cell of the memory plane, that is to say the different threshold voltages in the case considered. This structure makes it possible to extract the threshold voltages during functional tests with little overload in terms of both space on chip and test time.

 What is more, the threshold voltages are advantageously extracted in digital form, which allows: compatibility with entirely digital test means, - a simplification of the observation of these values through the logic kernel in the case of a Nested EEPROM.

 From the extraction of the threshold voltages, a diagnostic methodology was developed based on analog bit mapping, which can be used in concert with conventional digital bit mapping. This results in a more efficient analysis of the analog behavior of each cell in the memory plane. This diagnostic methodology also makes it possible to obtain the distribution of the threshold voltages over the entire memory plane, which may be useful for the qualification of the manufacturing control process.

The control in accordance with the present invention can be carried out in the context of several types of intervention where it is advantageous to acquire values of analog parameters, in particular at the level of the memory test. The control can take place, for example:
1. By systematic acquisitions on all the plates of a batch of memories, or by

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 sampling on some of them, so as to produce at least one history relating to the centering of the memory manufacturing process, in particular for the different states of the cells. blank, erased, written. We can register the follow-ups thus obtained by a statistical process control (also known by the acronym SPC, from "statistical process control), and therefore obtain information on possible drifts and dispersion of parameters.

This information can provide links between the analog values extracted and the values measured during the steps of the process.

 2. By data acquisition on faulty cells, as part of a diagnosis.

The analog bit mapping described above allows in this case an analysis of the bits (cells) in error from the analog electrical signatures, these being listed in a signature library.

 3. By acquiring data on cells at the periphery of the defective cells or, more generally, of at least one determined cell, so as to establish whether the cells as a whole are healthy or different, or if on the contrary they are potentially failed. This approach consisting in studying systems in the vicinity of a system (a cell in this case) is generally designated by the term "reliability coverage".

 These checks 1, 2 or 3 can be carried out by the device 200 of Figures 14 or 18, or by any other suitable device.

 Many other embodiments and variants can be envisaged in the context of the invention, both in terms of control processes

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 than hardware and software for their implementation.

 For example, the control can be carried out as well on all the cells of a memory as on some of them, these serving as samples and being able to be distributed on the whole of the memory plane 2 to offer good representativeness of the characteristics.

 Furthermore, the memory 110 or 120 can be both in the form of memory alone and in integrated form with other circuits, for example in the case of a microcontroller, etc.

 Although the description and the embodiments relate to memories, in this case non-volatile memories of the EEPROM type, the field of application is much wider, extending to any system using an analog parameter. serving as a reference for quantifying an output value, and the number of levels to be identified can be greater than two, such as analog-digital or digital-analog converters, or charge transfer devices (known by the CCD acronym of charge-coupled device).

Claims (47)

1. Method for controlling a system (16), this system being intended to present a quantity to be identified with one of a finite number of pre-established levels, the identification being conditioned by at least one intrinsic analog parameter (VT ; IT) of the system, characterized in that it comprises a determination of the value of said intrinsic analog parameter (VT, IT).  2. Method according to claim 1, characterized in that said value of said intrinsic analog parameter (VT, IT) is determined internally by a device (100; 110; in which the system (16) is integrated and is presented at output of this device for external control.  3. Method according to claim 2, characterized in that said value of said intrinsic analog parameter (VT, IT) is presented at the output of the device (100; 110; in digital form.  4. Method according to any one of claims 1 to 3, wherein said or each intrinsic analog parameter (VT, IT) conditions a threshold by which a predetermined level is identified under determined operating conditions, characterized in that it comprises the stages of: <Desc / Clms Page number 57>  - position the system under operating conditions at which said quantity is located at a determined side of said threshold, change the operating conditions of the system in the direction bringing said quantity (Vcg, ID) towards the threshold, - when said quantity reaches or crosses the threshold, determine the value of an identifiable parameter or linked to said intrinsic analog parameter (VT, IT).  5. Method according to any one of claims 1 to 4, implemented in a device comprising a set of systems (16) individually identifiable, characterized in that said determination of the value of said parameter (VT, IT) is carried out individually for each system subject to control.  6. Method according to claim 5, characterized in that the value of said determined parameter (VT, IT) is listed with an identification of the individual system from which it was determined, for example in the form of cartography.  7. Method according to any one of claims 1 to 6, characterized in that said system is a cell (16) of a non-volatile memory (1, 110; 120), the method being carried out on at least one cell of said memory.  8. Method according to claim 7, characterized in that the memory is a memory of the electrically erasable programmable type, known by the acronym EEPROM (from the English electrically erasable programmable read only memory). <Desc / Clms Page number 58>  9. Method according to claim 7 or 8, characterized in that said intrinsic analog parameter (VT; IT) is the threshold value of a cell (16) of the memory, for a written cell, blank or erased, and in what said quantity is the current (ID) passing through the cell or the bias voltage (Vcg) of a storage transistor (FGT) in read mode.  10. Method according to claim 9, characterized in that the threshold value (VT) is assimilated to the value of the bias voltage (VCG) of a storage transistor (FGT) of the cell (16) in read mode , to which this storage transistor passes a determined current (Il).  11. Method according to claim 9, characterized in that the threshold value ((IT) is assimilated to the value of the current (ID) passed by a storage transistor (FGT) of the cell (16) in read mode when this transistor is biased at a voltage (Vcg) positioned at a reference value.  12. Method according to claim 10 or 11, characterized in that: to determine the threshold of a blank or erased cell (16), the bias voltage (Vcg) of the storage transistor (FGT) at which this transistor is determined conducts a current (ID), the value of which crosses a substantially fixed threshold (Il ,,,), to determine the threshold of a written cell (16), the limit value of the current (ID) that the transistor can conduct is determined storage (FGT) for <Desc / Clms Page number 59>  a substantially fixed bias voltage (Vcg) thereof.  13. Method according to claim 12, characterized in that said threshold corresponds to a threshold of the storage transistor (FGT), which is determined by the logic state switching condition of a sense amplifier (12) at which said cell (16) is functionally connected and in that: to determine the threshold (VTvierge or VTeff) of a blank or erased cell (16), a reading current (Ilect) of the reading amplifier is maintained substantially constant and on changes the bias voltage (Vcg) of the transistor (FGT) so as to approximate the current (ID) passed through it to this reading current (Ilect), until causing a logic state switching of the read amplifier, and the value of this bias voltage at which the read amplifier (12) switches from logic state is determined, this bias voltage being assimilated to the threshold voltage of the blank or erased cell (VTvierge or VTeff); and - to determine the threshold (VTinscr) of a written cell, the bias voltage (Vcg) of the transistor (FGT) is kept substantially constant and said current (ID) flowing through the cell is changed until the state changes logic of the sense amplifier (12), the tipping point corresponding to the crossing of the current limit value that the cell can conduct for said transistor bias voltage (FGT), this current limit value passing through the cell being assimilated on the dance floor) of the written cell. <Desc / Clms Page number 60>  14. Method according to claim 11, characterized in that, to determine the threshold of a cell (16), whatever its state: blank, erased, or written, the value of the current (ID) passed through the storage transistor (FGT) for a substantially fixed bias voltage (Vcg) thereof.  15. The method of claim 14, characterized in that the switching threshold of the storage transistor (FGT) is determined by the condition of switching of logic state of a sense amplifier (12) to which said cell (16) is functionally connected, and in that: to determine the threshold of a cell (16) whether it is its state: blank, erased, or written, the bias voltage (Vcg) of the transistor (FGT) is kept substantially constant and said current (ID) flowing through the cell is changed until the logic state of the sense amplifier (12) changes, the tipping point corresponding to the crossing of the limit value of said current which the cell can conduct for said voltage bias of the transistor (FGT), this current limit value passing through the cell being assimilated to the threshold (ITinscr) of the cell.  16. Method according to any one of claims 9 to 15, characterized in that one changes the bias voltage (VCG) applied to the storage transistor (FGT) of the cell (16) and / or the current of reference (Ilect) on a variation range which covers the range of values accepted by the memory specification for the threshold voltage (VT) and / or the threshold current (IT) considered. <Desc / Clms Page number 61>  17. Method according to any one of claims 9 to 16, characterized in that the bias voltage (VCG) applied to the storage transistor (FGT) of the cell (16) and / or the current ( ID) traversing the cell (16) incrementally by means of a programmable voltage source (18) and / or a programmable current source (20) respectively, the or each source being controlled digitally by programming means (66 , 42), the latter being also used to provide an output to the outside (114; 124), in digital form, an expression of the value of the threshold considered (VT, IT), the values of the bias voltage ( Vcg) or of said current (ID) flowing through the cell giving the voltage or the current causing said change of logic state of the sense amplifier to the nearest increment.  18. The method of claim 17, characterized in that the programming means comprise a shift register (66,42) whose parallel outputs (EPV1-EPVM, EPI1-EPIN) are used to control their respective parts of the current source (18) and / or the voltage source (20), so as to produce a range of evolving reference current values (Ilect) and / or a range of applied bias voltage (VCG) values to a storage transistor (FGT) of the cell (16), as a function of the bit pattern loaded in the register, during the evolution of the values produced, this pattern controlling a current or voltage value, and in that this bit pattern is extracted, when that bit sets the current value or the voltage value causing a threshold to be crossed <Desc / Clms Page number 62>  in reading (12), as information on the programmed current or voltage value.  19. The method of claim 18, characterized in that said bit pattern controls coefficients of an elementary value (IREF, VREF) of current or voltage produced by internal circuits of the memory used in normal operating mode of it.  20. Method according to any one of claims 9 to 19, characterized in that at least one of: the programmable voltage generator (18), in particular a reference voltage source (VREF) thereof, the generator programmable current (20), in particular a reference current source (IREF) thereof, - the programming means (42, 66), is produced with circuit elements used by the memory (100; 110; 120) in normal operating mode.  21. Method according to any one of claims 7 to 20, characterized in that it is carried out with means embedded in said memory (1; 110; 120).  22. Method according to any one of claims 9 to 21, characterized in that it is managed, at least in part, by a memory state machine (100; 110; 120). <Desc / Clms Page number 63>  23. Method according to any one of claims 7 to 22, characterized in that it comprises a step of selecting an individual cell (16) from the memory, said determination of the intrinsic analog parameter value applying specifically to this cell.  24. Method according to any one of claims 1 to 23 used to control said intrinsic analog parameter (VT, IT) relating to each of a designated set of points (16) listed, each point comprising a said system, characterized in what we produce the results of the control obtained from the points in a corresponding listed form for analysis or diagnostic purposes.  25. The method of claim 24, applied to a memory (1; 110; the points listed being at least part of the set of cells (16) of the memory, the intrinsic analog parameter being a threshold value (VT IT ), the listed form of the control results in the form of a mapping of the threshold values like the mapping of the cells in their memory plane (2), thus defining an analog bit mapping usable in addition to a bit mapping classic binary.  26. The method of claim 24 or 25, characterized in that a statistical distribution is produced of the values of the intrinsic analog parameter obtained on the monitored points, for example in the form of a histogram, to perform a <Desc / Clms Page number 64>  statistical analysis of the variations of this parameter on all the points checked (16).  27. Implementation of the control method according to any one of claims 1 to 26 for the acquisition of values of said analog parameter within the framework of a test of devices integrating at least one said system (16), such as programmable memory, the control being carried out on at least some of said devices on manufacturing batches, so as to produce at least one history relating to the method of manufacturing the device, for example, in the case of a programmable memory (1; 110 ; 120), different states of at least some of the cells: blank, erased, or written, in order to obtain monitoring and manage information on possible drifts and dispersion of parameters.  28. Implementation of the control method according to any one of claims 1 to 26 for the acquisition of values of said analog parameter within the framework of a diagnosis on a faulty or under development device, such as a memory. programmable (1; 110; 120), in which at least one value of said parameter coming from a faulty system (16) is extracted for analysis, for example from an analog bit mapping.  29. Implementation of the control method according to any one of claims 1 to 26 for the acquisition of values of said analog parameter within the framework of a study of systems, for example cells (16), of a memory programmable (1; 110; 120), so as to establish whether the systems in their <Desc / Clms Page number 65>  together are healthy or, more generally, different.  30. System control device (16), this system being intended to present a quantity to be identified with one of a finite number of preset levels, the identification being conditioned by at least one intrinsic analog parameter (VT ; IT) of the system, characterized in that it comprises means for determining the value of said intrinsic analog parameter (VT, IT).  31. Device according to claim 30, characterized in that it is physically integrated with said system (16) and comprises an output (114; 124) of said value of said intrinsic analog parameter (VT, IT) for external control.  32. Device according to claim 31, characterized in that it comprises means (42,66) for presenting said value of said intrinsic analog parameter (VT; IT) at output (114; 124) in digital form.  33. Device according to any one of claims 30 to 32, associated with a system where said or each intrinsic analog parameter (VT; IT) conditions a threshold by which a preset level is identified under determined operating conditions, characterized in that that it comprises: means for positioning the system under operating conditions at which said quantity is located at a determined side of said threshold, <Desc / Clms Page number 66>  - Means (18, 20, 42, 66) for changing the operating conditions of the system in the direction bringing said quantity towards the threshold, means, active when said quantity reaches or crosses the threshold, for determining the value of an identifiable parameter or linked to said intrinsic analog parameter (VT; IT).  34. Device according to any one of claims 30 to 33, characterized in that it can be connected to a set of individually identifiable systems (16), and in that said means determining the value of said parameter (VT, IT ) operate individually on each system subject to control.  35. Device according to claim 34, characterized in that it comprises means for listing the value of said determined parameter (VT, IT) with an identification of the individual system from which it was determined, for example in the form of a map.  36. Device according to any one of claims 30 to 35, characterized in that said system is a cell of a non-volatile memory (1, 110; 120), the device being configured to perform control on at least one cell of said memory.  37. Device according to claim 36, characterized in that the memory is a memory of the electrically erasable programmable type, known by the acronym EEPROM (from the English electrically erasable programmable read only memory). <Desc / Clms Page number 67>  38. Device according to any one of claims 35 to 37, characterized in that the means (18,20, 42,66) for changing the operating conditions of the system in the direction bringing said quantity towards the threshold comprise means to change the bias voltage (VCG) applied to the storage transistor (FGT) of the cell (16) and / or the current (ID) passing through the cell (16) in an incremental manner, these means respectively comprising a voltage source programmable (18) and / or a programmable current source (20), programming means (66,42) for controlling the or each source, the latter providing an output to the outside (114; 124), in digital form , an expression of the value of the threshold considered (VT, IT).  39. Device according to claim 38, characterized in that the programming means comprise a shift register (66,42) whose parallel outputs (EPV1-EPVM, EPI1-EPIN) control by their logical state respective parts of the source current (18) and / or the voltage source (20), so as to produce a range of reference current values (Ilect) and / or a range of bias voltage values (VCG) applied to a transistor storage (FGT) of the cell (16) as a function of the bit pattern loaded in the register during the evolution of the values produced, this pattern controlling a current or voltage value, the device comprising means (114; 124 ) output of this bit pattern, when the one programs the current value or the voltage value causing a <Desc / Clms Page number 68>  crossing of reading threshold (12), as information on the programmed current or voltage value.  40. Device according to claim 39, characterized in that said bit pattern controls coefficients of an elementary value (IREF, VREF) of current or voltage produced by internal circuits of the memory used in normal operating mode of that -this.  41. Device according to any one of claims 38 to 40, characterized in that at least one of: - the programmable voltage generator (18), and in particular a reference voltage source (VREF) thereof, - the programmable current generator (20), and in particular a reference current source (IREF) thereof, - the programming means (42,66), is produced with circuit elements used by the memory (100; 110; 120) in normal operating mode.  42. Device according to any one of claims 36 to 41, characterized in that it comprises means for selecting an individual cell (16) from the memory, said determination of the intrinsic analog parameter value applying specifically to this cell.  43. Device according to any one of claims 30 to 42, programmed to carry out the <Desc / Clms Page number 69>  method according to any one of claims 1 to 26.  44. Programmable memory (1; 110; 120), characterized in that it embeds a device according to any one of claims 30 to 43.  45. Integrated circuit comprising a programmable memory, characterized in that it embeds a device according to any one of claims 30 to 44.  46. Control device (200) intended to cooperate with the device (100; 110; according to any one of claims 30 to 45, characterized in that it comprises an inlet (210) intended to functionally connect to an outlet (114; 124) of the device (100; 110; producing an expression of the value of the intrinsic analog parameter.  47. Control device according to claim 46, characterized in that said input (210) is a digital input intended to receive a bit pattern which encodes the expression of the value of the intrinsic analog parameter, and in that it comprises data storage means (220) making it possible to extract exploitable information from this encoded expression.