FR2852414A1 - Modem and multiplexer interoperability problems analyzing device, has emulating units for emulating operation of modem and multiplexer, and master card for determining whether equipment under test has interoperability defect - Google Patents

Abstract

The device has a connecting equipment (1) with several copper interfaces, and a software with an application accommodated by a control computer and an application executed on a master card (5). The operation of a modem and a multiplexer is emulated by respective emulating units as per determined x digital subscriber line (DSL) norm. The master card determines whether the equipment under test has an interoperability defect.

Description

"Device for analyzing xDSL interoperability problems"

  The present invention relates to a device making it possible to analyze the interoperability problems occurring between two xDSL access devices, particularly xDSL modems on the one hand and xDSL access multiplexers on the other hand.

  The invention relates to the field of xDSL type broadband access systems, for example SDSL (Single pair symmetric Digital Subscriber Line in English terminology). It typically finds its application when physical layer interoperability problems arise between the xDSL modem and the access multiplexer.

  A broadband access system is typically composed of - an xDSL modem located on the customer premises, - one or more copper pairs between the customer premises and the subscriber distributor, and - a subscriber multiplexer, called DSLAM or master chassis, co-located with the subscriber distributor.

  Interoperability in the context of the invention is the property that two pieces of equipment have to communicate with each other. However, most of the communications standards and of the communication assemblies implement the ISO communications model which is divided into seven layers ranging from the physical transmission network to the users. Each link therefore passes through a succession of equipment distributed over each of the seven layers of the ISO model and the dialogue is established by means of layer interfaces between a transmission side and a reception side.

  Each layer interface receives a message from the upper layer. It adds control information and transmits the new message to the next layer up to the physical layer. In addition, each layer interface of the same layer on the source machine and on the destination machine can directly exchange protocol data.

  The physical layer provides the procedures and functions making it possible to provide all of the mechanical and physical functionalities for establishing, maintaining and freeing the connections between each terminal data processing equipment such as a computer and terminal data circuit equipment such as a modem.

  However, despite the manufacturer's announcement that the xDSL physical layer conforms to the reference standard such as the standards: - ADSL G.992.1 and TS 101 388, - SDSL G.991.2 and TS 101 524, - VDSL TS 101 270, it is common to find abusive interpretations or omissions of certain points in the standard. This then gives rise to problems of interoperability between devices located in the xDSL physical layer. Interoperability problems are encountered during the introduction of additional equipment into the network, but also during the software update of equipment already placed in the network. New operating anomalies between devices can therefore appear while the devices are deployed in the network.

  This is for example the case when adding new EOC requests exchanged on the EOC operating channel and not managed by the equipment located at the other end.

  In the state of the art, it is therefore very difficult to attribute the responsibility for the non-interoperability of the modem-DSLAM subscriber multiplexer pair to the modem manufacturer or to the manufacturer of the DSLAM subscriber multiplexer. The users are required to put pressure on the two manufacturers 30 to make them work together and put an end to the dysfunction caused by the non-interoperability, which results in an extended time of non-operation of the telephone equipment.

  To overcome this drawback of the state of the art, the invention relates to an analysis device which makes it possible to analyze the physical layer of xDSL links in order to ensure the conformity of the physical layer of the equipment to the reference standard used in the xDSL communications system in which the equipment is installed.

  According to one aspect of the invention, the analysis device makes it possible to determine the cause of non-functioning of a Modem-DSLAM pair. Depending on its programming, the device of the invention can simulate a modem and will then be connected to a DSLAM subscriber multiplexer or a DSLAM subscriber multiplexer, and the device of the invention will then be connected to a modem.

  According to another aspect of the invention, the analysis device 15 comprises a means of analysis of the different stages of activation of the physical layer to detect the failures and nonconformities of an xDSL modem.

  According to another aspect of the invention, the analysis device comprises means for exploiting the xDSL connection characteristics of a plurality of xDSL chipset integrated circuit sets on the market. Thanks to the data from multiple sets of xDSL "chipset" integrated circuits and to its fine capacity for analyzing the different stages of activation of the physical layer, the analysis device of the invention allows the operator serving the analysis device of the invention to decide on the failure state on the basis of the data measured by the analysis device.

  In one embodiment, the analysis device of the invention includes means for detecting that a modem does not respect the latency times required by the xDSL standard applied for a change of state, which can prevent the activation phase to proceed properly.

  In order to ensure an accurate analysis of the physical layer of the xDSL equipment, the analysis device of the invention comprises a hardware part and a software part.

  It thus consists of a means capable of emulating the operation of a subscriber multiplexer by working in a CO mode of telephone center emulation for the establishment of the physical layer or the operation of an xDSL modem. by working in a CPE mode by emulating a modem on the subscriber side of the telephone network.

  Other characteristics and advantages of the present invention will be better understood with the aid of the description and the appended figures among which: FIG. 1 is an example of an embodiment of an analysis device of the invention; - Figure 2 is a test means belonging to the device of Figure 1; - Figure 3 is a state machine explaining the operation of the device of Figure 1; and FIG. 4 is a block diagram explaining the structure of the automaton integrated into the test device of FIG. 1.

  In Figure 1, there is shown schematically an example of an analysis device according to the invention.

  Since xDSL interoperability is also intrinsically linked to the use of the xDSL "chipset" circuit set used, the analysis device according to the invention comprises a means for emulating the CO or CPE functions for the various circuit sets " known xDSL chipset.

  Whatever the CO operation in central emulation or CPE in terminal emulation, the management of the maintenance channel called EOC is fully ensured.

  Furthermore, the analysis device of the invention integrates a TDM interface and an ATM interface in order to test the quality of the xDSL link, whether in TDM mode or in ATM mode (FIG. 2).

  To this end, the analysis device of the invention comprises means for carrying out a controlled loopback on the equipment under test. To this end, a pseudo-random sequence is injected on the TDM interface (respectively ATM). The pseudo-random sequence is then transmitted over the xDSL link. Then, it is looped on the equipment under test and is restored on the TDM interface (respectively ATM).

  In FIG. 2, a generator of pseudo-random sequences GSPA is shown, provided with an ATM link and a TDM link with an activation simulator SA connected to the equipment under test EST by the copper line 2_i.

  The hardware part of the analysis device of the invention, schematically represented in FIG. 1, includes equipment 1 integrating cards 6_1 to 6_n called "xDSL cards", each xDSL card 6_i corresponding to a determined type of circuit set a xDSL chipset required for interoperability analysis. All of these 6_i cards provide a means of exploiting the xDSL connection characteristics of a plurality of 20 xDSL chipset sets on the market. hardware 1 of the analysis device of the invention then comprises a master card 5 controlling the means for exploiting the xDSL connection characteristics of a plurality of sets of xDSL "chipset" integrated circuits on the market consisting of xDSL cards 6_1 to 6_n, a 3 TDM traffic control card and a 4 ATM traffic control card.

  The master card 5 restores the information relating to the physical layer of an xDSL card 6_i to a control computer (not shown) via a link 9, which can be of RS232, GPIB, or other type. The control computer runs a "host" application of the software part of the device of the invention.

  In operation in TDM mode, the analysis device 1 of the invention can acquire an external pseudo-random sequence via a link 7 according to a G.703 / G.704 protocol. This sequence is restored to the master card 5 by means of a processing module 3 of G.703 / G.704 protocol and a link 10.

  The master card 5 then injects the pseudo-random sequence into the xDSL card concerned 6_i via a link 12_i, said link 12_i possibly being of the serial type. The pseudo-random sequence is then integrated into the payload of the xDSL frame on the copper link 2 i. Since the operation must be symmetrical, the xDSL card 6_i recovers the pseudo-random sequence on the copper link 2_i and 10 transmits it to the master card 5 on the link 12_i.

  In operation in ATM mode, the equipment can acquire an external pseudo-random sequence via a link 8 according to an ATIV protocol of the type "1.432.3", "ATMF25.6", "STIMI", or other. This sequence is restored to the master card 5 via an ATM processing module 4 and a link 11. The operation is then identical to the operation in TDM mode.

  The synchronization of the xDSL chipset circuit set implemented on the xDSL 6_i card can be carried out: - by recovery of the clock rhythm on the copper line 2_i, - by an internal clock or - by recovery of the clock rhythm from of the service interface 7 or 8 via the links 13_i or 14_i.

  The software part of the analysis device of the invention is split into two applications, called "host" application and "PLC" application. The "host" application is installed on the control or supervision computer and the "PLC" application is embedded on the master card 5 and executed by a microprocessor thereof.

  The two applications communicate by means of the interface 9, which can be of the RS232, GPIB, or other type. The two applications allow the analysis device of the invention to perform actions of: - configuring the physical layer of the selected xDSL "chipset" circuit set and in particular executing: the selection of CO mode of central office emulation or CPE d terminal emulation, * selecting one or more data rates from a list of authorized transmission rates, activating automatic responses to EOC requests from the equipment under test, launching the activation phase and recovering the information 10 relating to the different sequences of activation by performing all the phases described in the xDSL reference standard, - responding to EOC requests when they come from the equipment under test, - generating EOC requests at the request of the user among the EOC requests defined by the xDSL reference standards, - configure a plurality of components in order to authorize a BER error rate test via the inte rface TDM or the ATM interface and in particular: * a traffic control card TDM 3 which comprises a means of defining the time intervals selected to transport the pseudo-random sequence, * a traffic control card ATM 4 which comprises a means for delimiting the ATM connection (UNI, VP / VC) to transport the pseudo-random sequence, * master card 5 which includes a means of activating the data relay function between the traffic control card 3 TDM and a card xDSL 6_i determined or between the TDM 4 traffic control card and a determined xDSL 6 i card.

  To this end, the "host" application opens a session with the "PLC" application in order to define the xDSL 6_i card which will be used for the interoperability test and select the various parameters necessary for establishing the physical layer. xDSL (CO mode or CPE mode, list of authorized debits, ...). These parameters are stored in memory.

  The configuration can then be read by the "host" application by means of a specific request.

  The operation of the "PLC" application is described using FIG. 4.

  The "host" application then commands the activation of the xDSL link.

  When the activation phase is launched, the scheduler 10 15 sends the configuration data to the xDSL component 6_i via the link 22 i.

  In the specific case of SDSL access equipment, the reference standards "ITU G.991.2" and "ETSI TS 101524" break down the activation phase into two phases: a pre-activation phase 15 (G.994.1) and an actual activation phase.

  Figure 3 describes the sequence of these two phases. In FIG. 3, two diagrams of transitions between states are shown for the activation of the two units during communication 20 during activation launching: - on the left, the reception transmitting unit on the central side o simulated by the analysis device, when the analysis device emulates a DSLAM subscriber multiplexer, performed by the DSLAM subscriber multiplexer, when the analysis device emulates an xDSL modem, initially in state 30; - on the right, the transmission unit reception on the remote side o performed by the xDSL modem, when the analysis device emulates a DSLAM subscriber multiplexer, o simulated by the analysis device, when the analysis device emulates an xDSL modem, initially in state 43.

  The process represented at the level of the receiving transmitting unit on the central side, respectively of the receiving transmitting unit on the remote side, first performs a power-up 31, respectively 44, then a preactivation action 32 , respectively 45, according to the standards used.

  On the "remote" side (half-diagram on the left in Figure 5 3), the transceiver unit transmits (state 45) a signal Cr of waveform defined by the standard concerned with determined duration and latency. The signal Cr is detected on the "central" side by a state 33 and the reception transmitting unit on the "central" side emits a signal Sc (state 34) of waveform defined by the relevant standard 10 with durations and latency determined relative to the Cr signal.

  Then, the transmission unit reception on the "remote" side transmits a signal Sr (state 47) of waveform defined by the standard concerned with duration and latency determined relative to the signal Cr. The remote side transmitting and receiving unit "then tests by a test 48 a convergence fault state 49 according to the xDSL standard used.

  Then, the transmission unit reception on the "central" side transmits the signal Tc during a step 35, once its own convergence test 34 of the receiver has been carried out on the signal Sr, the signal Sc being transmitted for a duration determined. A test 37 of absence of detection of the signal Tr is carried out, as well as a convergence fault test 36 on the signal Sr so that, in the two verified cases, 36 and 37, an exception state 38 is 25 written on the reception transmission device on the "central" side.

  Then, the transmitting and receiving unit on the "remote" side produces 51 a signal Tr once it has converged and detected the signal Tc (test 50). The signal Tr is of waveform defined by the standard concerned with determined duration and latency. A test 30 52 of absence of detection of a signal Fc defined below and which depends on the manufacturer of the equipment under analysis is carried out.

  The transmission unit reception on the "central" side transmits a signal Fc of waveform defined by the standard concerned with duration and latency determined during a step 40 after having transmitted frame Tr during the step 60 and the test for detection of the signal Tr of step 36. The signal Fc is transmitted during two activation frames.

  Then, on the transmitting and receiving device on the "remote" side 5, the detection test 53 of signal Fc is carried out and the data is received in a state 54.

  If an exception is detected by a test 55, as in tests 48 and 52, an "exception" state 49 is established on the remote sending device.

  If an exception 42 is detected on the data transmitted to the reception transmission device on the "central" side (state 41), as for test 36 or 37, an exception state 38 is established on the reception transmission device "central" .

  A component application of the "host" application, called a "PLC" application, forms a scheduler 15 which manages a history memory 17 which records a time-stamped history of changes in state of the activation phase.

  The equipment 1 of the analysis device comprises means for forming clock signals with a determined resolution. The changes of state observed at the level of the equipment 1 during the activation of the xDSL link are time-stamped by the means to form clock signals with an accuracy of 1 ms.

  The "host" application cyclically executes a request 25 to retrieve the data from the history memory 17.

  This request enters a memory buffer 19 before being processed by the scheduler 15. The scheduler 15 then retrieves the history data and transmits them to an output memory buffer 20. The scheduler 15 then erases the memory of the 30 historical 17.

  The exchange protocol between the host and the controller does not depend on the type of chipset circuit set used. For this, the "automaton" application comprises a component application, called the "convergence" API, making it possible to control a processor 18 of SDSL management which makes it possible to overcome the differences, in control for example, between the technologies of each game of chipset circuits.

  The equipment under test issues EOC requests which are exchanged on at least one integrated operating channel formed according to what is set out in the xDSL standards. These requests are received by the scheduler 15 via the link 22_i.

  The scheduler 15 includes an automatic response means to the request, the operation of which can be authorized during the configuration of the analysis device 1 of the invention.

  The user, via the Human-Machine HMI command interface which is executed on the command or supervision computer by the "host" application, can create an EOC request to be transmitted to the equipment under test. The "host" application 15 then generates a request stored in the memory buffer 19, then processed by the processor 15 which executes the "scheduler" application. The request is then translated into a specific command that can be understood by the card emulating the "chipset" circuit set 6_i using the component application API 20 of convergence 18 and transmitted to the xDSL "chipset" circuit set 6_i via the link 22_i. .

  The chipset circuit set inserts the EOC command into the channel of the xDSL frame in accordance with. xDSL reference standard. The equipment under test then responds to the request. This response follows the reverse path to the scheduler 15 which analyzes the response and stores it in its timestamped history memory 17. The host making a periodic request to read the history, the response is returned to the user via the HMI human machine interface.

  Once the physical layer has been established, the user can order a test for measuring the bit rate in BERT error. To this end, the analysis device of the invention comprises a means for generating beforehand an EOC command for looping back to the equipment under test. Thus, all the data received by the equipment under test will be retransmitted to the transmitter.

  The user will use a TDM tester generating a pseudo random sequence in TDM mode or an ATM 5 tester generating a 0.191 sequence in ATM mode. In TDM mode, the user must therefore connect a TDM tester to the G.703 / G.704 interface (referenced 7 in the drawing).

  The user then selects the IT interrupts which will be used for the test in the human-machine interface application 10 HMI. Once validated, the "host" application transmits the configuration to the scheduler 15 via a request memory 19. The scheduler then parameters the component 3 in accordance with the configuration via the link 10. The data from the component 3 is then framed and sent to the xDSL "chipset" circuit set 15 via the link 12_i. It will be noted that the link 12_i, which depends on the xDSL 6_i "chipset" circuit set, can integrate the addressing and data transmission function.

  The scheduler performs the opposite operation for the data returned by the equipment under test. These data are then restored on the G.703 / G.704 interface (referenced 7 in the drawing) intended for the TDM tester.

  In ATM mode, the scheduler transmits the ATM configuration required for the transmission of the sequence 0.191 to component 4 via link 11.

  The scheduler then performs the cell relay function to the xDSL 6_i chipset via the 12_i link. The scheduler performs the opposite operation for the data returned by the equipment under test. These data are then restored on the ATM interface 8 intended for the 30 ATM tester.

  Whatever the test configuration (TDM or ATM mode), the tester analyzes the bit error rate.

Claims (4)

  1. Device for analyzing equipment for accessing a high speed xDSL type communications network, characterized in that it includes means for analyzing (1) the physical layer of xDSL links in order to ensure that the physical layer of the equipment conforms to the reference standard used in the xDSL communications system in which the equipment is installed.   2 - Analysis device according to claim 1, 10 characterized in that it also comprises a means for determining the cause of non-operation of a Modem-Multiplexer pair of DSLAM subscribers, which comprises a means for simulating normal behavior a modem and a means of connection to a DSLAM subscriber multiplexer and / or a means for simulating the normal behavior of a DSLAM subscriber multiplexer, and a means of connecting a modem.   3 - Analysis device according to claim 1, characterized in that it also comprises a means of analysis of the different steps (30 - 60) of activation of the physical layer 20 to detect failures and nonconformities of an xDSL modem.   4 - Analysis device according to claim 1, characterized in that it also comprises: - means (6_1 - 6_n) for memorizing the xDSL connection characteristics of a plurality of sets of xDSL "chipset" integrated circuits of the market, - means for detecting (5) failures or nonconformities of the xDSL physical layer of the equipment under test making it possible to decide on the failure state on the basis of the measured data; and - a means for reporting (9) the xDSL equipment in lack of interoperability.   - Analysis device according to claim 4, characterized in that it also comprises means for detecting that a modem does not respect the latency times required by the xDSL standard applied for a change of state.   6 - Analysis device according to claim 4, characterized in that it also comprises a means for putting the DSLAM subscriber multiplexer 5 out of cause in an interoperability failure state.   7 - Analysis device according to claim 4, characterized in that it also comprises a means for emulating the operation of a subscriber multiplexer by working in a CO mode of emulation of the telephone exchange for the establishment of the physical layer and / or a means for emulating the operation of an xDSL modem by working in a CPE mode by emulating a modem on the side of the subscriber to the telephone network.   8 - Analysis device according to at least one of the preceding claims, characterized in that it comprises: 0 equipment (1) for connection to a plurality of copper interfaces at the output (2_1 - 2_n), each copper interface may include a pair of copper or more, interfaces 20 for coupling TDM and ATM mode test equipment (7, 8), a plurality of xDSL line cards each representing a foundry technology (6_1 - 6_n ), a master card (5) hosting a PLC comprising at least one means for configuring the line cards and one means for ensuring exchanges between the test interfaces (7, 8) and the line cards (6_1 - 6_n) and means for ensuring the exchange of information between the device and a control computer by means of a link (9); a software comprising two entities: a "host" application hosted by said control computer connected to the equipment (1) by means of a link (9) and a "PLC" application hosted by the master card ( 5), so that at least one of the following actions is executed * the master card sets all the line cards (61 - 6_n) of different technologies via a convergence API (18) according to a specific configuration by l 'user, * the master card and its automaton supervise the various 5 stages of the activation phase of the selected xDSL link, each event being time-stamped and memorized via the control interface (22_i) with a determined precision, * the master card and its controller respond to EOC requests from the equipment under test, * the master card relays the EOC commands from the host to the specific xDSL line card, * the master card establishes a channel re the test interfaces and the specific line card.   9 - Device according to claim 8, characterized in that the automaton on board the master card includes a scheduler (15), a memory (17) responsible for collecting a timestamped history, a convergence API application (18) to unify the command language for the different xDSL line cards (6_1 - 6_n), an internal clock (16) responsible for providing the reference rhythm, an input memory (19) responsible for receiving requests from the host , an output memory responsible for receiving responses to requests from the host.   - Device according to claim 9, characterized in that the application executed by the automaton hosted by the master card (5): activates the scheduler (15) so that the activation state of the component is cyclically recovered (6i), via requests translated by the convergence API application (18), - organizes a symmetrical data transfer channel between the test interfaces (7, 8) and the component (6_i).   11 - Device according to claim 1, characterized in that the "host" application hosted by said control computer connected to the equipment (1) via the link (9) performs at least one of the following operations: o the capture of all the information relating to the establishment of the xDSL physical layer, o activation of the xDSL layer, o recovery of data archived in a history database (18) comprising at least the state component activation (6d), the content of responses to EOC requests.