FR2842682A1 - Isochronous data stream connection setting method for digital bus networks uses bridge system with parameterizable delay - Google Patents

Abstract

A routing path is obtained between a talker and a listener terminal that includes bridges with the bridges including parameterizable isochronous delay. The values or possible values of delay of the bridges are obtained. For one bridge selecting the value that must be taken so that the stream connection takes a predetermined delay. Independent claims are also included for (1) a computer program, (2) bridge of a digital bus network and (3) device to control the setting up of an isochronous data stream.

Description

Method for establishing an isochronous data flow connection, with

  applying a predetermined total isochronous delay on one or more routing paths. The field of the invention is that of digital bus networks, of the type comprising a plurality of digital buses on which terminals can be connected. Such digital bus networks make it possible to interconnect analog and / or digital audio and / or video terminals (also called devices) so that they exchange audiovisual signals. The terminals belong for example to the following list of equipment (which is not exhaustive): television receivers (satellite, over-the-air, cable, xDSL, ...), television sets, video recorders, scanners, digital cameras , digital cameras, DVD players, computers, personal digital assistants (PDAs), printers, etc. The invention applies in particular, but not exclusively, to digital bus networks of the IEEE 1394 type. It is recalled that the IEEE 1394 standard is described in the following reference documents: "IEEE Standard 1394-1995, Standard for High Performance Serial Bus "and" IEEE Std 1394a-2000, Standard for High Performance Serial Bus (Supplement) ". A third "IEEE P1394.1 Draft 0.17 Standard for High Performance Serial Bus Bridges" document describes how to connect different bus

IEEE 1394 type.

  More specifically, the invention relates to a method for establishing an isochronous data flow connection between at least one input terminal and at least one

  a destination terminal, within a digital bus network.

  Recall that, conventionally, a digital bus network is homogeneous.

  Digital buses are interconnected to each other via homogeneous bridges. Each homogeneous bridge comprises first and second doors, to each of which is connected one of the digital buses. Each bridge allows the transfer of packets from one

  bus, connected to its first door, to another bus, connected to its second door.

  Each bridge is associated isochronous time, for each direction of crossing from one to the other of its doors. This isochronous delay represents the time required for the bridge to pass an isochronous packet from one to the other of its doors. The isochronous delay is mainly used for the transport of common isochronous packets (also called CIP packets for "Common Isochronous Packets") in the network. A CIP packet contains absolute time information, indicating when the packet should be consumed by the destination application. This time information is computed by the isochronous initiator, for a packet transferred on a single bus (where the input terminal, "talker", and the destination terminal, "listener", are connected to the same digital bus). When several bridges separate the input terminal, "talker", and the destination terminal, "listener", the information contained in the CIP packet may no longer be up to date, due to the latency introduced by crossing the bridges. In order to avoid this situation, each bridge between the input terminal and the destination terminal increases the time information contained in the CIP packet with the isochronous delay specific to this bridge (transfer delay between the two buses).

interconnected by this bridge).

  Currently, and in accordance with the aforementioned standards in the case of IEEE 1394 bus, each bridge is associated, for each crossing direction, a constant isochronous delay. In other words, all the isochronous packets transferred across the bridge from a bus to another bus are processed with the same isochronous delay regardless of

the flow to which they belong.

  In a particular embodiment of the present invention, it is also interested in a new type of digital bus network, described as heterogeneous because the digital buses are interconnected with each other either directly, via homogeneous bridges such as mentioned above, or through at least one switched network, via bridges

heterogeneous.

  Each heterogeneous bridge comprises a first gate, to which is connected one of the digital buses, and a second gate to which the switched network is connected. The switched network includes a plurality of nodes, interconnected by a plurality of links. These links are for example of the type allowing bidirectional data transfers, according to the IEEE 1355 standard. It is recalled that the IEEE 1355 standard is defined by the reference IEEE Std 1355-1995 Standard for Heterogeneous InterConnect

  (HIC) (Low Cost Low Latency Scalable Serial Interconnect) (aka ISO / IEC 14575 DIS).

  Each heterogeneous bridge also acts as a node of the switched network.

  The operation of such a heterogeneous network is as follows: a connection is established, via one or more bridges and possibly via the switched network, between a first terminal (or "listener" in English) - connected to a first digital bus -, which wishes to receive audiovisual signals, and a second terminal (destination terminal, or "talker" in English) - connected to a second digital bus -,

who can provide them.

  By input terminal is meant for example a digital camera, a digital camera, a digital output DVD player, or any analog device seen at

  through an analog / digital converter.

  The network (homogeneous or heterogeneous) digital bus is for example a home audio-visual network, including the exchange of real-time animated images, for distribution in the context of a home. In the case where it is

  heterogeneous type, it includes for example a high-speed switched network.

  Two major drawbacks of the state of the art are now presented, related to the fact that at present, and in accordance with the aforementioned standards in the case of the IEEE 1394 bus, each bridge must be associated, for each crossing direction, with a delay.

constant isochron.

  From this obligation arises the impossibility of choosing the total isochronous delay experienced by the isochronous data flow by traversing the routing path between the input terminal and the destination terminal. Indeed, the total isochronous delay is the sum of

  Isochronous delays of successive successive bridges along the routing path.

  The isochronous delays of the bridges to be constant, the total isochronous delay that undergoes

  the flow is therefore also constant and imposed.

  However, there is a need to be able to choose the total isochronous delay, especially for applications such as the provision to a new recipient of information to be synchronized with a previously established flow and whose

delays are different.

  The problem of synchronization of the arrival time to multiple terminals is new. Indeed, currently, it is impossible to ensure that the same stream (from a single input terminal) can be simultaneously received by several destination terminals. In this case, the stream connection takes several routing paths in parallel, each between the input terminal and one of the destination terminals. However, as explained above, the total isochronous delay experienced by the stream on each routing path is constant and imposed. Since the different routing paths generally do not include the same bridges or the same number of bridges, there is no

  no reason that their respective total isochronous delays are equal.

  Thus, for example, it is currently impossible in a digital bus network for loudspeakers (destination terminals) to receive stereophonic data from an input terminal at the same time synchronously. The purpose of the invention is notably to overcome these various disadvantages of

the state of the art.

  More precisely, one of the objectives of the present invention is to provide a method for establishing an isochronous data flow connection within a digital bus network, which makes it possible to choose the total isochronous delay experienced by the isochronous data flow by traversing the routing path between the input terminal and

the terminal (s) recipient (s).

  The invention also aims to provide such a method allowing, in the case of an isochronous data flow connection between an input terminal and several destination terminals, to have the same total isochronous delay on each of the

  routing paths to the different destination terminals.

  Another object of the invention is to provide such a method that can be implemented

  works with a network of digital buses of both homogeneous and heterogeneous types.

  A complementary objective of the invention is to provide such a method allowing, in the case where it is implemented with a heterogeneous digital bus network comprising a switched network, to take into account the account of a delay.

  (variable from one stream to another) introduced by the passage of the flow in the switched network.

  These various objectives, as well as others which will appear subsequently, are achieved according to the invention by means of a method for establishing an isochronous data flow connection between at least one input terminal and at least one destination terminal connected by at least one bridge of a digital bus network comprising a plurality of digital buses interconnected by a plurality of bridges, each bridge being associated with an isochronous delay. According to the invention, at least some of said bridges are associated with a configurable isochronous delay in a range of predetermined values, and said method comprises the following steps: (a) at least one routing path is obtained between said at least one terminal of input and said at least one destination terminal, comprising one or more bridge (s) of which at least one configurable isochronous delay bridge; (b) for each bridge included in said at least one routing path, the value or possible values of the isochronous delay of said bridge are obtained; (c) for at least one configurable isochronous delay bridge included in said at least one routing path, selecting the value, called selected value, to be taken by the isochronous delay of said bridge, so that said flow connection borrowing said least one routing path undergoes a predetermined total isochronous delay; (d) for said at least one configurable isochronous delay bridge included in said at least one routing path, at least one resource of said bridge is adapted and instantiated, so that the configurable isochronous delay of said bridge takes said

selected value.

  The general principle of the invention therefore consists in using at least one bridge of a new type, namely with configurable isochronous delay. In this way, it is possible to choose a predetermined total isochronous delay that it is desired to apply to a given stream when it traverses a given routing path between an input terminal and a destination terminal. This predetermined total isochronous delay is therefore not imposed, unlike that of the prior art (see discussion above). It can be chosen all the more easily and in a range of values even greater than the number of decks isochronous configurable delay is large. In a particular embodiment, all

  bridges are configurable isochronous delay.

  It will also be noted that the choice for a bridge of a significant isochronous delay makes it possible to use the memory of this bridge as a buffering means

privileged in the network.

  In a particular embodiment of the invention, an isochronous data flow connection is established between an input terminal and at least two destination terminals, and said method comprises the following steps: for each of said at least two terminals recipients, there is obtained a routing path, comprising one or more bridge (s) including at least one configurable isochronous delay bridge, between said at least one input terminal and said destination terminal; for each of said at least two routing paths, said steps (b) to (d) are carried out, so that said stream connection undergoes the same predetermined total isochronous delay on each of said at least two paths;

routing it borrows.

  Thus, it is possible to apply the same total isochronous delay to a stream that uses several parallel routing paths. In this way, data transmitted by an input terminal can be received synchronously by several terminals

recipients.

  It is known that a bad positioning of loudspeakers in a so-called "surround" system generates delays between the sound signals (of the order of 1 ms for a bad positioning of the order of 30 cm). If signals intended for this type of speakers are delayed by a different delay depending on the path taken, the sound signal perceived by the user will be disturbed. A configurable delay according to the invention

to correct this problem.

  Advantageously, said digital bus network is a homogeneous network, the digital buses being interconnected directly with each other, via homogeneous bridges each comprising a first and a second gate each of which is connected to one of the digital buses. Said at least one routing path between said at least one input terminal and said at least one destination terminal comprises at least one

  least one homogeneous bridge with configurable isochronous delay.

  Advantageously, said digital bus network is a heterogeneous network, the digital buses being interconnected with one another: either directly, via homogeneous bridges each comprising a first and a second gate each of which is connected to one of the digital buses; or through at least one switched network, via heterogeneous bridges each comprising a first gate, to which one of the digital buses is connected, and a second gate, to which the switched network is connected, the switched network comprising a plurality of nodes. interconnected by a plurality of links, each heterogeneous bridge forming one of the nodes of the switched network; In addition, said at least one routing path, between said at least one input terminal and said at least one destination terminal, traverses the switched network and comprises at least one pair of heterogeneous bridges, respectively forming nodes.

  input and output of the switched network, and possibly at least one homogeneous bridge.

  Said at least one routing path comprises at least one heterogeneous bridge with configurable isochronous delay and / or at least one homogeneous bridge with configurable isochronous delay, each taking into account in its definable isochronous delay, in a given proportion, a delay introduced by the passage of the flow in the network

switched.

  According to an advantageous characteristic, the delay introduced by the passage of the stream in the switched network is taken into account: in a first proportion Pi, in the configurable isochronous delay of one of said heterogeneous bridges, forming the input node of the switched network ; in a second proportion P2, in the configurable isochronous delay of the other of said heterogeneous bridges, forming the output node of the switched network; with the sum of the first and second proportions substantially equal to 100% (Pi + P2

= 100%).

  Preferably, said first and second proportions are both

  substantially equal to 50% (Pi = P2 = 50%).

  Preferably, the time delay, Diel, switched, introduced by the passage of the flow in the switched network is calculated according to the following formula: Switched network = N intermediate nodes x Dcommutadion with N nodes intermediate the number of intermediate nodes in the part of the path of routing included in the switched network,

  and Dchange the average switching time per intermediate node.

  Thus, we take into account the delay introduced by the crossing of each of the nodes located on the part of the routing path included in the switched network, so as to obtain a most accurate estimate of the transfer time of the flow within the network.

switched network.

  Preferably, said at least one adapted and instantiated resource is a

  FIFO memory included in said configurable isochronous delay bridge.

  This plays on the size of the FIFO memory of a bridge to increase or

  reduce, if necessary, the configurable isochronous delay of this bridge.

  In a particular embodiment of the invention, the adaptation and instantiation of said at least one resource of each configurable isochronous delay bridge included in said at least one routing path, is common to several flows, so that the selected value of the configurable isochronous delay

  bridge is applied to each of said streams by said bridge.

  Thus, once the configurable isochronous bridge delay has been adjusted, for a given traversing direction, and takes a given value in the range of possible values, it retains this given value until the next change (e.g. following a restart (reset) of the bridge or the reception by it of a command to update its configurable isochronous delay). Until the next modification, the bridge applies this given value of the configurable isochronous delay to

  all the successive flows that pass through it.

  According to a preferred variant, the adaptation and the instantiation of said at least one resource of each configurable isochronous delay bridge included in said at least one routing path is specific to a particular stream, so that the selected value of the delay configurable isochron of said bridge is applied only to said

particular flow by said bridge.

  In this way, the bridge manages several configurable isochronous delays and selectively applies each of them to a particular stream, independently of other managed streams. A new parameterizable isochronous delay is assigned to each new flow

crossing the bridge.

  Advantageously, said digital buses are digital bus type

IEEE 1394.

  Advantageously, said digital bus network is a home audio-visual network. Such a home audiovisual network makes it possible, for example, to exchange images

  animated, or sound files, in real time as part of a home.

  Preferably, said steps (a) to (c) are performed by a device for controlling the establishment of a flow connection, connected to said digital bus network. Advantageously, said method comprises a step of obtaining a

  description of the network, and during said step (a), said description of the

  network to get the bridges of each routing path.

  Advantageously, said method is implemented for each direction of

  traversing each bridge included in said at least one routing path.

  The invention also relates to a computer program which comprises sequences of instructions adapted to the implementation of the aforementioned method when said

  program is running on a computer.

  The invention also relates to a computer program product for establishing an isochronous data flow connection between at least one input terminal and at least one destination terminal connected by at least one bridge of a bus network. digital terminals comprising a plurality of digital buses interconnected by a plurality of bridges, each bridge being associated with an isochronous delay, at least some of said bridges being associated with a configurable isochronous delay in a range of predetermined values. According to the invention, said computer program product comprises program code instructions recorded on a usable medium in a computer comprising computer readable programming means for performing the following steps: (a) at least one path is obtained; routing between said at least one input terminal and said at least one destination terminal, comprising one or more bridge (s) including at least one configurable isochronous delay bridge; (b) for each bridge included in said at least one routing path, the value or possible values of the isochronous delay of said bridge are obtained; (c) for at least one configurable isochronous delay bridge included in said at least one routing path, selecting the value, called selected value, to be taken by the isochronous delay of said bridge, so that said flow connection borrowing said least one routing path undergoes a predetermined total isochronous delay; (d) for said at least one configurable isochronous delay bridge included in said at least one routing path, at least one resource of said bridge is adapted and instantiated, so that the configurable isochronous delay of said bridge takes said

selected value.

  The invention also relates to a bridge of a digital bus network, of the type associated with an isochronous delay. According to the invention, this bridge is associated with a configurable isochronous delay in a range of predetermined values and it comprises: means for receiving a selected value of said configurable isochronous delay, said selected value being such that a flow connection isochronous data, established between at least one input terminal and at least one destination terminal and using at least one routing path comprising said bridge, undergoes a predetermined total isochronous delay; means for adapting and instantiating at least one of its resources in order to

  that said configurable isochronous delay takes said selected value.

  The invention also relates to a device for controlling the establishment of an isochronous data flow connection between at least one input terminal and at least one destination terminal connected by at least one bridge of a digital bus network comprising a plurality of digital buses interconnected by a plurality of bridges, each bridge being associated with an isochronous delay, at least some of said bridges being

  associated with a configurable isochronous delay in a range of predetermined values.

  According to the invention, said control device comprises: first means for obtaining at least one routing path between said at least one input terminal and said at least one destination terminal, comprising one or more bridges; ) including at least one configurable isochronous delay bridge; second means for obtaining, for each bridge included in said at least one routing path, the value or possible values of the isochronous delay of said bridge; selection means, for at least one configurable isochronous delay bridge included in said at least one routing path, of the value, referred to as the selected value, that the isochronous delay of said bridge must take, so that said flow connection borrowing said at least one routing path undergoes a predetermined total isochronous delay; means for transmitting said selected value to said at least one configurable isochronous delay bridge included in said at least one routing path, so that said at least one configurable isochronous delay bridge adapts and instantiates at least one of its resources in order to that its isochronous delay

  parameterizable takes said selected value.

  In a particular embodiment of the invention, in the case where an isochronous data flow connection is established between an input terminal and at least two destination terminals, said device comprises: first means of obtaining, for each of said at least two destination terminals, a routing path, comprising one or more bridge (s) including at least one configurable isochronous delay bridge, between said at least one input terminal and said destination terminal; said second obtaining means, said selection means and said transmission means being such that, when they are used for each of said at least two routing paths, said flow connection undergoes the same predetermined total isochronous delay on each of said at least two paths of

routing it borrows.

  Advantageously, said selection means are such that the delay introduced by the passage of the flow in the switched network is taken into account: in a first proportion Pi, in the configurable isochronous delay of one of said heterogeneous bridges forming a node switched network input; in a second proportion P2, in the configurable isochronous delay of the other of said heterogeneous bridges, forming the output node of the switched network; with the sum of the first and second proportions substantially equal to 100% (Pi + P2

= 100%).

  Advantageously, said first and second proportions are both

  substantially equal to 50% (P1 = P2 = 50%).

  According to an advantageous characteristic, said device comprises means

  obtaining a description of the network, and said first means of obtaining from

  least one routing path between said at least one input terminal and said at least one

  a destination terminal use said network description to obtain the bridges of

each routing path.

  Preferably, said device can be used for each of the directions

  said at least one routing path.

  Other characteristics and advantages of the invention will appear on reading

  the following description of a preferred embodiment of the invention, given as a

  indicative and non-limiting example, and the accompanying drawings, in which: - Figure 1 shows a block diagram of an example of a homogeneous network of digital buses, wherein can be implemented the method according to the invention; FIG. 2 illustrates an exemplary embodiment of a homogeneous bridge included in the homogeneous network of FIG. 1; FIG. 3 shows an exemplary algorithm implemented by the controller

  included in the homogeneous network of Figure 1, in order to obtain a description

  the homogeneous network of Figure 1;

  FIG. 4 illustrates a description of the homogeneous network of FIG. 1, obtained

  by applying the algorithm of FIG. 3 to the homogeneous network of FIG. 1; FIG. 5 shows an exemplary algorithm implemented by the controller included in the homogeneous network of FIG. 1, in order to establish an isochronous data flow connection according to the method of the invention; FIG. 6 is a block diagram of an example of a heterogeneous network of digital buses, in which the method according to the invention can be implemented; FIG. 7 illustrates an embodiment of a heterogeneous bridge included in

  the heterogeneous network of Figure 6.

  The invention therefore relates to a method for establishing an isochronous data flow connection between at least one input terminal and at least one destination terminal connected by at least one bridge of a digital bus network. This method is such that a predetermined total isochronous delay can be applied along at least one routing path between the (at least one) input terminal and the (at least one) destination terminal. An example of a homogeneous network of digital buses is presented in connection with the block diagram of FIG. 1, in which the following can be implemented:

process according to the invention.

  In this example, the homogeneous network consists of a plurality of IEEE 1394-type buses, referenced 4, 23, 47, 58, 145 and 912, and in accordance with the aforementioned first and second standards ("IEEE Std 1394-1995, Standard for High Performance Serial Bus "and" IEEE Std 1394a-2000, Standard for High Performance Serial Bus

(Extra charge) ").

  The buses are interconnected by homogeneous bridges according to the aforementioned third standard "IEEE P1394.1 Draft 0.17 Standard for High Performance Serial Bus Bridges". The bridges are referenced P1 / P2, P3 / P4, P5 / P6, P7 / P8, P9 / P10, with Pi, i = 1

  at 10, representing a gate of an IEEE P1394 bridge.

  On IEEE 1394 buses are connected terminals or devices. In this example, those referenced D1 to D1, T, Li and L2 are in accordance with the aforementioned first and second standards, and that referenced C is in accordance with the first, second and third

above mentioned standards.

  The device referenced C is a "controller", that is to say a device in charge of controlling the establishment of isochronous data flow connections,

  as described in detail in the remainder of this description.

  By way of example and as illustrated in FIG. 1, the following is considered as the case of establishing an isochronous data flow connection between an input terminal T ("talker") and two destination terminals Li, L2. ("listeners"). The objective is, when it is physically possible, to make the total isochronous delay DT1 between the input terminal T and the first destination terminal T1, equal to the total isochronous delay DT2 between the input terminal T and the second destination terminal T2. The input terminal T is for example a source of A / V flow. In this example, the Dl terminals

  to D1i are not concerned with this establishment of a stream connection.

  FIG. 2 illustrates an exemplary structure of a homogeneous bridge referenced

  P1 / P2, P3 / P4, P5 / P6, P7 / P8, P9 / P10 in Figure 1.

  Such a bridge includes two gates and an internal structure, for data processing so that they can cross the bridge from an incoming bus to an outgoing (adjacent) bus. Each gate B4 comprises layers "PHY", "LINK" and "TRANSACTION" as defined in the first, second and third aforementioned standards. The internal structure includes: routing and flow control tables B5, which enable the bridge to know which types of data packets will cross the bridge in each traversing direction; a ROM configuration B6, which identifies its capabilities (including its isochronous delay, which can be parameterizable, according to the present invention); a clock B2 that makes it possible to synchronize the two doors of the bridge; - B8 FIFOs dedicated to asynchronous packets (whose processing is not the subject of the present invention); B7 FIFOs dedicated to the isochronous packets (whose processing is the subject of the present invention). There must be at least one FIFO for each direction

  crossing each bridge capable of processing isochronous traffic.

  We now present, in connection with FIG. 3, an example of an algorithm

  implemented by the controller C of FIG. 1, in order to obtain a description of the network

homogeneous to which it is connected.

  This algorithm is stored in the controller C's ROM. It is loaded into controller C's RAM memory during power-up and the CPU (CPU) thereof will execute the corresponding instructions when the controller is

  newly connected to an IEEE 1394 bus.

  The network description obtained by the controller thanks to this algorithm

  consists of a list of bus and gate descriptors, which can be updated when a change appears in the network structure (adding or removing a bridge). The network structure change information is propagated on each bus of the network through the gates, when they are informed by their adjacent gate (i.e. the gate belonging to the same bridge). This updating action of the routing card is performed by an "UPDATE ROUTES" message defined in the third aforementioned standard. Thus, the door having its routing card modified by its adjacent door, following the receipt of an "UPDATE ROUTES" message, generates a bus update ("bus reset") on its local bus and indicates in its packet self-identifier ("self-ID packet") that a significant change has occurred in the network "behind" itself. It is recalled that a self-identifying packet is a packet sent by each IEEE 1394 terminal as defined in the first, second and third aforementioned standards, indicating whether the terminal is a bridge, which of its ports are connected, what is its number node physics,

  The object of this algorithm is for the controller C to complete a description of

  network structure such as (in pseudo-C code): / * Net descriptor structure * / typedef std :: list <* BusDescriptor> NetDescriptor; / * Bus descriptor structure * / typedef struct BusDescriptor f unsigned int busID; PortalDescriptorList portals; } BusDescriptor; / * Portal descriptor structure * / typedef std :: list <* PortalDescriptor> PortalDescriptorList; typedef struct PortalDescriptor f unsigned int reachablebus [32]; / * one bit per bus ID * / long long EUI64; unsigned int nodeID; / * IEEE1394 global node ID * / PortalDescriptor * coportal; j PortalDescriptor; During a step referenced S2, it is indicated that the information is

  obtained from local bus devices.

  During a step referenced S3, the controller C identifies the bridge doors present on the local bus. This can be done by analyzing self-ID packets contained in the topology map control and status registers ("TOPOLOGY MAP CSR"). These CSR registers are defined in the aforementioned first and second standards. The self-identifying packets of the devices in accordance with the aforementioned third standard contain a "bridge" field with specific values (2 indicates that the device is a bridge gate, 3 indicates that a change has occurred in the network topology and 0 indicates that the device is not

not a bridge).

  In the network example illustrated in FIG. 1, the result of the operation

  carried out at the step referenced S3 is: gates P2 and P3.

  During a step referenced S4, the controller C obtains the routing cards of the doors identified during the step referenced S3. This information is contained in the response packet to a read block request ("Read Block Request") addressed to the routing card register ("ROUTE MAP CSR") of the gate. The reachable buses are identified in the routing card of a door with a "FORWARD flag" in correspondence with the bus identifier ("bus ID"). In fact, the routing card register is a table with the bus identifiers as inputs and the statuses as outputs (valid ("VALID"), forward ("FORWARD"), clean

("CLEAN") and dirty ("DIRTY")).

  At this stage, in the network example illustrated in FIG. 1, the controller can fill the following parts of the network structure: the network descriptor contains pointers to six bus descriptors (buses referenced 4, 23, 47, 58, 145, 912); the bus descriptor of the bus referenced 47 (local bus for the controller) contains "47" as bus identifier and a list of identifiers P2 and P3; the bus descriptors of the buses referenced 4, 23, 58, 145, 912 respectively contain "4", "23", "58", "145" and "912" as bus identifier and a list of gates (temporarily) empty; the door descriptor of the gate referenced P2 contains: information indicating the bus referenced 912 as a reachable bus; its EU164 (unique identifier) which can be obtained from a response to a read block request ("Read Block Request") addressed to the bus information block ("Bus Info Block") of the gate, in its configuration ROM; its global node ID, as defined in the third aforementioned standard, and consisting of the bus identifier of the local bus and the virtual identifier of the gate - these can be obtained from ( respectively) of a response to a read request of a quadlet addressed to the "CLANINFO CSR" register and of a response to a block read request addressed to the "VIRTUALIDMAP CSR" register of the door (see the third aforementioned standard). for more details on the information available in these registers); the door descriptor of the gate referenced P3 contains: information indicating the buses referenced 4, 23, 58 and 145 as reachable buses; his

  EU164 (unique identifier); its global node identifier.

  The steps referenced S5 to S9 will allow the controller C to fill all the fields of the network descriptor, except that allowing to associate a bridge door to its adjacent door ("co-portal" field of the door descriptor). Filling this

  field is performed by the operations of steps referenced S10 to S15.

  During the step referenced S5, the controller C obtains, from the routing cards of the doors of its local bus, the identifiers of the buses that are used in the network. For example, bus IDs are marked with the flag

  "FORWARD" in the door routing maps.

  In the network example illustrated in FIG. 1, the bus identifiers are those of the buses referenced 4, 23, 58, 145 and 512 (that is to say all the buses of the network except the one

referenced 47).

  Thanks to the mechanism of the steps referenced S6 and S7, the steps are carried out

  referenced S8 and S9 for each of the buses identified during the step referenced S5.

  During the step referenced S8, the controller C obtains the doors present on each bus identified during the step referenced S5. This can be done for example by sending quadlet read requests addressed to a "CSR destination offset" which is specific to IEEE 1394 bridges ("CLANINFO" for example) for all node identifiers between 0 and 62 (63 being used for broadcasting on this bus). The time spent for this action can be reduced once a bridge gate is identified (no error response code in the response to the quadlet read request: in this case, the device to which the request was addressed is a bridge gate, if the response code indicates "extinvalidglobal-ID": the proxy (identified by the field "proxyjD" in the response as defined in the third aforementioned standard) is then a bridge gate) by sending a block read request to his "VIRTUALIDMAP" register. Thus, the assigned virtual identifier can be determined and then

  we will only access these devices to know if they are deck doors or not.

  Then, the unique identifiers (EUI64) of the bridge gates can be obtained by analyzing the response to a block read request addressed to the bus information block of their configuration ROM (as was done before on the bus local

controller C).

  During the step referenced S9, the controller C obtains the routing cards of the doors identified during the step referenced S8. This information is contained in a response packet to a block read request addressed to the "ROUTE MAP CSR" register of the gate. The reachable buses are identified in the gate routing card with a forward flag ("FORWARD") in

  correspondence with the bus identifier ("bus ID").

  After the steps referenced 8 and 9 have been performed for all buses

  present on the network, the controller C has a fairly complete description of the network.

  It remains to make the association of each door with its adjacent door, so that the

  controller knows the bridges between the buses.

  During the step referenced S1O, the controller C obtains, from its

  current description of the network, the list of doors and their corresponding routing map

  (or the "connectable" field of the descriptor of the gate, since it contains enough information for the implementation of the continuation of the algorithm). Then, the controller creates a temporary descriptor of the network gate list, which will be completed later in the algorithm. From this temporary descriptor, he selects the doors that

  allow to reach a single bus (these buses are the leaves in the topology of the network).

  In the network example illustrated in FIG. 1, the controller selects the referenced ports P2 (accessing the bus referenced 912), P5 (accessing the bus referenced 23).

  and P9 (accessing the bus referenced 58).

  By virtue of the mechanism of the steps referenced S1 and S12, the steps referenced S13, S14 and S15 are carried out for each of the gates selected during the step

referenced S10.

  During the step referenced S 13, the controller C defines as current bus the

  bus accessed through the current selected gate.

  During the step referenced S14, the controller C identifies the active gate on the current bus (which can be accessed by the selected gate). An active gate is a gate that is not in a dumb bridge (a mute bridge, which is a bridge that does not send any asynchronous or isochronous packet), which means that its routing card must contain a "FORWARD" flag at least for a bus identifier entry. In the network example illustrated in FIG. 1, for the bus referenced 912 accessed by the gate referenced P2, the active gate is referenced Pi. The controller can then associate the referenced ports P1 and P2 as constituting a bridge, and thus set the door descriptor (in the current network descriptor) for the referenced doors P1 and P2: the "co-portal" field of the door descriptor

  referenced Pi must point to the descriptor of the referenced gate P2, and vice versa.

  During the step referenced S15, the controller C modifies the temporary descriptor so that the doors which constitute the bridge identified during the step referenced S14 are removed from the list of doors to be analyzed (they will never again be selected as gate current during the step referenced S 11). In addition, the corresponding leaf bus (that referenced 912 in the example of the previous paragraph) is removed from the routing cards doors not yet processed. Thus, in the aforementioned example, the gateway routing card referenced P4 in the temporary descriptor, which indicated that the buses referenced 47 and 912 were accessed by this gate, now only indicates the bus referenced 47 as the bus accessed, which allows the referenced gate P4 to be selected during the step referenced S1O (since it

  now allows to reach a single bus).

  After the association between a door and its adjacent door ("co-door" or "coportal" in English) is obtained, it remains valid for the lifetime of the network, which may not be the case for numbering This is why it seems more interesting to obtain a network descriptor consisting of a descriptor of doors pointing to the descriptor of their co-doors, rather than a descriptor of doors pointing to the descriptor of their adjacent buses. It is clear, however, that the invention applies

  whatever the type of descriptor used.

  FIG. 4 illustrates a network description, obtained by application of

  the algorithm of FIG. 3 to the homogeneous network of FIG.

  For the sake of simplification of FIG. 4, for each gate, the gate descriptor does not contain the unique identifier (EU164), nor the global node identifier ("global node ID") of this gate, but only the buses that can be accessed by

  this door and the pointer to the adjacent door ("co-door").

  The network descriptor contains six bus descriptors, one for each bus in the network. For example, one of the bus descriptors identifies the bus with the identifier "47", with a list of two doors P2 and P3, P2 allowing access to the bus 912 with Pi as co-door, and P3 allowing to access buses 4, 23, 58 and 145 with P4 as

co-door.

  This descriptor allows the controller to know during the establishment of a flow connection, which are the bridges on the routing path between a bus on which is connected an input terminal ("talker") and another bus on which is connected a

  recipient terminal ("listener").

  FIG. 5 shows an example of an algorithm implemented by the controller C in order to establish a data flow connection.

  isochronous according to the method of the invention.

  This algorithm is stored in the memory of the controller C. It is loaded into the RAM memory of the controller C during power up. The CPU of the latter will execute the corresponding instructions when the controller receives a stream connection request, requiring that the total isochronous delay between the input terminal ("talker") and the terminal (s). (ux) recipient (s) ("listener (s)") is equal to a predetermined value. If there are several destination terminals, the request requires, for example, that the same total isochronous delay be applied between the terminal

  input and each destination terminal.

  During the step referenced El, the controller C receives a request from

  flow connection as aforesaid.

  During the step referenced E2, the controller C obtains the identifier of the buses on which are connected the input terminal and the terminal (s) recipient (s). This information may be contained in the stream connection request itself, or it may be obtained from the unique identifiers (EUI64) through the use of an EUI64 discovery message by application of the DEP protocol (" Discovery

  and Enumeration Protocol ") (see third standard above).

  During the step referenced E3, the controller C uses its network descriptor (see discussion above in connection with FIGS. 3 and 4) to obtain the bridges of each routing path between the input terminal and each terminal. recipient. The referenced step E4 is implemented only if there are several routing paths for which one wishes to have an identical total isochronous delay. In this case, the controller identifies within these routing paths the bridges that differ for

each routing path.

  During the step referenced E5, the controller C obtains the capacities of these bridges, that is to say, for each crossing direction, the possible value (s) of the isochronous delay of each bridge. This information may be contained in a response packet to a block read request addressed to a bridge capacitance input of

  the configuration ROM of each door.

  Currently, the IEEE 1394 standard (described in the aforementioned third reference document) defines only a single value of isochronous value for a bridge and for a given traversing direction of this bridge, regardless of the flow crossing this bridge. The present invention introduces a new type of bridge, with configurable isochronous delay, which reports in its configuration ROM a range of values of the delay

isochronous it can apply.

  The value of this configurable isochronous delay can be adjusted in a common way for all flows. This means that once the configurable isochronous bridge delay has been adjusted, it can not be changed until the bridge is restarted ("reset") or until it has received a command requesting an update of the value of its configurable isochronous delay. This case applies for example if the internal structure of the bridge comprises a single FIFO memory, for each crossing direction of the bridge,

  to temporarily store isochronous packets.

  According to one variant, for each crossing direction of the bridge, there is a FIFO per stream supported by the bridge. In this case, the configurable isochronous delay is modifiable for each flux supported by the bridge and is independent of

  already supported streams (within the limit of the size of the bridge's internal memory).

  During the step referenced E6, the controller C identifies among the bridges obtained during the steps referenced E3 and E4, those which are configurable isochronous delay. The invention consists in calculating an isochronous delay adapted for these bridges, in order to obtain, over the entire routing path, a total isochronous delay having a predetermined value, or to make identical the total isochronous delays of two

routing paths.

  During the step referenced E7, the controller C calculates the isochronous delay (parameterizable) for each bridge obtained in step E6, so that: the isochronous delay of the bridge is greater than or equal to its minimum value; the isochronous time of the bridge is less than or equal to its maximum value; the sum of the isochronous delays of the bridges of the routing path between the input terminal and each destination terminal is equal to a predetermined value. This predetermined value of the total isochronous delay must be greater than or equal to the minimum value applicable over the entire routing path, and less than or equal to the maximum value applicable on

the entire routing path.

  During the step referenced E8, the controller C informs the configurable isochronous delay bridges of the value that each must apply for the flow connection concerned. This can be done by using a lock request transaction or a Write request to a specific offset in the CSR range of the bridge (as already defined in

  the aforementioned standards for IEEE 1394 transactions).

  Each homogeneous bridge with configurable isochronous delay plays on the threshold of its internal FIFO memory to modify the value of its isochronous delay. More precisely, in the case illustrated in FIG. 1 of a homogeneous network, the homogeneous bridge with configurable isochronous delay instantiates its internal FIFO memory for the flow concerned, so that it has a threshold such that the sum of: - the delay (Bridgewise) that the isochronous traffic undergoes in the internal structure of the bridge, and - the delay (FIFO) that the isochronous traffic undergoes while traversing the FIFO memory (that is to say the delay for the FIFO memory to reach its threshold A), is equal to the isochronous delay defined by the controller for this configurable isochronous delay bridge. It is recalled that the threshold of a FIFO memory corresponds to a quantity of data stored in this memory which, when it is reached, indicates that the

  data can begin to be read.

  During the step referenced E9, the controller C sends the appropriate stream connection command through the network ("JOIN" request as defined in

the third standard mentioned above).

  During the step referenced E10, the controller C terminates the execution of the algorithm and can inform the applicant of the flow connection (the user, another device for which he acted as a proxy, ...) about the status of the establishment of the stream connection. This status is in particular reported in the message "STREAM STATUS" returned to the controller C after the flow connection, as defined

  in the third aforementioned standard.

  It should be noted that instantiation of the FIFO memory of a configurable isochronous delay bridge included in the routing path between the input terminal and an output terminal is preferably performed during the flow connection phase. (That is during the exchange of the "JOIN" and "LISTEN" messages as defined in the aforementioned third standard and indicated above in relation to the step referenced E9). This is particularly suited to the case where the bridges that support the streams have separate FIFO memories for the different streams. Indeed, the bridge can begin to calculate the instantiation of a FIFO memory and reserve the necessary internal resources, and if a rest period (to be determined) expires before receiving the flow connection message (as defined in the step referenced E9), the bridge releases

  internal resources for other uses.

Another possibility, which is also within the scope of the present invention, is to carry out this instantiation directly when the bridge is informed by the controller of the value of the isochronous delay which it must apply (that is to say during

step referenced E8).

  An example of a heterogeneous network of digital buses is presented in connection with the block diagram of FIG. 6, in which the following can be implemented:

process according to the invention.

  In this example, the heterogeneous network consists of a plurality of IEEE 1394 type buses referenced 110, 120, 130, 140, 150 and 250 interconnected to each other.

  other and / or to a switched network 100.

  The bridge 216/217 is a homogeneous bridge interconnecting two buses of the IEEE 1394 type. An example of a structure of such a homogeneous bridge has been discussed and described.

  in detail above, in connection with Figure 2.

  The interconnection of the switched network 100 and IEEE 1394 buses is achieved via heterogeneous bridges, in accordance with the third aforementioned standard. They are each constituted by two paired doors, referenced 201/202, 203/204, 205/206, 207/208 and 209/211. Thus, a heterogeneous bridge referenced X / Y consists of gates themselves referenced X and Y. Each of these heterogeneous bridges has a first gate connected to the switched network 100 and a second gate connected to a digital bus type IEEE 1394. A detailed example of the structure of a heterogeneous bridge

  is presented below in connection with FIG. 7.

  The switched network 100 is seen as a serial bus by all the equipment (terminals, homogeneous bridges, controller, ...) that do not belong to this network

switched 100.

  On the IEEE 1394 buses are connected terminals or devices, referenced 101 to 104 (on the bus referenced 110), 105 to 107 (on the bus referenced 120), 108 and 109 (on the bus referenced 130), 111 to 114 ( on the bus referenced 140), 119 and 121 (on the bus referenced 250), 115 to 118 (on the bus referenced 150). They conform to the first and

second aforementioned standards.

  All of the bridges in FIG. 6 play a resource reservation role during the establishment of a flow connection, as described in more detail in the third aforementioned standard. These bridges, on the routing path from an input terminal ("talker") to at least one destination terminal ("listener"), interpret and exchange inter-bridge messages (for example messages of "JOIN" type). "," LISTEN "," LEAVE "and" STREAM STATUS "), as provided by the IEEE 1394 standard. Such messages provide information on the" talker ", the" listener ", the bandwidth required for the transport of data. isochronous, and the status of

  establishing a flow connection.

  The switched network 100 consists of links referenced 160, 170, 180, 190, 200, 210, 220, 230 and 240 which interconnect: on the one hand nodes referenced 201/202, 203/204, 205/206, 207 / 208 and 209/211, also called heterogeneous bridges, interconnecting the switched network 100 with IEEE 1394 buses, and - secondly nodes referenced 212/213 and 214/215, internal to the network

switched 100.

  The routing of packets through the switched network 100 is achieved by implementing a source routing method, in which the routing information of a packet is computed by a central unit, or CPU referenced 391 in FIG. 7, which knows the topology of the switched network 100.

  aspect will not be described in more detail in the context of the present invention.

  As in the homogeneous network discussed above in connection with FIG. 1, the device referenced C is a "controller" in charge of controlling the establishment of isochronous data flow connections, with a predetermined total isochronous delay. The operation of this controller has already been explained in detail

  in the foregoing (in connection with Figures 1 to 5).

  By way of example and as illustrated in FIG. 6, the processing of an isochronous data flow connection request from the input terminal ("talker") referenced 114 and T '(connected to the referenced bus) is considered. 140), to the terminal

  recipient ("listener") referenced 102 and L '(connected to the bus referenced 110).

  As in the case discussed above of a homogeneous network, the objective is, when it is physically possible, to give a predetermined value to the delay.

  total isochron between the input terminal and the destination terminal (s).

  The controller C, which is integrated in a heterogeneous bridge 201/202, also implements the algorithm of FIG. 5, already described in detail above in the case of a homogeneous network. In the present case of a heterogeneous network, the application of

  this algorithm has some differences discussed below.

  During the step referenced E3, the controller C obtains the homogeneous bridges and / or the heterogeneous bridges of each routing path between the input terminal and each destination terminal. Thus, in the above example, the routing path between the input terminal T 'and the destination terminal L' comprises two heterogeneous bridges.

  referenced 207/208 and 201/202 respectively.

  It is assumed in this example that the heterogeneous bridges referenced 201/202 and 207/208 are configurable isochronous delay and are therefore identified as such during

the step referenced E6.

  During the step referenced E7, when calculating the configurable isochronous delay for each of the heterogeneous bridges obtained in step E6, the controller C

  takes into account the delay introduced by the passage of the flow in the switched network.

  For example, the delay introduced by the passage of the flow in the switched network (also called "latency d switched network") is taken into account: - in a first proportion Pi of 50%, in the parameterizable isochronous time of the bridge heterogeneous referenced 207/208, forming the input node of the switched network; in a second P2 proportion of 50%, in the configurable isochronous time of the

  Heterogeneous bridge referenced 201/202, forming the output node of the switched network.

  The delay, the network switches' introduced by the passage of the flow in the switched network; For example, it is calculated according to the following formula: Switched network e = Intermediate nodes x Dchange with intermediate nodes the number of intermediate nodes in the part of the routing path included in the switched network, and Dcom ,, utation the average switching time per node which can be evaluated by network and switch models, by simulation, and / or by performing

  prototype performance tests. For example: Dcojruajon = 30 gs5.

  In the example mentioned above, the part of the routing path included in the switched network comprises, for example, in addition to the heterogeneous bridges 207/208 and 201/202 (forming input and output nodes respectively of the switched network), the two intermediate nodes. referenced 213 and 214. The latency time of the switched network 100 is

so here equal to 60 gs.

  Each heterogeneous bridge with configurable isochronous delay plays on the threshold (A) of

  its internal FIFO memory to modify the value of its isochronous delay.

  More precisely, in the case illustrated in FIG. 6 of a heterogeneous network, each of the heterogeneous bridges with configurable isochronous delay 201/202 and 207/208 instantiates its internal FIFO memory for the flow concerned, so that it presents a threshold (A) such as the sum of: - the delay time) that the isochronous traffic undergoes in the internal structure of the bridge, and - the delay (RFaF traversed) that the isochronous traffic undergoes crossing the FIEO memory (i.e. say the delay for the FIFO memory to reach its threshold (A)), - of a part (proportion Pi or P2 above) of the delay (Drdseau cte) introduced by the passage of the flow in the switched network, equal to the isochronous delay defined by the controller for this heterogeneous bridge with delay

isochronous parameterizable.

  The delay (bridge delay) that the isochronous traffic undergoes in the internal structure of the bridge is for example 125 ts, taking into account the data recovery time in the DPRAM, the modification time of the packet heads, transfer time to the bus interface, and synchronization time with the bus clock

local IEEE 1394.

  On the switched network 100, the routing path of a packet transiting from a first to a second node may be more or less congested, depending on the data flows that pass through the switch (referenced 320 in Figure 7 discussed below). ) of each heterogeneous bridge. In FIG. 7, the DPRAM 330 acts as a buffer for the data, in order to counter the jitter of the network, and to ensure that: - there is always enough free space to write data in the transmission FIFO ( Tx FIFO), by implementing a stream write operation; - there is always enough data to be transmitted by scheduling in the transmission FIFO (Tx FIFO); - there is always enough free space in the receive FIFO (Rx FIFO) for the re-assembly of data received from the network; - there is always enough data to be read by the receiving FIFO

  (Rx FIFO), by a stream read operation.

  Thus, the instantiation of the FIFO must take into account an estimate of the

  jitter of the switched network 100, in order to guarantee the conditions listed above.

  The switched network 100 is for example clocked by means of a clock at 49, 152 MfIHz. The synchronization of all the nodes of the switched network 100 on this clock is not the subject of the present invention, and therefore will not be described in more detail in this document. An interval time (in English "time slot") on the switched network has a duration of 125 gs, as for a serial bus type IEEE 1394. The transfer of a packet on the switched network is established according to connections already within this switched network. Thus, in the worst case, a packet may be received by the destination node at the beginning of a cycle of 125 gls, if none of the intermediate switches of the routing path were subject to congestion, while the next packet will be received at the end of the next cycle of 125, due to "traffic jams" in some intermediate switches. Therefore, the maximum jitter value of the switched network is 250 ps. A more accurate estimate can be made by analyzing the behavior of the switched network 100 in the presence of concurrent data flows (by simulation, network modeling, prototype performance testing), but a rough estimate of the jitter at 250 ps is sufficient for

illustrate the present invention.

  For an application requiring a data rate of 30 Mbps (for example a DV video format), the estimation of the FIFO size of each heterogeneous bridge needed to counterbalance the jitter of the switched network 100 is as follows: LIFO adapted A + X = 2 * A = 2 * bit rate * jitter = 2 * 30.106 * 250.106 = 1875 bytes - 470 Quadlets As defined above, A represents a first part of the FIFO memory, called the threshold, on which the invention is played. to change the value of the configurable isochronous delay. Moreover, X represents a second part of the FIFO memory, making it possible to counter the jitter of the network. In a preferred embodiment of the invention, X = A is selected. An example of a structure of a heterogeneous bridge referenced 201/202, 203/204, 205/206 is now presented with reference to FIG. 207/208, 209/211, 2121/213

or 214/215 in Figure 6.

  Such a bridge comprises two communication interfaces: a first interface 350 with the IEEE 1394 bus, and a second interface 310 with the switched network. The latter comprises, for example, a CI-type component 13 manufactured by 4Links Ltd (registered trademark), if the switched network is based on the "IEEE 1355-1995" standard.

  Standard for Heterogeneous Interconnect (HIC) ".

  The switch 320 transfers data from a first port to a second port of the switched network interface, receives data from a port of the switched network interface to the DPRAM 330, and transmits data from the network. the DPRAM 330 to at least one port of the switched network interface (in this decreasing order of priority). The operation of such a switch 320 is described in particular in the French patent application No. 01 02037 by the same applicant, not yet published at the filing date of the present application. Such functioning does not make

  the subject of the present invention, it will not be described in more detail in this document.

  The DPRAM 330 is arranged in a set of FIFOs, which allow the transfer of data from the IEEE 1394 interface 350 to the interface of the switched network 310, and vice versa. The DPRAM 330 is managed by the control module

  360, by means of the control signals ctrl2.

  The SAR module 340 is used for segmentation and reassembly (in English "Segmentation And Reassembly") of the data from and to the network interface 310. Thus, IEEE 1394 isochronous packets can be segmented for transmission over the switched network 100. The transfer of asynchronous packets is not part of the present invention, and will therefore not be described in more detail. In addition, the SAR 340 acts as a planner for the transmission of data over the network, in order to respect the time constraints imposed by the

isochronous transfers.

  The configuration of all the modules is carried out by the CPU or CPU 391, via the bus interface 370. The data and control exchanges between the Control / Bridge module 360 and the CPU 391 are carried out via the interface of data 304 and the

  ctrl signals], the bus interface 370 and the host bus 380.

  The bridge module 360 includes a first flow control table (also referred to as the flow routing table), as specified in the aforementioned standards, for communications on the IEEE 1394 interface 350. The bridge module 360 also maintains, in correspondence with this first table, a second flow control table, for communications with the switched network. In addition, the bridge module 360 is in charge of modifying the fields of the IEEE 1394 packets for transmission on the IEEE 1394 interface (350), and in particular fields relating to: the bit rate; the channel taken by the packets; time information (CIP Packets); to indications for the IEEE 1394 interface (350) relating to the transmission rate.

Claims (10)

  A method of establishing an isochronous data flow connection between at least one input terminal and at least one destination terminal connected by at least one bridge of a digital bus network comprising a plurality of digital buses interconnected by a plurality of bridges, each bridge being associated with an isochronous delay, characterized in that at least some of said bridges are associated with a configurable isochronous delay in a range of predetermined values, and in that said method comprises the following steps (a ) at least one routing path is obtained between said at least one input terminal and said at least one destination terminal, comprising one or more bridges (s) including at least one configurable isochronous delay bridge; (b) for each bridge included in said at least one routing path, the value or possible values of the isochronous delay of said bridge are obtained; (c) for at least one configurable isochronous delay bridge included in said at least one routing path, selecting the value, called selected value, to be taken by the isochronous delay of said bridge, so that said flow connection borrowing said least one routing path undergoes a predetermined total isochronous delay; (d) for said at least one configurable isochronous delay bridge included in said at least one routing path, at least one resource of said bridge is adapted and instantiated, so that the configurable isochronous delay of said bridge takes said selected value.   2. Method according to claim 1, characterized in that establishes an isochronous data flow connection between an input terminal and at least two destination terminals, and in that said method comprises the following steps: for each said at least two destination terminals, a routing path is obtained, comprising one or more bridge (s) including at least one configurable isochronous delay bridge, between said at least one input terminal and said destination terminal; for each of said at least two routing paths, said steps (b) to (d) are carried out, so that said stream connection undergoes the same predetermined total isochronous delay on each of said at least two paths; routing it borrows.   3. Method according to any one of claims 1 and 2, characterized in that   said digital bus network is a homogeneous network, the digital buses being interconnected directly with one another, via homogeneous bridges each comprising a first and a second gate to each of which is connected one of the digital buses, and in that said at least one path routing between said at least one input terminal and said at least one destination terminal comprises at least one bridge   homogeneous with configurable isochronous delay.   4. Method according to any one of claims 1 and 2, characterized in that   said digital bus network is a heterogeneous network, the digital buses being interconnected with one another: either directly, via homogeneous bridges each comprising a first and a second gate to each of which is connected one of the digital buses; or through at least one switched network, via heterogeneous bridges each comprising a first gate, to which one of the digital buses is connected, and a second gate, to which the switched network is connected, the switched network comprising a plurality of nodes. interconnected by a plurality of links, each heterogeneous bridge forming one of the nodes of the switched network; in that said at least one routing path, between said at least one input terminal and said at least one destination terminal, traverses the switched network and comprises at least one pair of heterogeneous bridges, respectively forming input and output nodes. output of the switched network, and possibly at least one homogeneous bridge, in that said at least one routing path comprises at least one heterogeneous bridge with configurable isochronous delay and / or at least one homogeneous bridge with configurable isochronous delay, each taking into account in its configurable isochronous delay, in a given proportion, a delay introduced by the passage of the flow in the switched network. 5. Method according to claim 4, characterized in that the delay introduced by the passage of the flow in the switched network is taken into account: in a first proportion Pi, in the parameterizable isochronous delay of one of said heterogeneous bridges forming input node of the switched network; in a second proportion P2, in the configurable isochronous delay of the other of said heterogeneous bridges, forming the output node of the switched network; with the sum of the first and second proportions substantially equal to 100% (Pi + P2 = 100%).   6. Method according to claim 5, characterized in that said first and   second proportions are both substantially equal to 50% (Pi = P2 = 50%).   7. Method according to any one of claims 4 to 6, characterized in that the   delay, switched network, introduced by the passage of the flow in the switched network is calculated according to the following formula: Switched network = intermediate nodes XDcommulation with intermediate nodes the number of intermediate nodes in the part of the routing path included in the switched network,   and Deonrnutaton the average switching time per intermediate node.   8. Process according to any one of Claims 1 to 7, characterized in that   said at least one adapted and instantiated resource is a FIFO memory included   in said configurable isochronous delay bridge.   9. Method according to any one of claims 1 to 8, characterized in that   the adaptation and the instantiation of the said at least one resource of each configurable isochronous delay bridge included in the said at least one routing path is common to several flows, so that the selected value of the configurable isochronous delay   said bridge is applied to each of said flows by said bridge.   10. Method according to any one of claims 1 to 8, characterized in that   the adaptation and instantiation of said at least one resource of each configurable isochronous delay bridge included in said at least one routing path, is specific to a particular flow, so that the selected value of the configurable isochronous delay   said bridge is applied only to said particular flow by said bridge.