FR2835935A1 - Controlled pipeline logic has combined logic units processing input components, flip-flops connected to logic unit inputs/outputs, random signal generator, control bit, maintains data flow - Google Patents

Abstract

The device combines or overlaps commands; the flow path input is decided after each stage. It has combined logic units for processing input components, flip-flops connected to logic unit inputs and outputs, a random signal generator and a control bit. As soon as an input is no longer present the random signal generator is activated to continue the simulated signal; the control bit notified to accept simulated signals, thus maintaining data flow.

Description

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 The present invention relates to a structure for controlled pipeline logic, in which controlled pipeline logic always remains active. Controlled pipeline logic does not reveal its internal functionality, which avoids the risk of unwanted auscultation or listening and analysis.

 Sequential logic can be thought of as being formed by a combination of logic paths and memory elements. The assembly logic path is formed by a plurality of logic gates. The assembly path has no feedback loop or memory element. Its characteristic is that the relation between the entry state and the exit state is fixed. Its output can be directly represented by a form of assembly of the input signals at this time, without any relation to the previous state.

 Currently, sequential central clock logic, such as a controller, is generally designed as a logic state machine. The logical state machine, or state machine, is a machine that can remain in its present state until the next state is started. For example, the sequential clock logic and the logic state machine are formed by assembly logic elements and a memory element. The memory element can be a toggle. The flip-flop is a binary cell intended to store a bit of information. If the logic element receives energy, the flip-flop installed in the state machine can maintain its original binary state until an input signal generates a change of state of the flip-flop.

 The most important features of sequential clock logic are the cost of the gates and its ability to integrate. These two factors are in

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 exponential relation as a function of the complexity of sequential clock logic. Referring to Figure 1, since the sequential clock logic is simple, the base time or cadence of the state machine is then as small as possible and can be used in the easiest way possible.

Therefore, simple clock sequential logic works best when using a state machine.

However, recently, with the requirement to have increasingly complicated sequential clock logic, the state machine has lost its superiority in terms of low cost and integration capacity. On the contrary, when the logic complexity increases above a predetermined level, the cost of designing a sequential clock logic with respect to the state machine is higher.

 Another type of controller is through the use of a pipeline. The pipeline is a technology that overlaps a plurality of instructions. An instruction is broken down into several stages. By reducing the average execution time of each instruction, the production of a central processing unit is increased.

A pipeline divides an instruction into a plurality of pipeline steps or pipeline segments. Each pipeline step executes small parts of different instructions. Pipeline steps are linked together to be formed into a pipeline. The difference between the pipeline and the state machine is that, in a pipeline, at each clock cycle, the data is transferred downwards, while the state machine is determined according to a condition introduced by the input signal and held until the next instruction is entered.

 The time required to enter the next step before the execution of an instruction by the pipeline is

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 called a machine cycle. Therefore, all of the pipeline steps are required to transfer the instruction. The length of the machine cycle is determined by the slowest speed pipeline stage.

In other words, the pipeline has a disadvantage in terms of time delay. In addition, since the pipeline operates under an input or instruction condition such that the data is processed in a pipeline step or has been processed, the pipeline processing mechanism can be deduced by monitoring or listening to and then analyzing . Therefore, the processing mechanism is completely known.

 Correspondingly, the main object of the present invention is to provide a structure for controlled pipeline logic, in which the controlled pipeline logic of the present invention has a minimum clocking time comparable to that of the state machine and the advantages provided by its very nature and by its ability to execute the instructions of a central processing unit. Controlled pipeline logic always remains active. Controlled pipeline logic does not have to reveal its internal functionality, which avoids unwanted auscultation or listening and analysis.

 To achieve this goal, the present invention provides a controlled pipeline logic structure, which must overlap a plurality of instructions. The structure comprises a plurality of assembly logic elements subjected to a part of the input signal. An input and an output of each logical assembly element are connected to a respective flip-flop. A random noise generator uses characteristics of assembly logic elements and electrical supply current to generate random noise in order to control said logic element.

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 than assembly to accept a real input signal or to force said logic element to accept random noise. The controlled pipeline logic is always in an active state, either as a result of the introduction of a possible real input signal into the controlled pipeline logic, or else the controlled pipeline logic executes its internal functionalities. Controlled pipeline logic does not have to reveal its internal functionality, which avoids the risk of auscultation or unwanted listening and analysis.

 Thus, a controlled pipeline logic structure, according to the present invention, overlapping a plurality of instructions, paths for the passage of corresponding data being determined according to the input signals sent to each stage of the pipeline, comprising: a plurality assembly logic elements subjected to a part of said input signals; an input and an output of each logical assembly element being connected to respective flip-flops; a random noise generator, for generating random noise to simulate an input stream, introduced into the assembly logic element; and a binary switch having an active state and an inactive state, for controlling an assembly logic element in order to accept an actual input signal or to be forced to accept a random noise; in which, by the above-mentioned components, a plurality of data paths are formed and when there is no input signal flow in said controlled pipeline logic, said noise generator generates noises random, and the binary switch will impose the acceptance by said logic element of assembly of the random noise as an input signal, so that said logic

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 in controlled pipeline is always maintained in its active state.

 Preferably, the flip-flop of this controlled pipeline logic structure is used to determine a data passing state.

 Advantageously, the clock signals of the assembly logic element and the power supply are used as factors generating random noises.

 Preferably, before determining the path through the controlled pipeline logic, data is sent to any possible path; and, once an actual path is determined, the passage of data in an inappropriate path is stopped.

 According to the description mentioned above, the flip-flop is used to determine the execution of a certain specific condition instead of being maintained in a certain condition. The operation of the present invention is different from that of the scale that is encountered in a state machine. Therefore, controlled pipeline logic has the advantages of eliminating time delay, reducing costs and complexity of the layout, and increasing performance.

 The various objects and advantages of the present invention will be better understood on reading the detailed description below, read in conjunction with the accompanying drawings.

FIG. 1A represents the graphical relationship between the complexity and the cost of the logic.

The figure read represents the graphical relationship between the complexity of the logic and the structure of the present invention.

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 Figure 2 is a schematic view showing the concept of controlled pipeline logic according to the present invention.

FIG. 3 is a schematic view for determining the path for the passage of the data according to FIG. 2.

Figure 4 is a schematic view showing the clock output of a state machine and a controlled pipeline machine.

FIG. 5 is a schematic view showing the state of reception of the signal by a logic assembly element as an actual input signal introduced into the logic elements.

FIG. 6 is a schematic view showing the state of reception of the signal in the same assembly logic element, when no input signal passes through the logic element.

 Referring to Figure 2, a schematic view relating to the controlled pipeline logic of the present invention is illustrated. In the drawing, each small square shape is used to represent a small logical assembly element CL. Each rectangular shape represents a flip-flop FF for storing a bit of data. The dotted line represents a one-bit path for passing the data by different possible paths.

 The controlled pipeline logic of the present invention includes the following components.

 A plurality of logical assembly elements CL.

The input and output of each assembly logic element CL are connected to respective flip-flops FF.

Each flip-flop FF is used to determine the transfer of the data which can be in an active state (execution) or inactive state (not in execution). In each proper path, the data will pass through each logical element of as-

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 different CL appearance, while each CL assembly logic element only processes part of the input signal.

 A random noise generator 20 (see FIG. 5) uses input characteristics coming from a clock of the assembly logic element CL and from the power supply, to generate random noises in order to simulate inputs which pass in the logical assembly element CL.

 A binary switch, or switch, A uses its active and inactive states to control the assembly logic element CL, in order to accept a real input signal or else to impose to accept a random noise.

 Below, Figure 3 is used as an example to describe the operation of controlled pipeline logic 10. It has the following advantages: 1. Controlled pipeline logic 10 overlaps a plurality of instructions. The path is determined by the entry at each stage of the pipeline. The various input signals of the flip-flop FF will induce the passage of the data towards a different path. Of course, in general, some external inputs (II to 17) are expected, to determine the effective path of the data. However, in addition to waiting, the pipeline always performs other operations. Before determining the path through the controlled pipeline logic 10, the data may pass through a possible possible path (with reference to Figure 2). Once a path is determined, data going to an unsuccessful or default path will be stopped (such as the entries Il, 14, and

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I5 in Figure 3, which are fault paths).

 Therefore, no delay is produced.

2. Controlled pipeline logic 10 is formed by a plurality of small assembly logic elements CL instead of a large assembly logic element in the state machine, in order to receive all inputs . We will assume that a controlled pipeline logic 10 fully processes 10 input signals. The CL assembly logic elements found in controlled pipeline logic 10 do not have to execute all of the 10 input signals like what is happening in the state machine, whereas each logic element of assembly C1 is responsible for the input signal, ie for an input signal or less than 10 input signals.

3. The small assembly logic element CL that we have in controlled pipeline logic 10 is only subjected to part of the input signal. Consequently, only a certain assembly logic element CL is pending, the controlled pipeline logic 10 can accept to execute the input instruction which corresponds to the assembly logic. For example, we will assume that a certain logic has three cycles, and that each cycle consists of five clock signals. If this logic is designed by the state machine, 3 cycles need 15 clock signals.

In addition, the next cycle will not start until the previous cycle is completed. On the contrary, if the controlled pipeline logic 10 is used to design the final path, only seven cycles are used. Once the cycle
1 is completed, then cycle 2 starts the corresponding clock signal without waiting for the clock to complete the entire cycle 1. Three cycles with

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 Different clocks can execute the input instruction (referring to Figure 4).

4. The sequential clock logic formed by a large number of small assembly logic elements and memory elements (such as the flip-flop FF) can be designed more easily than a state machine. Furthermore, the memory element belonging to the controlled pipeline logic 10 only determines whether it is in an active state or inactive in certain environments. In addition, each small CL assembly logic element only processes part of the input signal, and therefore the unused gateway is not included in the process. The complexity of the logic is reduced.

5. The discrete state machine maintains its state until the next input signal is received. The representation of controlled pipeline logic is discontinuous, which can be in an active or inactive state. Although, once the input or instruction signals pass through the system, the controlled pipeline logic can execute the input signal or instruction continuously. However, if no input signal passes through the system, the monitored pipeline logic 10 is inactive or at rest.

 To protect clock sequential logic from the risk of unwanted auscultation and analysis in the present invention, a random noise generator 20 is added to the function blocks of controlled pipeline logic 10. In addition, each logic element CL assembly of the controlled pipeline logic 10 is annexed a binary switch A. In this embodiment, in an inactive state, this binary switch is set to "O", while in its active state, it is fixed to "l".

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 For the sake of brevity, we will hereinafter only describe an assembly logic element CL in the controlled pipeline logic 10. In a general state, when input signals pass through the logic, the random noise generator 20 is inactive and the binary switch A of the assembly logic element CL is at "O", precisely in an inactive state. At this time, the assembly logic element CL only receives real input signals (cf. FIG. 5).

 Referring to Figure 6, when the controlled pipeline logic 10 does not receive an actual input signal, the random noise generator 20 will simulate an input signal to pass through the controlled pipeline logic 10. The binary switch A will be toggled from its active state to "l", so that the assembly logic element CL only receives an input signal consisting of random noise.

 Therefore, unauthorized persons cannot perceive that the controlled pipeline logic is in an active state despite the fact that there is transit of a possible real input signal in the controlled pipeline logic 10 or that the controlled pipeline logic 10 performs internal functionality. In other words, it makes no sense, from the behavior of the controlled pipeline logic 10, to deduce its internal functioning. Thanks to these characteristics, the controlled pipeline logic of the present invention is superior to the state machine, among other things from the point of view of performance and safety.

 In summary, the controlled pipeline logic according to the present invention presents the minimum clocking time of the state machine and benefits from the advantage of its structure and the advantages provided by its ability to execute instructions from a central processing unit.

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 treatment. In addition, thanks to the installation of the random noise generator and binary switches, the controlled pipeline logic can always be maintained in an active state. Controlled pipeline logic does not reveal its internal functionality, which avoids unwanted auscultation and analysis. The present invention offers an improvement over the disadvantages of the state machine and the pipeline of the prior art.

 Although the present invention has been described with reference to preferred embodiments, it will be apparent that the invention is not limited to the described details thereof. Various substitutions and modifications have been suggested in the foregoing description and others will appear to those of ordinary skill in the art. Therefore, all of these substitutions and modifications are intended to be encompassed within the scope of the invention, as defined by the appended claims.

Claims (4)

1. A controlled pipeline logic structure overlapping a plurality of instructions, corresponding data paths being determined according to the input signals sent to each stage of the pipeline, comprising: a plurality of logic elements assembly subjected to a part of said input signals; an input and an output of each logical assembly element being connected to respective flip-flops; a random noise generator, for generating random noise to simulate an input stream, introduced into the assembly logic element; and a binary switch having an active state and an inactive state, for controlling an assembly logic element in order to accept an actual input signal or to be forced to accept a random noise; in which, by the above-mentioned components, a plurality of data paths are formed and when there is no input signal flow in said controlled pipeline logic, said noise generator generates noises random, and the binary switch will impose the acceptance by said logic element of assembly of the random noise as an input signal, so that said controlled pipeline logic is always maintained in its active state.  2. Controlled pipeline logic structure according to claim 1, wherein said flip-flop is used to determine a data passing state.  The controlled pipeline logic structure of claim 1, wherein the clock signals of the assembly logic element and the power supply are used as factors generating random noise. <Desc / Clms Page number 13>  The controlled pipeline logic structure of claim 1, wherein, before determining the path through the controlled pipeline logic, data is sent to any possible path; and, once an actual path is determined, the passage of data in an inappropriate path is stopped.