FR2833728A1 - Universal machine, for the simulation of various types of computer architectures, from the simple to the complex - Google Patents

Abstract

The device includes embedded virtual immobile machines (20,21,30,31), i.e. a simple machine is emulated by another hierarchically more complicated machine, with its data emulated totally by this elaborate machine. Each machine virtually having an original architecture, each machine virtually being adapted to execute a programme of emulation or dynamic compilation simulating the virtual complex architecture of its immediate superior machine. The machine language of the two virtual machines immediately lower to it, is specifically configured to allow the execution of all the operations of the superior level machine.

Description

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 The present invention relates to a method and an information processing device. It applies, in particular to personal computers, network computers and computer servers.

 More and more tools used daily work through one or more microprocessors. This is the case of a microcomputer, but also a mobile phone, a car, an appliance, for example. These microprocessors fulfill an essential or accessory role within these tools. These microprocessors can receive and / or send information to the devices to which they are connected.

Since the birth of microprocessors in the 1970s, a multitude of models with very different characteristics have appeared on the market. Every electronics manufacturer has improved their products, and made different technological choices. This phenomenon was particularly pronounced for peripherals (graphics cards, printers, sensors, etc.), which are now available in hundreds of different versions.

This heterogeneity is today a brake. Indeed, the programs must be adapted z Z: D in as many versions as there are microprocessors and peripherals. Moreover, the programs must be able to communicate with each other in a transparent way, which requires a specific adaptation to each different interlocutor. These adaptations are long and expensive to achieve.

To solve these problems, emulation is a solution sometimes used. An emulator is a program, executed on a machine A (machine support), which simulates the hardware architecture of a machine B. We can thus use the programs originally designed for machine B on machine A. We therefore factor the work adaptation of programs from machine B to machine A.

But an emulator is a complex and time-consuming program. It only simulates a particular hardware architecture. But above all, it depends on the architecture of machine A.

The problem is thus only partially solved, since this material architecture A can become obsolete and be replaced by a different model A ', a priori incapable of directly executing the programs written for the machine A.

The Java (trademark) technologies of Sun microsystems (registered trademark) or VP (trademark) of Tao Group (registered trademark) are based on a virtual machine. Emulation techniques make it possible to implement the virtual machine on currently available hardware architectures. These virtual machines have been designed as new programming standards. They are intended to standardize the writing and execution of programs in order to eliminate incompatibilities.

 We observe that the same kind of problem is found in linguistics. The European Commission incurs considerable expenses for the translation of working documents

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langue C vers chaque langue officielle, le nombre de traducteurs nécessaires serait extrêmement ZD réduit. Dans ce cas, l'étape supplémentaire dans le processus de traduction peut entraîner un délai, mais moins de moyens sont nécessaires.

that it generates and for its meetings. Official languages must be translated between them, which implies a multiplication of translations. If all languages were first translated into a common C language (English or Esperanto for example), then retranslated from that language

C language to each official language, the number of translators needed would be extremely reduced ZD. In this case, the extra step in the translation process may result in a delay, but less means are needed.

This solution can be transposed to the problem of the heterogeneity of hardware architectures Zn seen previously. Thus, the simulation of all the programs of a set of machines B, ZD B ', B ", ..., towards a set of machines A, A', A", ..., can be simplified by the use of an intermediate virtual machine C.

Indeed, it suffices to write the emulators of the machines B, B ', B ", ..., for the virtual machine C.

It is then necessary to write on a type of machine A, or any other type of machine A ', A ", .... the emulator of virtual machine C. It is thus possible to execute any program written for the machines B, B', B ", ..., on any machine A, A ', A", ...

There is a factorization of the working time since the emulation programs of B, B ', B ", ... to C are written once and for all.

However, emulator C remains complex and time consuming to write.

In addition, the capabilities of the virtual devices of the machine C depend directly on the capabilities of the devices available on the support machine. If some devices are missing, the programs on machine C may not work. The machine C can not easily adapt to the material environment available on the support machine. Finally, the programmer must write often complicated subprograms making it possible to link the virtual machine C and the peripherals of the machine A (drivers or device drivers). These drivers are specific to a given machine A, and must therefore be rewritten systematically for any new machine A ', A ", ...

Each aspect of the present invention aims to meet all or some of these disadvantages.

According to a first aspect, the present invention aims at an information processing device, characterized by: nested virtual machines, that is to say that one machine is emulated by another, hierarchically from the simplest to the most complex, that is to say that a given machine totally emulates another more complicated and elaborate machine, each virtual machine having an original architecture, that is to say, differentiating itself from the architecture of the other machines of the hierarchy of virtual machines, each virtual machine being adapted to execute an emulation or dynamic compilation program simulating the more complex virtual architecture of next higher level, a virtual machine of a given level in the

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les langages machines des deux niveaux de machines virtuelles les plus bas de la hiérarchie sont C > Z : > spécifiquement conçus pour permettre l'exécution de toutes les opérations du niveau supérieur ; un niveau de la hiérarchie, constituant le sommet de la hiérarchie, n'émule aucun autre niveau de la hiérarchie ; et tout niveau de la hiérarchie peut être lié à une machine réelle généraliste (la machine support) au moyen d'un programme exécutable d'émulation ou de compilation dynamique spécifique à cette machine réelle. hierarchy thus having a simpler architecture than those of all the higher-level virtual machines;

the machine languages of the two lowest virtual machine levels in the hierarchy are C>Z:> specifically designed to allow all top-level operations to be executed; a level in the hierarchy, constituting the top of the hierarchy, emulates no other level of the hierarchy; and any level of the hierarchy can be linked to a real generalist machine (the support machine) by means of an executable program of emulation or dynamic compilation specific to this real machine.

Thus, according to its first aspect, the present invention aims at a set of hierarchically nested virtual machines whose basic machine is an extremely simplified virtual machine C, so that the work for the human being is reduced to a minimum when must be emulated on any machines A, A ', A ", ...

In return, the lower the hierarchical level of a virtual machine, the more difficult it is to design programs for it. That's why it runs an emulator that will simulate a more complex architecture, of a higher level, but more practical to program for the human. This is so for each virtual machine, until one reaches the level of complexity adapted for a given use.

The simplification offered by the present invention is countered by a greater number of operations to be performed for the support machine (lower efficiency). However, most of the work to have a virtual machine of satisfactory complexity is performed by the support machine, since the programmer has only to realize the emulation program of the machine at the base of the hierarchy. The present invention therefore transfers to the software level a maximum of the complexity of an ordinary general-purpose hardware machine, a general-purpose machine being a machine capable of performing any type of mathematical operation.

Thus, according to the first aspect of the present invention, an extremely simplified virtual machine C is implemented so that the work for the human being is reduced when it is to be emulated on any machines A, A ' , AT",...

According to particular characteristics, the machine language of the virtual machine at the base of the entire hierarchy has only two elementary operations. It is therefore very easy to emulate on any machine support A, A ', ...

According to particular characteristics, the two instructions of the lowest level virtual machine are a subtraction and a memory backup.

According to particular characteristics, the machine language of the virtual machine level immediately higher than the virtual machine at the base of the entire hierarchy has four

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 elementary operations. This second level has both a good efficiency and ease of use by a programmer, relative to the lower level.

According to particular characteristics, the machine language of the virtual machine at the base of the entire hierarchy has only four basic operations. It is therefore easy to emulate on any machine support A, A '...

sauvegarde en mémoire, une fonction logique booléenne et un chargement depuis la mémoire. According to particular features, said four instructions are a subtraction, a

backup in memory, a Boolean logic function and a loading from the memory.

Zn ZD 11 Il The Boolean logic function is, for example one of the functions "and" or "or".

According to particular features, the information processing device targeted by the first aspect of the present invention implements an organized and standardized description of the peripherals.

Thanks to these provisions, the implementation of the organized and standardized description of the peripheral devices provides all the information necessary for the virtual machines to be able to adapt to their material environment, whatever it may be, with a limited human intervention.

Thus, the simplification of the virtual machine C is also involved in the management of peripherals.

According to particular features, infinite memory space is managed using addresses having address length information and value information of said address.

According to particular features, the information processing device as succinctly described above implements at least three hierarchically nested virtual machines from the simplest to the most complex.

According to a second aspect, the present invention aims at an information processing method, characterized by at least three nested virtual machines, that is to say that a machine is emulated by another, hierarchically from the simplest to the more complex, that is to say that a given machine fully emulates another more complicated and elaborate machine, each virtual machine having an original architecture, that is to say, differentiating itself from the architecture of the other machines of the hierarchy of virtual machines, each virtual machine being adapted to execute an emulation or dynamic compilation program simulating the more complex virtual architecture of next higher level, a virtual machine of a given level in the hierarchy thus having a higher architecture simple as all higher level machines.

The particular features and advantages of the method of the second aspect of the present invention being the same as those of the process of the first aspect of the present invention are not repeated here.

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temps sur la gestion de ces particularités alors qu'il pourrait le consacrer à d'autres fonctions plus C > essentielles de son logiciel. Le programmeur doit recevoir et/ou envoyer les données au C > périphérique selon un format qui lui est spécifique. C'est donc le programmeur qui se plie doublement aux exigences du matériel. Nous avons cherché à uniformiser la gestion des 1 ZD périphériques pour qu'un même périphérique (ou des périphériques aux fonctions semblables) soit géré de la même façon par le programmeur quel que soit l'environnement matériel dans ZD 1--l lequel est simulée la Machine Universelle. The very wide variety of peripherals greatly complicates the work of the programmer. Devices with similar functions (example: graphics cards) come in a multitude of versions, each with its own specificities, forcing the programmer to move from

time on the management of these peculiarities while he could devote it to other more essential functions of his software. The programmer must receive and / or send the data to the C> device in a format that is specific to it. It is therefore the programmer who complies doubly with the requirements of the material. We have tried to standardize the management of the 1 peripheral ZDs so that the same device (or peripherals with similar functions) is managed in the same way by the programmer regardless of the hardware environment in ZD 1 - l which is simulated the Universal Machine.

For this! In accordance with the aspects of the present invention briefly described below, the devices actually available in a standardized form which is as little as possible to write the emulator of the zero level machine are described.

Each of the following aspects of the present invention intends to overcome all or some of the disadvantages set forth above.

According to a third aspect, the present invention relates to a device management method, characterized in that it implements a tree of device representations, tree in which a device is apprehended by following a path from the root of the device. tree and passing through at least one sheet, the information necessary to control said device being collected during said path, at least each leaf of the tree encountered.

According to particular features, the information necessary to control said device is successively collected at each node or leaf of the tree encountered.

According to particular features, the present invention provides a device management method characterized in that it implements a tree structure for describing any device, tree in which: the description of each device is performed according to the basic characteristics of the device , synthetic information resulting from elementary phenomena and a process of device analysis, these basic features allowing the program controlling the device, executed by a processor, to apprehend the non-algorithmic units that provide the direct interface with the real world units whose arrangement fulfills the function of the device; the description of the devices is organized according to a tree structure resulting from the elementary phenomena and from a device analysis process, this tree comprising nodes and sheets, the links between the nodes being symbolized by branches, a node

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- pour prendre connaissance d'un périphérique, et/ou y accéder, le programme contrôlant les Zn périphériques parcourt l'arbre depuis la racine, noeud qui n'est pas regroupé par un autre noeud et qui représente tous les périphériques, vers les feuilles.

grouping other nodes or sheets that describe it more precisely, a sheet being an indivisible unitary information that does not gather other more basic information,

- to learn about a device, and / or access it, the program controlling the peripheral Zn traverses the tree from the root, node that is not grouped by another node and that represents all the devices, to the sheets .

With these provisions, peripherals with similar functions are handled in the same way, regardless of the hardware environment in which a virtual machine is simulated. Moreover, by considering only the non-algorithmic units, the modeling of the peripheral ZDs is simplified and thus the standardization of their representation and thus their management is facilitated.

A device is thus described according to its basic characteristics, that is to say the set of parameters that control the device and whose arrangement can fulfill the function of the device.

According to particular characteristics, each elementary characteristic, physical or symbolic, governing the ratio of the device to its real environment is represented by a "coordinate", your "coordinates" being grouped in "dimensions", representing dimensions, in the mathematical sense of the In the end, the combination of all "dimensions" forms a space, in the mathematical sense of the term, with n dimensions, in which the function of the device is completely modeled, where n is the number of "dimensions" of the device.

It is observed that an elementary characteristic is represented on a "dimension" by a "coordinate".

 The set of "coordinates" of certain "dimensions" can express an elementary phenomenon of their elementary characteristic (the "modulated characteristic") with a certain intensity among a set of possible intensities. We speak of the "intensity" of a "coordinate".

The choice of an "intensity" among all the "intensities" available for a "coordinate" of a "space" point of a peripheral systematically excludes all the other "intensities" of this same "coordinate". "According to particular characteristics, the" universe "of the peripherals, the root of the tree, brings together two nodes called" groups "located on the next level, these" groups "symbolizing the fate of the information exchanged between the processor and a device: the "group" of the exchange devices, for which the exchanged information is transmitted in an open environment, accessible by other receivers than the processor, thus allowing their communication with the outside of the machine, or the information exchanged are transmitted from transmitters, located in an open environment, to the processor, and - the "group" of the storage devices, for which the information exchanged is trans put in an environment accessible exclusively to the processor.

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Selon des caractéristiques particulières, chacun des"groupes"englobe deux"hyperespaces", les "hyperespaces"du"groupe"des périphériques d'échange indiquant le sens de transmission des 1- c informations, les "hyperespaces" du "groupe" des périphériques de conservation indiquant le niveau de disponibilité de l'information pour le processeur et comportant un"hyperespace"des périphériques de conservation adressables pour lesquels le processeur a un accès direct,

instantané et permanent aux périphériques pour échanger des informations et un"hyperespace" z : l des périphériques de conservation non adressables pour lesquels l'accès aux informations est indirect car il requiert des opérations supplémentaires pour le processeur.

According to particular characteristics, each of the "groups" includes two "hyperespaces", the "hyperespaces" of the "group" of the exchange devices indicating the direction of transmission of the information, the "hyperespaces" of the "group" of the peripherals of conservation indicating the level of availability of information for the processor and having a "hyperspace" addressable storage devices for which the processor has direct access,

snapshot and permanent to devices to exchange information and "hyperspace" z: l non-addressable storage devices for which access to information is indirect because it requires additional operations for the processor.

"espaces" de périphériques, chacun regroupant la description du modèle arborescent d'un C > périphérique. According to particular characteristics, each of the "hyperespaces" includes one or more

"Spaces" of devices, each grouping together the description of the tree model of a C> device.

niveau zéro appelée le cartographe/énumérateur (Mapper/Enumerator) qui prend en charge les ZD protocoles d'accès aux périphériques à partir du niveau zéro, - par un processeur qui reçoit des blocs qui donnent les principales informations permettant d'évaluer la fonction de chaque périphérique et toutes les informations pour calculer et interpréter les données de configuration et d'exploitation, les calculs et interprétations des données

d'exploitation et de configuration étant effectués au moyen de programmes spécifiques insérés e dans ce codage, le second bloc comportant la description d'au moins un"espace"de périphérique et de tous les noeuds qu'il englobe dans une arborescence de représentation des périphériques, et - par un processeur virtuel spécialisé, nommé coprocesseur de périphériques, prenant en charge les programmes de calcul des données de configuration et d'exploitation, ainsi que des directives de dépendance insérées dans les noeuds de l'arbre. According to particular characteristics, the exploitation of the tree structure is ensured: by the support machine, through a portion of the machine's emulation program

Zero level called the Mapper / Enumerator that supports device access ZDs from scratch, - by a processor that receives blocks that provide key information to evaluate the function of the device. each device and all information to calculate and interpret configuration and operating data, data calculations and interpretations

by means of specific programs inserted in this coding, the second block comprising the description of at least one "space" of a device and all the nodes that it includes in a representation tree of peripherals, and - through a dedicated virtual processor, called a device coprocessor, that supports the programs for calculating configuration and operating data, as well as dependency directives inserted into the nodes of the tree.

programmes du coprocesseur qui accèdent à un registre"MER". The processor is then able to execute a program that supports the traversing of the different branches of the tree to access the peripherals, via the

coprocessor programs that access a "MER" register.

Zn In zero level, the "TREE" blocks are transmitted to order by the cartographer / enumerator, via the register "MER". All of these blocks contain all the information needed to reconstruct a complete device tree. "LINK" blocks are installed in the memory of the support machine by the cartographer / enumerator, who calls them according to the "spaces" of peripherals used. The "FEXT" blocks are explicitly loaded by a program written at level 0.4 and enrich the descriptions of the "TREE" blocks.

According to a fourth aspect, the present invention aims to access devices from a processor:

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pour établir la communication avec le périphérique voulu, un plan d'organisation de la mémoire z : l étant mis en oeuvre, et - la gestion des autres données repose sur un seul registre situé à une adresse mémoire fixe. - for access to the data of certain devices to which only the processor can access, both in reading and writing, not being taken into account the accesses by means other than the processor that do not result in any change in the peripheral environment of the processor or on the processor itself, and do not change the direction of information exchanged with the device, some portions of the address space are specialized for the devices, and a portion corresponds to a device particular, that it is sufficient to execute the processor an instruction that accesses that portion of the address space

to establish communication with the desired device, a z: 1 memory organization plan being implemented, and - the management of other data is based on a single register located at a fixed memory address.

- le premier bloc qui permet de transporter et d'aiguiller les données de configuration et c d'exploitation échangées entre un processeur et au moins un périphérique particulier de la machine support par l'intermédiaire d'un registre, le premier bloc établissant le lien avec les adresses d'accès à chaque dit périphérique sur la machine support, et contenant des programmes écrits dans le langage machine natif de la machine support afin de transporter les données échangées aux bonnes adresses, ces programmes permettant aussi de détecter la présence de chaque dit périphérique et d'initialiser chaque dit périphérique dans un état stable permettant son bon fonctionnement ultérieur ; et - le second bloc qui donne les principales informations permettant d'évaluer la fonction de chaque dit périphérique et toutes les informations pour calculer et interpréter les données de configuration et d'exploitation, l'évaluation étant permise par le codage binaire du modèle théorique arborescent, tandis que les calculs et interprétations des données d'exploitation et de configuration sont effectués au moyen de programmes spécifiques insérés dans ce codage, le second bloc étant la description, pour chaque dit périphérique, del'"espace"de périphérique et de tous les noeuds quel'"espace"englobe ("espace","dimensions","coordonnées"et "intensités"), donc une portion de l'arbre, et indiquant t'"hypcrespace"auquel appartient ledit "espace". According to a fifth aspect, the present invention is directed to a method for operating peripherals, characterized in that all the information necessary for operating a device is gathered in at least two separate data blocks:

the first block which makes it possible to transport and route the configuration and operating data exchanged between a processor and at least one particular device of the support machine via a register, the first block establishing the link with the access addresses to each said device on the support machine, and containing programs written in the native machine language of the support machine in order to transport the exchanged data to the correct addresses, these programs also making it possible to detect the presence of each said device and initialize each said device in a stable state allowing its subsequent operation; and the second block which gives the main information making it possible to evaluate the function of each said peripheral and all the information for calculating and interpreting the configuration and operating data, the evaluation being allowed by the binary coding of the theoretical tree model. , while the calculations and interpretations of the operating and configuration data are carried out by means of specific programs inserted in this coding, the second block being the description, for each said peripheral, of the "space" of the peripheral and all the nodes which "space" encompasses ("space", "dimensions", "coordinates" and "intensities"), thus a portion of the tree, and indicating "hypcrespace" to which said "space" belongs.

According to particular characteristics, all the information relating to the operation of a device comprises a third block, which contains a type of modeling of physical, symbolic or logical characteristics making it possible to specify the behavior in the reality of the "spaces". "," dimensions "," coordinates "and" intensities "included in the second block, including elementary features associated with them. It can also contain other information enriching the second block.

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(par exemple graphiques). The third block, "FEXT", may be present when the second block, "TREE", can not provide certain information. It can contain physical equations, symbolic representations

(for example graphics).

chaque groupe possède le même nombre de"coordonnées", c aucun groupe ne comporte qu'une seule "coordonnée", il n'existe pas de phénomène élémentaire qui n'appartienne ni à une caractéristique intra-groupe, ni à une caractéristique inter-groupes et au moins deux"coordonnées"de la"dimension mère"doivent comporter au moins un phénomène élémentaire ; pour chaque groupe, l'ensemble des phénomènes élémentaires présents à l'identique dans chaque "coordonnée"du groupe étant nommé"caractéristique intra-groupe", parmi les éventuels phénomènes élémentaires n'appartenant pas aux caractéristiques intragroupes, l'ensemble des phénomènes élémentaires qui sont présents à l'identique dans une "coordonnée"de chacun des groupes est nommé"caractéristique inter-groupes", un phénomène élémentaire ne pouvant participer qu'à une seule caractéristique inter-groupes ; b) dans le cas d'un rassemblement en un seul groupe respectant les règles suivantes : la"dimension mère"contient au moins deux"coordonnées", toutes les "coordonnées" contiennent des "intensités", et la caractéristique modulée de chaque"coordonnée"fait partie de la caractéristique intra-groupe ; au moins un phénomène élémentaire présent à l'identique dans chaque"coordonnée"du groupe étant nommés "caractéristique intra-groupe", According to a sixth aspect, the present invention is directed to a device modeling method, characterized in that it comprises, for each peripheral: a step of microscopic analysis of said peripheral to determine the phenomenal characteristics as well as the exclusive sets relating to said auditory device; peripheral; an initial step during which it is considered that no "dimension", "coordinate" or "intensity" is defined, each of the exclusive sets being associated with a set of "intensities" attached to a new "coordinate" , the phenomenal characteristic linked to the exclusive set being associated with this new "coordinate", for an exclusive set, each "intensity" representing a distinct operating datum, the set of "coordinates" being grouped together within a only "dimension"; - iterative steps during which, for each existing "dimension", called "mother dimension", one seeks to gather all its "coordinates" in at least one group by respecting the following rules: a) in the case of a rally in at least two groups, respecting the following rules:

each group has the same number of "coordinates", c no group has only one "coordinate", there is no elementary phenomenon which does not belong either to an intra-group characteristic or to an international characteristic. groups and at least two "coordinates" of the "mother dimension" must have at least one elementary phenomenon; for each group, all the elementary phenomena present identically in each "coordinate" of the group being named "intra-group characteristic", among the possible elementary phenomena not belonging to the intragroup characteristics, the set of elementary phenomena which are present identically in a "coordinate" of each of the groups is called "inter-group characteristic", an elementary phenomenon that can only participate in one inter-group characteristic; (b) in the case of a single group meeting the following rules: the "parent dimension" contains at least two "coordinates", all "coordinates" contain "intensities", and the modulated characteristic of each "coordinate""is part of the intra-group characteristic; at least one elementary phenomenon present identically in each "coordinate" of the group being called "intra-group characteristic",

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pour chaque"coordonnée", une caractéristique inter-groupes rassemble les éventuels phénomènes tD élémentaires qui n'appartiennent pas à la caractéristique intra-groupe ; c) dans les deux cas, le non respect d'au moins une règle interdisant le rassemblement des ZD "coordonnées"en groupe (s) et rendant définitive la "dimension" ; - une étape de constitution de"dimensions"au cours de laquelle, s'il est possible de constituer

des groupes selon les règles a) et b), alors deux nouvelles "dimensions" sont créées : Z : > C > une "dimension" possédant un nombre de "coordonnées" égal au nombre de"coordonnées"d'un groupe de la "dimension mère", les caractéristiques phénoménales des "coordonnées" de cette nouvelle "dimension" étant celles d'un groupe quelconque de la "dimension mère", desquelles on

a retiré la caractéristique intra-groupe, Z : D une"dimension"possédant un nombre de"coordonnées"égal au nombre de groupes de la "dimension mère", chacun de ces groupes engendrant une "coordonnée" de la nouvelle 1- ZD "dimension", la caractéristique intra-groupe de chacun de ces groupes constituant la 1 caractéristique phénoménale de la "coordonnée" engendrée, une"intensité"restant toujours liée à a "coordonnée" qui contient la caractéristique modulée, et donc à la "dimension" qui contient cette "coordonnée" ; - une fois toutes les "dimensions" traitées, une étape de finalisation au cours de laquelle, s'il n'a pas été possible de créer des groupes sur au moins une des "dimensions", alors la construction du modèle est terminée, les "dimensions" produites étant regroupées au sein de f'espace"du périphérique.

for each "coordinate", an inter-group characteristic collects the possible elementary tD phenomena that do not belong to the intra-group characteristic; c) in both cases, the non respect of at least one rule prohibiting the gathering of the "coordinated" DZ in group (s) and making definitive the "dimension"; - a step of constitution of "dimensions" during which, if it is possible to constitute

groups according to the rules a) and b), then two new "dimensions" are created: Z:>C> a "dimension" having a number of "coordinates" equal to the number of "coordinates" of a group of the " dimension ", the phenomenal characteristics of the" coordinates "of this new" dimension "being those of any group of the" mother dimension ", of which

has removed the intra-group characteristic, Z: D a "dimension" having a number of "coordinates" equal to the number of groups of the "mother dimension", each of these groups generating a "coordinate" of the new 1ZD " dimension ", the intra-group characteristic of each of these groups constituting the phenomenal 1 characteristic of the generated" coordinate ", an" intensity "always remaining linked to a" coordinate "which contains the modulated characteristic, and therefore to the" dimension " which contains this "coordinate"; once all the "dimensions" have been processed, a finalization stage during which, if it has not been possible to create groups on at least one of the "dimensions", then the construction of the model is completed, the "dimensions" produced being grouped within the "space" of the device.

Other advantages, aims and features of the present invention will emerge from the description which follows, given with reference to the appended drawings, in which: FIG. 1 represents, schematically, a representation of a peripheral in a space, at the using dynamics, - Figure 2 shows, schematically, steps of modeling a device, - Figure 3 shows, schematically, two configurations of a device, - Figures 4 and 5 show, schematically, a microscopic structure, 2, a device, FIGS. 6 to 14 schematically represent a dimension produced during a modeling step illustrated in FIG. 2; FIG. 15 is a diagrammatic representation of a device tree conforming to FIG. In one aspect of the present invention, FIG. 16 schematically represents a path of nodes of a tree representing according to one aspect of the present invention, and - Figure 17 shows a virtual machine organization scheme in an exemplary embodiment of the first aspect of the present invention.

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Throughout the description, in the preamble and the claims, the following definitions are used.

précis appelé "langage machine" du processeur. L'ensemble des éléments des périphériques Il z accessibles par un quelconque moyen logiciel ainsi que le langage machine constituent ce que t ID C > nous appelons "l'architecture matérielle". Le terme "machine" désigne dans la suite une "machine à registres" (ou machine de Von Neumann). z : l On appelle "machine universelle" une machine mettant en oeuvre au moins un aspect de la présente invention. The set of elements of a (micro) processor accessible by any software means (the instructions, the registers, the management of the memory, ...), results in a binary coding

precise called "machine language" of the processor. All the elements of the peripherals that can be accessed by any software means as well as the machine language constitute what we call the "hardware architecture". The term "machine" hereinafter refers to a "register machine" (or Von Neumann machine). z: l A "universal machine" is a machine embodying at least one aspect of the present invention.

langage machine donné, tout comme un "processeur réel" est un ensemble de mécanismes Zr > physiques (par exemple électriques) qui réalisent le langage machine pour lequel il a été conçu. We denote by "virtual processor" a set of software mechanisms that realize a

given machine language, just as a "real processor" is a set of physical Zr> mechanisms (eg electrical) that realize the machine language for which it was designed.

A virtual processor therefore simulates a real processor. If we add a simulation program for peripherals connected to the processor, we obtain a "virtual machine".

The "efficiency" of a machine language is defined by its ability to perform all the operations of a high level language in a minimum of instructions.

It is observed that for the purposes of the present invention, a tree, or a tree, is a graph that is traversed starting always from the same predetermined node, called "root".

 Preferentially, the tree or tree is, however, a tree in the mathematical sense of the term, that is to say having other ends than the root.

First aspect of the present invention, illustrated in FIG.

1-Introduction to the Zero Level Machine The zero level machine, based on the hierarchy of nested emulators constituting the Universal Machine, comes in two distinct versions called "machine level 0. 2" 20 and "machine level 0 4 "21. Most of the features of these machines are similar.

1. 1 - Introduction to Level 20 Machine 20 Level 0.2 represents the foundations of the Universal Machine. This is the simplest level of the entire hierarchy of nested emulators. The execution of all higher level programs may be based on it. We distinguish the virtual machine 20 level 0.2 of the emulator 22 level 0.2.

The level 20 virtual machine 20 presents itself to the programmer as a minimal computer, with a basic machine language and access to the peripherals 32.

The emulator 22 of level 0.2 is the program responsible for performing the translation of the operations of the virtual machine of level 0.2 into executable operations by the support machine 23. As

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 the level 20 machine 20 is extremely simple, the programming of this translation is very easily (of the order of a few days for a programmer).

d'émulation du niveau 0. 2 dans le langage natif de la machine support 23. Tous les émulateurs c t, des niveaux supérieurs s'exécuteront directement sur cet émulateur 22. When you want to use a machine of the hierarchy, it is enough to adapt the algorithm

emulation level 0. 2 in the native language of the support machine 23. All emulators ct, higher levels will run directly on this emulator 22.

1. 2 - Introduction to Level 21 Machine 21 The 0.2 level instruction structure involves a large increase in the number of operations required to execute programs written in a high level language (low efficiency) compared to a machine. virtual (or physical) classic. This results in a very strong slowdown of the Universal Machine which can be harmful for some applications.

The inventors analyzed the least efficient characteristics of level 0. 2 and enriched it accordingly.

simple, il entraîne une augmentation raisonnable du nombre d'opérations nécessaires pour C > exécuter des programmes écrits dans un langage de haut niveau. Level 0.4 represents a very good compromise between simplicity and efficiency. While remaining very

simple, it results in a reasonable increase in the number of operations required to execute programs written in a high-level language.

C>:> ID Here again there is the machine 21 of level 0. 4 of (emulator 24 of level 0. 4, with one difference: the emulator 24 of level 0.4 can be written directly for the machine support 23 or for the machine 20 of level 0. 2. The second case respects the hierarchy (the virtual machine 21 level 0.4 is simulated by the virtual machine 20 level 0.2 which is simulated by the support machine 23). If the hierarchy is short-circuited, the execution of all programs at the top of the hierarchy may be based on level 0.4 instead of level 0.2.

When it is desired to create a Universal Machine on a support machine 23, it suffices to adapt the emulation algorithm of the level 0.2 or 0.4 (or higher), as required, in the native language of this support machine 23.

convention, on numérote les bits du mot de 0 à 15, de droite à gauche. Les données sont z enregistrées dans des fichiers au format binaire"big endian" (octet de plus fort poids stocké à l'adresse de plus faible numéro). Les données sauvées en mémoire peuvent être au format Il little

endian"ou"big endian". En effet, les programmes exécutés sur la machine de niveau zéro n'ont ZD pas la possibilité de le vérifier, et n'en sont pas affectés. Par contre, en environnement multiprocesseur, il faut s'assurer que tous les processeurs utilisent le même format de données pour le stockage en mémoire. 2-Data Format The elementary unit that can be manipulated by the zero-level machine is the 16-bit word. The data has a fixed size of 16 bits. Note the Least-Significant Bit (LSB) to the right of the word, and the Most-Significant Bit (MSB) to the left. By

convention, we number the bits of the word from 0 to 15, from right to left. The data is z saved in "big endian" binary format (most significant byte stored at the lowest numbered address). The data saved in memory can be in the format Il little

endian "or" big endian "because programs running on the zero-level machine do not have the ability to check it, and are not affected by it, but in a multiprocessor environment, you have to ensure that all processors use the same data format for storage in memory.

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We recall that, by convention, a "$" character preceding a number indicates that it is expressed in hexadecimal base.

3-Organization of the address space The address space of the machines of level zero (ie 0.2 and 0.4) is undefined in size. It starts at address 0, continues sequentially at addresses), 2, 3, ..., and its end address has no logical limit. Each address points to a 16-bit word.

The structure of the control registers of the level 0. 4 machine 21 causes a segmented and paged ZD vision of the address space of the level 0.4 machine. This same vision also applies to the machine 20 level 0.2.

part) sont donc des plages d'adresses de taille fixe, situées les unes à la suite des autres, et c couvrant l'ensemble de l espace d'adressage. The address space is seen as being cut into segments of 64 kilobytes (or Kmots, a ZD Z = Kmot corresponding to 1024 16-bit words) for reading the instructions composing a program (i.e. 'fetch' stage). This space is also seen as being cut into pages of 8 Kmots for reading or writing data. These segments (and these other pages

part) are thus fixed-size address ranges, one after the other, and c covering the entire address space.

programme tente d'y accéder. We define by "valid address", an address to directly access a 16-bit information bijectively (examples of information media: RAM, ROM, EEPROM, ...). Such information is accessible only by the virtual processor. Any other address is called "invalid address", and systematically provokes the exception (see paragraph 7) if a

program tries to access it.

Zn In this space of address, one distinguishes a "exploitable space", as well as a "space inexploitable" infinite, disjointed of the first, and located immediately after. These two spaces cover the entire address space. The exploitable space corresponds to the set of segments containing at least one valid address. The unusable space corresponds to all other segments, consisting only of invalid addresses. "Addressable space" defines the set of valid addresses of the exploitable space. By "executable addressable space" is defined all the addresses of the addressable space where the emulator can fetch the instructions to be executed. The rest of the addressable space is referred to as "non-executable address space".

The exploitable space is subdivided into two or three disjoint areas that correspond to memories having possibly different properties, such as RAM, ROM and EEPROM.

These areas cover the entire exploitable space. Each of these areas is continuous and starts at the beginning of a segment of 64 Kmots. A given area occupies one or more segments in their entirety, to the exclusion of any other area. One zone will not necessarily use the 65536 addresses of its last segment. In this case, the invalid addresses are grouped at the end of the segment.

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The different zones are defined as follows: The first zone consists of the first segment of the address space (addresses 0 to 1C> 65535). The first page of this field contains valid rewritable memory addresses that are grouped from the beginning of the page (address 0). The second page is for ZD c use at level 0. 2. It may have valid rewritable memory and read-only memory addresses, regardless of the structure of the first page. The remaining six z pages may have valid rewritable memory addresses that are grouped from the beginning of the third page (address 16384) in one block, provided that the first page contains no invalid addresses.

. tl The second field starts at the beginning of the second segment of the address space (ZD address ZD 65536). It may continue on the following segments. All addresses of all the segments it occupies must be valid, and must contain the same type of memory. When starting the zero level machine, this zone must contain the 0.4 boot program.

est valide. Dans ce cas, elle est constituée d'un ou plusieurs segments contigus. Le dernier Z, V > segment contient au moins une adresse valide. Ces adresses valides sont placées les unes à la suite des autres à partir de la première adresse de ce dernier segment. Tous les segments précédents éventuels ne contiennent que des adresses valides. Toutes les adresses valides de la troisième zone doivent contenir le même type de mémoire réinscriptible. The third zone is optional, starts immediately after the last segment of the second zone, and can only exist if the last address of the first segment (address 65535)

is validated. In this case, it consists of one or more contiguous segments. The last Z, V> segment contains at least one valid address. These valid addresses are placed one after the other from the first address of this last segment. All previous possible segments contain only valid addresses. All valid addresses in the third zone must contain the same type of rewritable memory.

 3. 1 - Specificity of the address space of the level 21 machine. The executable address space corresponds to the entire addressable space. The second page is reserved for the use of level 0.2. A program must never attempt to access this page under penalty of serious malfunctions if the machine level of 0.4 0.4 is emulated by the machine 20 level 0.2.

3. 2-Specificity of the address space of the machine 20 of level 0.2 For the sake of speed, the address space of the machine 20 level 0.2 is strictly identical to that of the machine 21 level 0.4. However, the structure of the instruction pointer (IP) modifies the definition of the executable addressable space: it is limited to the addressable space of the first zone, that is to say to the first 64 Kmots at most. The presence of memory is mandatory from the $ 2000 address to store the startup program 0.2.

4-ZD processor registers The register structure of level 0.2 is simplified compared to that of level 0.4.

 4. 1-Level registers 0.2

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<Tb>
<tb> Mode <SEP> Name <SEP> of <SEP> register <SEP> Size <SEP> Role
<tb> access
<tb> Read / <SEP> SE <SEP> 16 <SEP> bits <SEP><SEP> Registry <SEP> communication <SEP> with <SEP>
<tb> Write <SEP> (Mapper / Enumerator <SEP> Cartographer / Enumerator <SEP> 25.
<Tb>

Address <SEP> 0 <SEP> Register)
<tb> Write <SEP> MPW <SEP> 16 <SEP> bits <SEP> Access <SEP> to <SEP> the <SEP><SEP><SEP> portion of the <SEP><SEP> pointer
<tb> Address <SEP> 1 <SEP> (Memory <SEP> Pointer <SEP> Data <SEP> in <SEP> Memory <SEP> (designated <SEP> by <SEP> MPS).
<Tb>

window)
<tb> Write <SEP> IP <SEP> 16 <SEP> bits <SEP> Access <SEP> to the <SEP> statement <SEP> pointer.
<Tb>

<SEP> 2 <SEP> Address (<SEP> Pointer Statement)
<tb> Write <SEP> MPS <SEP> 16 <SEP> bits <SEP> Select <SEP> from <SEP><SEP><SEP> 16 <SEP><SEP> Bit <SEP><SEP> from
<tb> Address <SEP> 3 <SEP> (Memory <SEP> Pointer <SEP> Data <SEP> to <SEP> where <SEP> on <SEP> wishes to <SEP> access.
<Tb>

Selection)
<tb> Implicit <SEP> R <SEP> 16 <SEP> bits <SEP> Internal <SEP> register <SEP> to <SEP> general <SEP> usage.
<Tb>

(Register)
<tb> Implicit <SEP> B <SEP> 1 <SEP> bit <SEP><SEP><SEP> Binding flag when <SEP> of a <SEP> subtraction.
<Tb>

(Borrow)
<tb> Default <SEP> MP <SEP> Undefined <SEP><SEP> Pointer <SEP> Data <SEP>: <SEP> Specifies <SEP><SEP> Address for
<tb> (Memory <SEP> Pointer) <SEP> access <SEP> to <SEP> data <SEP> in <SEP> memory.
<Tb>
The difficulty of programming the level 0.2 makes it unlikely to be a direct general use.

That's why it was primarily designed to emulate level 0.4.

4. 2-The registers of level 0.4 (one observes that "L / E" means "Reading / Writing")

<Tb>
<tb> Mode <SEP> Name <SEP> of <SEP> register <SEP> Size <SEP> Role
<tb> access
<tb> LIE <SEP> R <SEP> 16 <SEP> bits <SEP> Internal <SEP> register <SEP> to <SEP> general <SEP> usage.
<Tb>

Address <SEP> 0 <SEP> (Register)
<tb> L / E <SEP> IPW <SEP> 16 <SEP> bits <SEP> Access <SEP> to <SEP> The <SEP><SEP> portion <SEP> of the <SEP> pointer
<tb> Address <SEP> 1 <SEP>(<SEP> Instruction <SEP> Pointer of <SEP> instructions (referred to as <SEP> by <SEP> IPS).
<Tb>

window)
<tb> LIE <SEP> IPS <SEP> 16 <SEP> bits <SEP><SEP><SEP> selection <SEP><SEP><SEP> 16 <SEP><SEP><SEP> bit
<tb> Address <SEP> 2 <SEP>(<SEP> Pointer <SEP> Instruction <SEP> statement to <SEP> where <SEP> on <SEP> wishes to <SEP> access
<tb> Selection)
<tb> L / E <SEP> MPW <SEP> 16 <SEP> bits <SEP> Access <SEP> to <SEP> The <SEP><SEP> Current <SEP> portion of the <SEP><SEP> pointer
<tb> Address <SEP> 3 <SEP> (Memory <SEP> POMER <SEP> Data <SEP> in <SEP> Memory <SEP> (designated <SEP> by <SEP> MPS)
<Tb>

<Desc / Clms Page number 16>

<Tb>
<tb> Window)
<tb> L / E <SEP> MPS <SEP> 16 <SEP> bits <SEP><SEP>SEP> selection <SEP><SEP> 16 <SEP><SEP><SEP> bit <7 <SEP> of
<tb> Address <SEP> 4 <SEP> (Memory <SEP> Pointer <SEP> Data <SEP> to <SEP> where <SEP> on <SEP> wishes to <SEP> access.
<Tb>

Selection)
<tb> L / E <SEP> SE <SEP> 16 <SEP> bits <SEP><SEP> Registry <SEP> communication <SEP> with <SEP>
<tb> Address <SEP> 5 <SEP> (Mapper / Enumerator <SEP> Cartographer / Enumerator <SEP> 25.
<Tb>

Register)
<tb> Implicit <SEP> 1 <SEP> bit <SEP> Bind <SEP> flag <SEP> when <SEP> of a <SEP> subtraction.
<Tb>

(Borrow)
<tb> Implicit <SEP> Unspecified <SEP><SEP><SEP> Pointer: <SEP> Specifies <SEP><SEP> Address of
<tb>(<SEP> Pointer) statement <SEP> The <SEP> next <SEP><SEP> statement to <SEP> execute.
<Tb>

Implicit <SEP> MP <SEP> Undefined <SEP><SEP> Pointer <SEP> Data <SEP>: <SEP> Specifies <SEP> the <SEP> address of
<tb> (Memory <SEP> Pointer) <SEP> base <SEP> for <SEP> access <SEP> to <SEP> data <SEP> in <SEP> memory.
<Tb>

Implicit <SEP> [PT <SEP> Undefined <SEP> Value <SEP> to <SEP> Copy <SEP> in <SEP> the <SEP> pointer
<tb> (Instruction <SEP> Pointer <SEP> Tank) <SEP> instructions. <SEP> When <SEP> IPW <SEP> is <SEP> accessed <SEP> in
<tb> write, <SEP> it is <SEP> IPT <SEP> which <SEP> receives <SEP> the <SEP> value. <SEP> IPT <SEP> is
<tb> copied <SEP> in <SEP> IP <SEP> on <SEP> access <SEP> in <SEP> write <SEP> to <SEP> IPW
<tb> when <SEP> IPS <SEP> is <SEP> equal <SEP> to <SEP> 0, <SEP> IPT <SEP> remaining <SEP> unchanged.
<Tb>

4. 3 - Common characteristics
The registers are addressed like any other location in the address space, under certain conditions. They cover the first addresses of the first page of the address space, called "page 0. The register R always constitutes the source operand or the destination operand of the instructions.

Depending on the amount of memory allocated to the zero level machine by the support machine 23, the instruction pointers (IP) and the data pointers (MP) can each take a specific maximum address. Each maximum address is represented by a number of significant bits called "addressing capability". This capacity, variable according to the available hardware environment, is expressed in number of bits and cut into portions of 16 bits, called windows.

If the addressing capacity is not multiple of 16, the accessible portion is enlarged to a multiple of 16 greater. The number of accessible windows is called the address width.

Thus, a level-level machine having an exploitable space ranging from 0 to 15,000,000 addresses has a 24-bit addressing capability, which will be addressed using 2 16-bit windows. IPS and MPS can therefore take the values 0 or).

In the case of level 0. 2, the instruction pointer (IP) addressing width is limited to a window. Therefore, only the instructions located in the first 64 Kmots can be executed.

<Desc / Clms Page number 17>

On remarque que l'on limite les tailles de IPS et MPS à 16 bits. Le bit de poids fort de ces registres est réservé. On peut donc adresser au maximum 32768 fenêtres de 16 bits Ce nombre permettrait l'accès à un nombre de cases mémoires bien supérieur au nombre estimé d'atomes de l'univers... Cependant, grâce au bit réservé, il serait malgré tout possible de définir une convention pour augmenter la taille de ces registres ! 5-Codage des instructions des processeurs Chaque instruction élémentaire des machines de niveau zéro a une taille fixe de 16 bits. La signification de ces différents bits varie entre le niveau 0.2 et le niveau 0.4. the address space. As a result, IPS is not accessible and considered to be always zero. In the previous example, only MPS can take the values 0 or 1.

Note that we limit the sizes of IPS and MPS to 16 bits. The most significant bit of these registers is reserved. We can therefore address a maximum of 32768 16-bit windows This number would allow access to a number of memory cells well above the estimated number of atoms in the universe ... However, thanks to the reserved bit, it would still be possible to define a convention to increase the size of these registers! 5-Coding of the instructions of the processors Each basic instruction of the machines of level zero has a fixed size of 16 bits. The meaning of these different bits varies between level 0.2 and level 0.4.

5. 1-Coding of level 0.2 instructions

<Tb>
<tb> 15 <SEP> 1 <SEP> bits <SEP> 13 ... <SEP> 0
<tb> home <SEP> op <SEP> mo
<tb> home <SEP>: <SEP> If <SEP> bit <SEP> to <SEP> a, <SEP> accesses <SEP> at <SEP><SEP> address pointed <SEP> by <SEP> MP <SEP>: <SEP> ae <SEP> = <SEP> address <SEP> effective <SEP> = <SEP> MP.
<Tb>

The <SEP> first <SEP> addresses <SEP> point <SEP> while <SEP> on <SEP> the space <SEP> address <SEP> and <SEP> no <SEP> on <SEP> the
<tb> regislres.
<Tb>

If <SEP> bit <SEP> null, <SEP> forces <SEP> access <SEP> to <SEP><SEP> page <SEP> 0 <SEP> into <SEP> ignoring <SEP> MP <SEP > but <SEP> in <SEP> using <SEP> the <SEP> field <SEP> mo <SEP>: <SEP> ae
<tb> = <SEP> mo
<tb> The <SEP> has <SEP> or <SEP> the <SEP> first <SEP> addresses <SEP> of <SEP> the <SEP> page <SEP> 0 <SEP> point <SEP> on <SEP > the <SEP> registers <SEP> intrenes <SEP> of <SEP> la
<tb> machine. <SEP> The <SEP> other <SEP><SEP> addresses point <SEP> on <SEP> the <SEP> address space.
<tb> op <SEP>: <SEP> Operation <SEP> Type <SEP>:
<tb> If <SEP> op <SEP> = <SEP> 0 <SEP> Subtract <SEP> with <SEP> hold <SEP> from ae <SEP> to <SEP> R <SEP>("SB<SEP> Mem "). <SEP> In <SEP> cases <SEP> of access <SEP> to <SEP> the <SEP> page
<tb> 0, <SEP> only <SEP> the <SEP> register "MER" 27 <SEP> (address <SEP> 0) <SEP> is <SEP> accessible.
<Tb>

If <SEP> op <SEP> = <SEP> 1 <SEP><SEP> Backup from <SEP> R <SEP> to <SEP> ae <SEP>("ST<SEP>Mem").<SEP> In <SEP> cases <SEP> of access <SEP> to <SEP> the <SEP> page <SEP> 0, <SEP> all <SEP>
<tb> registers <SEP> (addresses <SEP> 0 <SEP> to <SEP> 3) <SEP> are <SEP> accessible.
<tb> mo <SEP>: <SEP> Address <SEP> absolute <SEP> in <SEP><SEP> page <SEP> 0 <SEP> if <SEP><SEP> bit <SEP> home <SEP > is <SEP> dropped, <SEP> or <SEP> well <SEP><SEP> field of <SEP> bits
<tb> unexploited <SEP> if <SEP><SEP> bit <SEP> home <SEP> is <SEP> raised.
<Tb>

5. 2-Coding of Level 0.4 Instructions In level 0.4, an additional bit is used to encode two new instructions (LoaD and AND). As a result, there is one bit less to encode the "mo" field.

<Tb>
<tb> i5 <SEP> i4 <SEP>! <SEP> 3 <SEP> bits <SEP> 12 ... <SEP> 0
<tb> home <SEP> op <SEP> by <SEP> mo
<tb> home. <SEP> If <SEP> bit <SEP> to <SEP> a, <SEP> accesses <SEP> at <SEP> the <SEP> zone <SEP> where <SEP><SEP> base <SEP> is <SEP> dotted <SEP> with <SEP> MP <SEP>: <SEP> ae <SEP> - <SEP> effective <SEP>
<Tb>

<Desc / Clms Page number 18>

<Tb>
<tb> = <SEP> MP <SEP> AND <SEP> Logic <SEP> mo.
<Tb>

The <SEP> es <SEP> first <SEP><SEP> addresses point <SEP> ators <SEP> on <SEP><SEP> address space <SEP> and <SEP> No <SEP> on <SEP>
<tb> registers.
<Tb>

If <SEP> bit <SEP> null, <SEP> forces <SEP> access <SEP> to <SEP><SEP> page <SEP> 0 <SEP> into <SEP> ignoring <SEP> MP <SEP >: <SEP> ae <SEP> = <SEP> mo
<tb> The <SEP> has <SEP> or <SEP> the <SEP> first <SEP> addresses <SEP> of <SEP> the <SEP> page <SEP> 0 <SEP> point <SEP> on <SEP > the <SEP> registers <SEP> intenes <SEP> of <SEP> the
<tb> machine. <SEP> The <SEP> other <SEP><SEP> addresses point <SEP> on <SEP> the <SEP> address space.
<tb> op <SEP>: <SEP> Operation Type <SEP><SEP>:<SEP> 0 <SEP> = <SEP> Move <SEP> Memory, <SEP> 1 <SEP> = <SEP><SEP> arithmetic <SEP> or <SEP> logical operation
<tb> on <SEP> R.
<tb> by <SEP>: <SEP><SEP> setting of <SEP> operation
<tb> (by = <SEP> 0 <SEP>: <SEP><SEP> Backup from <SEP> R <SEP> to <SEP> ae <SEP>("ST<SEP>Mem").
<Tb>

If <SEP> op <SEP> = <SEP> 0 <SEP>
<tb> lpar <SEP> = <SEP> 1 <SEP>: <SEP> Loading <SEP> of <SEP> R <SEP> with <SEP><SEP> Content of ae <SEP>("LD<SEP> Mem ").
<Tb>

With <SEP> the <SEP> instructions <SEP> LD <SEP> and <SE> ST, <SEP> in <SEP><SEP> access cases <SEP> to <SEP><SEP> page <SEP > 0, <SEP> all <SEP> the <SEP> registers <SEP> (addresses
<tb> 0 <SEP> to <SEP> 5) <SEP> are <SEP> accessible.
<Tb>

(by <SEP> = <SEP> 0 <SEP>: <SEP> AND <SEP> logical <SEP> of the <SEP><SEP> content of ae <SEP> with <SEP> R <SEP>("AND<SEP> Mem ").
<Tb>

If <SEP> op <SEP> = <SEP> 1 <SEP> @
<tb> @par <SEP> = <SEP> 1 <SEP>: <SEP> Subtraction <SEP> with <SEP> hold <SEP> from ae <SEP> to <SEP> R <SEP>("SBB<SEP> Mem ").
<Tb>

With <SEP> the <SEP> statements <SEP> SBB <SEP> and <SEP> AND, <SEP> in <SEP><SEP> access cases <SEP> to <SEP><SEP> page <SEP > 0, <SEP> only <SEP> the <SEP> register <SEP> R
<tb> (address <SEP> 0) <SEP> is <SEP> accessible.
<tb> nb <SEP>: <SEP> the <SEP> flag of borrowing <SEP> B <SEP><SEP> can <SEP> be <SEP> accessed <SEP> only with <SEP><SEP><SEP> SBB <SEP> instructions and
<tb> AND.
<tb> mo <SEP>: <SEP> Address <SEP> absolute <SEP> in <SEP><SEP> page <SEP> 0 <SEP> if <SEP><SEP> bit <SEP> home <SEP > is <SEP> dropped, <SEP> or <SEP> well <SEP> mask <SEP> logical
<tb> combined <SEP> with <SEP><SEP> 13 <SEP> bits <SEP> of <SEP> weight <SEP> low <SEP> of <SEP> MP <SEP> for <SEP><SEP><SEP> calculation of <SEP> the <SEP> effective <SEP> address if
<tb><SEP> bit <SEP> home <SEP> is <SEP> raised.
<Tb>

6-Description of the instruction sets of the processors
It is observed that, by convention, the symbol (- designates the copy of the term situated on the right in the term on the left.) One speaks of "assignment of variable".

Le niveau 0. 2 se programme à l'aide de deux instructions : la soustraction et la sauvegarde du registre R vers l'espace d'adressage. 6. 1-Level Instruction Set 0.2

The level 0. 2 is programmed using two instructions: the subtraction and the saving of the register R towards the address space.

6. 1. 1 - The arithmetic operation

<Tb>
<tb> SB
<tb> Substract <SEP> with <SEP> Borrow-Subtraction <SEP> with <SEP> Loan
<tb> Syntax <SEP> SB <SEP> address
<Tb>

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<Tb>
<tb> Operation <SEP>: <SEP> R <SEP><-<SEP> (R-word <SEP> pointed <SEP> by <SEP> effective <SEP> address) -B, <SEP> B <SEP><-billing
<tb> Description <SEP>: <SEP> Subtract <SEP> from <SEP> register <SEP> R <SEP> the <SEP> word <SEP> located <SEP> to <SEP> the indicated <SEP> address <SEP> thus <SEP> than <SEP> the loan.
<Tb>

<SEP> state of <SEP> the <SEP> loan: <SEP> B <SEP> is <SEP> set <SEP> to <SEP> a <SEP> if <SEP> a <SEP> loan <SEP> is <SEP> generated, <SEP> it <SEP> is <SEP> set <SEP> to <SEP> zero <SEP> otherwise.
<Tb>

6. <SEP> 1. <SEP> 2 <SEP> - <SEP> The <SEP> operation of <SEP> move <SEP> memory
<tb> ST
<tb> STore-Backup <SEP> of <SEP> Registry <SEP> R
<tb> Syntax <SEP>: <SEP> ST <SEP> address
<tb> Operation <SEP>: <SEP> Word <SEP> Pointed <SEP> By <SEP> Actual <SEP> Address <SEP><-R
<tb> Description <SEP>: <SEP> Copy <SEP> to <SEP> the specified <SEP> address <SEP><SEP><SEP><SEP><SEP> R <SEP>< R <SEP> is <SEP> not <SEP> modified).
<Tb>

<SEP> state of <SEP> the <SEP> loan: <SEP> B <SEP> is <SEP> not <SEP> modified.
<Tb>

6. 2-Instruction Set of Level 0.4 Level 0.4 is programmed using four instructions: two to perform arithmetic and logic operations; two making it possible to move between the address space and the register R.

6. 2. 1-The memory displacement operations

<Tb>
<tb> ST
<tb> STore-Backup <SEP> of <SEP> Registry <SEP> R
<tb> Syntax <SEP>: <SEP> ST <SEP> address
<tb> Operation <SEP>: <SEP> Word <SEP> Pointed <SEP> By <SEP> Actual <SEP> Address <SEP><-R
<tb> Description <SEP>: <SEP> Copy <SEP> to <SEP> the specified <SEP> address <SEP><SEP><SEP><SEP><SEP> R <SEP>< R <SEP> is <SEP> not <SEP> modified).
<Tb>

<SEP> state of <SEP> the <SEP> loan: <SEP> B <SEP> is <SEP> not <SEP> modified.
<Tb>

LD
<tb> LoaD-Chargenieni <SEP> of the <SEP> register <SEP> R
<tb> Syntax <SEP>: <SEP> LD <SEP> address
<tb> Operation <SEP>: <SEP> R <SEP> e <SEP><SEP> word pointed <SEP> by <SEP> the effective <SEP> address
<tb> Description <SEP>: <SEP> Copy <SEP> in <SEP> The <SEP> Registry <SEP> R <SEP> The <SEP> Word <SEP> Located <SEP> to <SEP> Address <SEP> specified <SEP> (the <SEP> word <SEP> is <SEP> not <SEP> changed).
<Tb>

<SEP> state of <SEP> the <SEP> loan: <SEP> B <SEP> is <SEP> not <SEP> modified.
<Tb>
6.2. 2-Arithmetic and logical operations

<Tb>
<tb> AND
<tb> Logical <SEP> AND-AND <SEP> logical
<tb> Syntax <SEP>: <SEP> AND <SEP> address
<tb> Operation <SEP>: <SEP> R <SEP><-R<SEP> AND <SEP><SEP> word pointed <SEP> by <SEP> the effective <SEP> address, <SEP> buzz
<tb> Description <SEP>: <SEP> Perform <SEP><SEP> AND <SEP> Logic <SEP> Between <SEP><SEP> Registry <SEP> R <SEP> and <SEP><SEP> word <SEP> located <SEP> to <SEP> the <SEP> address specified <SEP> The <SEP> result
<tb> is <SEP> ordered <SEP> in <SEP> R.
<Tb>

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<Tb>
<Tb>

<SEP> state of <SEP> the <SEP> loan: <SEP> B <SEP> is <SEP> always <SEP> set <SEP> to <SEP> zero.
<tb> SBB
<tb> SuBstract <SEP> with <SEP> Borrow-Subtraction <SEP> with <SEP> Loan
<tb> Syntax <SEP>: <SEP> SBB <SEP> address
<tb> Operation <SEP>: <SEP> R <SEP><-<SEP> (R-word <SEP> pointed <SEP> by <SEP> effective <SEP> address) -B <SEP>;<SEP> B <SEP><-billing
<tb> Description <SEP>: <SEP> Subtract <SEP> from <SEP> register <SEP> R <SEP> the <SEP> word <SEP> located <SEP> to <SEP> the indicated <SEP> address <SEP> thus <SEP> than <SEP> the loan.
<Tb>

<SEP> state of <SEP> the <SEP> loan: <SEP> B <SEP> is <SEP> set <SEP> to <SEP> a <SEP> if <SEP> a <SEP> loan <SEP> is <SEP> generated, <SEP> it <SEP> is <SEP> set <SEP> to <SEP> zero <SEP> otherwise.
<Tb>

par MP. Ils existent dans le niveau 0. 2 et le niveau 0. 4, mais leur fonctionnement diffère dans certains cas particuliers. 6. 3-Addressing modes The value of the home bit (see section 5) defines two addressing modes. By "addressing mode" we mean a way of calculating the address on which an operation (effective address) is carried. These addressing modes are the absolute mode page 0 and the indexed absolute mode

by MP. They exist in level 0. 2 and level 0. 4, but their operation differs in certain particular cases.

6. 3. 1-The absolute mode page 0 In this mode, the effective address is calculated from the least significant bits of the instruction (field mo), allowing access to the addressable registers of the machine, as well as to the first words of the address space of the machine (after the registers).

In level 0. 2, the mo field making 14 bits, it is possible to access the first 16384 addresses of the machine. In level 0.4, since the mo field is only 13 bits, only the first 8192 addresses of the machine can be accessed.

la forme d'un numéro compris entre 0 et 8191 pour le niveau 0. 4 (entre 0 et 16383 pour le niveau
0. 2). We notice that, in assembly language, the "address" field of the instruction is expressed under

the form of a number between 0 and 8191 for the level 0. 4 (between 0 and 16383 for the level
0. 2).

 6.3. 2-Absolute mode indexed by MP This mode of addressing allows access to the entire addressable space (including the first words of the address space, inaccessible in absolute mode page 0, since hidden by addressable registers). Its operation differs between level 0. 2 and level 0. 4.

In level 0.4, the effective address is the result of the logical AND between the MP register and the 13 least significant bits of the instruction (on the 13 low-order bits of MP).

In the assembly language, the "address" field of the statement is then expressed as a number between 0 and 8t9), preceded by the character '&' (example: & $ 10 for the address resulting from the operation "logical AND logic 6").

In level 0. 2, the effective address is that contained in the register MP. In assembly language, the field "address" of the instruction then contains the character "&" only. The field "mo" of the instruction is ignored, and its content is indeterminate.

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 7 - The exception and the interruption The exception (and the interruption at level 0.4) are mechanisms that baffle the sequential execution of programs under certain conditions.

Appel au sous-programme de réinitialisation du cartographe/énumérateur 25. 7. 1 - The exception 7. 1. 1 - The exception in level 0.2 The exception is as follows:

Call to the map / enumerator reset routine 25.

MPS O MPO 1 P ± $ 2000 When the machine is first started, the exception is immediately triggered (all registers 0. 2 contain any values before it is executed).

Appel au sous-programme de réinitialisation du cartographe/énumérateur 25. In addition to starting, the cause of an exception is loading! P or ZD ZD MP with an invalid address, the loading of MPS with a window number greater than the t> width of addressing, or an illegal operation on the register "MER" 27. t, z: l C> 7. 1. 2-The exception in level 0.4 The exception is as follows:

Call to the map / enumerator reset routine 25.

IPS < -0 IPT PT $10000 IP < - IPT Lors du premier démarrage de la machine, l'exception est immédiatement déclenchée (tous les registres 0.4 contiennent des valeurs quelconques avant son exécution). CI addresses 0 # 16 low-order bits of IP at the time of exception MPS <-0 MP # 0

IPS <-0 IPT PT $ 10000 IP <- IPT When the machine is first started, the exception is immediately triggered (all 0.4 registers contain any values before it is executed).

 In addition to starting, the cause of an exception is loading IP or MP with an invalid address, loading MPS or IPS with a window number greater than the addressing width of MP and IP, or an IP address. Illegal operation on the "MER" register 27.

7. 2-The interruption 7.2. 1 - The interrupt at level 0.2 The "interrupt" mechanism at level 0.2 does not interrupt the sequential execution of instructions. So it's up to the program written in level 0.2 to check regularly with the

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 Cartographer / Enumerator 25 the presence of an interruption (usual technique called scanning or "polling").

7.2. 2-Interrupting at Level 0.4 The interruption at level 0.4 is triggered on command of a program 0.4 provided that the mapmaker / enumerator 25 has been requested by a request from a device 32.

If an interrupt is pending during the command, the mechanism is as follows: address 0 <-] 6 least significant bits of the address of the instruction following the instruction that triggered the interruption ("LD MER") .

I PT (- 1 IP IPIPT If not, the sequential execution of the instructions is not broken.

7. 3. 1 - Le programme de démarrage de niveau 0. 2 Z :- > ICI Ce programme est appelé immédiatement après le déclenchement d'une exception et prend en charge la machine 20 de niveau 0. 2. Il débute obligatoirement à l'adresse $2000. C'est une z succession de codes d'instructions 0.2 et de mots de données qui peuvent contenir n'importe quel programme de taille quelconque (dans la limite de la deuxième page). 7. 3-The startup programs

7. 3. 1 - The level 0 start program. 2 Z: -> HERE This program is called immediately after an exception is thrown and supports the level 20 machine. 2. It must start at the next level. $ 2000 address. This is a succession of instruction codes 0.2 and data words that can contain any program of any size (within the limit of the second page).

The level 0.2 boot program contains the complete Level 0.4 emulator 24 (approximately 2K in size). This program could be implemented in a ROM (or EEPROM) with a real machine of level 0.2.

7.3. 2-The Level 0.4 Startup Program This program is called immediately after an exception is thrown and supports the level 0.4 machine. It must start at $ 10000 (beginning of the second segment). It is a succession of instruction codes 0.4 and data words that can contain any program of any size.

The 0.4 level boot program will contain the full emulator at the top level (Level 30 machine), or any other program.

8-Operating Algorithms of Zero Level Emulators It is recalled that all operations are performed on 16 bits exclusively. Values are interpreted as a complement to two. Example: $ 000 - $ 0001 = $ FFFF, and the loan is set to 1.

By convention, the term "jump" denotes a sequence break without automatic return. The term "call" refers to a sequence break with systematic return to the instruction following the call instruction, after execution of the subroutine instructions.

8. 1-Algorithm of the emulator 22 of the level 0.2 processor.

 8.).) - Initialization:

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Reservation of the necessary memory. At least a few words for the machine's registers and the program (s) to be executed.

Copy of the x words that make up the startup program from the $ 2000 address. This Z:>t> program contains the emulator 24 of the entire level 0.4 in the implementation performed by the inventors.

Saut à l'exception (voir paragraphe 7.).)) z Lecture dans IP de l'adresse de l'instruction à exécuter Lecture de l'instruction 16 bits IP < -IP+I (addition effectuée sur les 16 bits du registre) Si bit home = 1 alors ae = MP saut au traitement générique des instructions Sinon mo = bits 0 à 13 de l'instruction (14 bits de poids faible) Si bitop = 0 Si mo = 0 Appel au sous-programme de lecture du cartographe/énumérateur 25 R < - (R-MER)-B B 1 si un emprunt est généré, sinon B < -0 Saut au Noyau Sinon ae = mo Saut au traitement générique. Call to the cartographer / enumerator initiator routine 25 z: l Jump to exception (see paragraph 7. 1. 1) ZD 8.1.2 - Core: If IP points to an invalid address

Jump to exception (see section 7.).)) Z Reading in IP of the address of the instruction to be executed Reading of the instruction 16 bits IP <-IP + I (addition made on the 16 bits of the register ) If bit home = 1 then ae = MP jump to the generic processing of the instructions Otherwise mo = bits 0 to 13 of the instruction (14 bits of low weight) If bitop = 0 If mo = 0 Call to the subroutine for reading cartographer / enumerator 25 R <- (R-MER) -BB 1 if a loan is generated, otherwise B <-0 Jump to Kernel Else ae = mo Jump to generic processing.

MER e R Appel au sous-programme d'écriture du cartographe/énumérateur 25 Saut au Noyau Sinon si mo = 1 ae = adresse des 16 bits de MP sélectionnés par MPS (dans l'espace d'adressage de la machine support 23) mot pointé par ae v R Otherwise if mo = 0

MER e R Call to Cartographer / Enumerator Write Routine 25 Jump to Kernel Else if mo = 1 ae = address of 16 MP bits selected by MPS (in address space of support machine 23) word pointed by ae v R

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Saut à l'exception (voir paragraphe 7. 1. 1) Z-1 Sinon MPS # R Saut au Noyau Sinon ae = mo

Saut au traitement générique. If MP points to an invalid address Jump to Exception (see section 7. 1. 1 Otherwise Jump to Kernel Else if mo = 2 IP FR Jump to Kernel Else if mo = 3 If R is greater than the addressing width

Jump to exception (see paragraph 7. 1. 1) Z-1 Otherwise MPS # R Jump to the kernel Otherwise ae = mo

Jump to generic treatment.

1 8. 1. 3-Generic processing of instructions:
In the following, "[ae]" means the word pointed to by ae.

If op bit = 0 R z (R- [ae]) - B B! if a loan is generated, otherwise B <-0 zz, Else [ae] <-R Jump to Kernel 8. 2 - Algorithm of the emulator 24 of the level 0.4 processor 8.2. 1-Initialization: Reservation of the necessary memory. At least a few words for the machine's registers and the program (s) to be executed.

Copy the x words that make up the startup program from the $ 10000 address. This program will contain the emulator of the higher level (level 1 machine) in the implementation carried out by the inventors.

Call to the Mapper / Enumerator Initialization Routine 25 Jump to Exception (see paragraph 7. 1. 2) 8.2. 2-Core: If IP points to an invalid address Jump to exception (see section 7. 1. 2)

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ae = (MP ET logique emo) ZD Saut au traitement générique des instructions Sinon

Si bit op = 0 Si mo = 0 RR < " Saut au Noyau Sinon si mo = 1 Si bit par = 0 ae = adresse des 16 bits de IPT sélectionnés par IPS (dans l'espace d'adressage de la machine ZD support 23) mot pointé par ae < -R Si IPS = 0 Si IPT pointe sur une adresse invalide Saut à l'exception (voir paragraphe 7. 1. 2) Sinon IP # IPT Saut au Noyau Sinon R # 16 bits de IP sélectionnés par IPS Saut au Noyau Sinon si mo = 2 Si bit par = 0 Si R est supérieur à la largeur d'adressage de IP Saut à l'exception (voir paragraphe 7. 1. 2) Sinon IPS v R Saut au Noyau Sinon R v IPS Saut au Noyau Reading in IP of the address of the instruction to be executed Reading of the instruction 16 bits IP # IP + 1 (addition done on its 16 bits of least significant weight) mo = bits 0 to 12 of the instruction (13 bits low weight) If home bit = 1 emo = extension by 1-bit bits of mo to MP addressing capability

ae = (MP AND logical emo) ZD Skip to Generic Processing of Instructions Otherwise

If bit op = 0 If mo = 0 RR <"Jump to the kernel Else if mo = 1 If bit by = 0 ae = address of the 16 bits of IPT selected by IPS (in the address space of the machine ZD support 23 ) word pointed to by ae <-R If IPS = 0 If IPT points to invalid address Jump to exception (see section 7. 1. 2) Otherwise IP # IPT Jump to Kernel Else R # 16 bits of IP selected by IPS Jump to the kernel Else if mo = 2 If bit by = 0 If R is greater than the IP address width Jump to exception (see section 7. 1. 2) Otherwise IPS v R Jump to Core If not R v IPS Jump to the Core

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Saut à l'exception (voir paragraphe 7. 1. 2) ZD Sinon Saut au Noyau Sinon R 16 bits de MP sélectionnés par MPS Saut au Noyau Sinon si ma = 4 Si bit par = 0 Si R est supérieur à la largeur d'adressage de MP

Saut à l'exception (voir paragraphe 7. 1. 2) tD Sinon MPS f-- R Saut au Noyau Sinon R < -MPS Saut au Noyau Sinon si mo = 5 Si bit par = 0 MER # R Appel au sous-programme d'écriture du cartographe/énumérateur 25 Saut au Noyau Sinon Appel au sous-programme de lecture du cartographe/énumérateur 25 R # MER Saut au Noyau Sinon ae = mo Saut au traitement générique. Otherwise if mo = 3 If bit by = 0 ae = address of the 16 bits of MP selected by MPS (in the address space of the support machine 23) word pointed by ae # R If MP points to an invalid address

Jump to exception (see section 7. 1. 2) ZD Else Jump to Kernel Else R 16 bits of MP selected by MPS Jump to Kernel Else if ma = 4 If bit by = 0 If R is greater than the width of MP addressing

Exception (see section 7. 1. 2) tD Else MPS f-- R Jump to Core If R <-MPS Jump to Core If mo = 5 If bit par = 0 MER # R Call subroutine Cartographer / Enumerator 25 Jump to Kernel Else Call to Cartographer / Enumerator Read Routine 25 R # MER Jump to Kernel Else ae = mo Jump to generic processing.

Otherwise if mo = 0

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Rf- (R ET logique R) (1) 80 Saut au Noyau Sinon R < - (R-R)-B B # 1 si un emprunt est généré, sinon B # (2) Saut au Noyau Sinon ae = mo Saut au traitement générique. If bit by = 0

Rf- (R AND logic R) (1) 80 Jump to Kernel Otherwise R <- (RR) -BB # 1 if a loan is generated, otherwise B # (2) Jump to Kernel Else ae = mo Jump to generic processing.

[ae] < -R Sinon R # [ae] Sinon Si bit par = 0 R < - (R ET logique [ae])

B v 0 Sinon Sinon R- (R- [ae])-B B f- 1 si un emprunt est généré, sinon B # 0 Saut au Noyau Les renvois (1) et (2) concernent : (1) Cette opération n'a aucun effet, et peut donc être supprimée si besoin. 8. 2.3 - Generic processing of instructions: Sibitop = 0 If bit par = 0

[ae] <-R Otherwise R # [ae] Else If bit by = 0 R <- (R AND logic [ae])

B v 0 Else Otherwise R- (R- [ae]) - BB f- 1 if a loan is generated, otherwise B # 0 Skip to the kernel The references (1) and (2) concern: (1) This operation does not has no effect, and can be deleted if necessary.

(2) This operation and the previous one can be summarized by the operation: R # 0 - B Second aspect of the present invention.

9-Theoretical aspects 9.1 - Important concepts 9. 1. 1 - Concept of device 9. 1. 1. 1 - Definition of a device

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 A processor is a machine designed to process data. For its operation to be useful, it must be able to receive data and / or send the results of its calculations where they will have an appropriate effect.

éventuellement une conversion de l'information échangée. "Devices" are everything outside the processor. They make available to the latter data and / or collect the result of its calculations, by operating

possibly a conversion of the information exchanged.

CD With the integration of electronic components, it is frequently found that several Zn functions are provided by what is commonly called "a device" for the processor. Thus, an electronic card managing a keyboard can also handle a ZD joystick game and a mouse. The problem is that we confuse the place where the functions are provided (the electronic card) and their purposes (manage a keyboard, manage a mouse, etc.). In this example, we consider that the keyboard, the mouse, and the joystick are all different devices.

So we will talk about three devices, despite the fact that they are managed by the same card. tD C> 9. 1. 1. 2 - Function, configurations, and homogeneity tD Each device has a set of characteristics that perform a single homogeneous function, for which it was designed, called a function. All elements that participate in this ZD function are considered to belong to the same device. The function therefore defines the unit of the device. The characteristics of this function can be set according to a number of configurations.

The appreciation of the limit for defining the homogeneity of a function is sometimes difficult and subjective. For example, the keyboard of a computer can be considered as a tool for transcribing cultural data composed of letters, but whose meaning only appears when they are assembled into words. In this respect, a single letter does not make sense, so the entire keyboard must be represented as a single device. On the other hand, if the keyboard is considered as a set of buttons each conveying a symbolically independent information, then each key can be presented as a device in its own right.

To evaluate the homogeneity of the function provided by a device, we must therefore study: the utility and the purpose of the device (eg a mouse essentially allows a continuous spatial movement, a keyboard occasionally gives symbolic information). the dependence of the information processed by the device to ensure its function (ex: you can manipulate the mouse, without affecting the state of the keyboard, and vice versa).

It is important to be wary of the geographical proximity of the different components of a device. For example, a keyboard and a mouse are usually placed side by side, but they should not be considered as a single device. Conversely, a steering wheel for video games.

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accompagné de pédales sont considérés comme un seul périphérique, bien que le volant soit souvent assez éloigné géographiquement des pédales pour des raisons ergonomiques. tl > 9. 1. 1. 3 - Unités algorithmiques et non algorithmiques z : l ZD Tout périphérique dispose de procédés techniques traitant l'information sous forme de signaux (électriques, lumineux, sonores,...). On considère ces procédés comme rassemblés en"unités fonctionnelles". Une unité fonctionnelle manipule et transforme les signaux selon son domaine de compétence. L'ensemble des unités fonctionnelles assure ainsi la fonction pour laquelle le périphérique est conçu. On ne s'intéresse pas au détail des procédés techniques sous-jacents à une unité fonctionnelle, mais à la fonction de transformation du signal qu'elle réalise.

with pedals are considered as a single device, although the steering wheel is often geographically far enough away from the pedals for ergonomic reasons. tl> 9. 1. 1. 3 - Algorithmic and non-algorithmic units z: l ZD Any device has technical processes that process information in the form of signals (electrical, light, sound, etc.). These processes are considered as grouped into "functional units". A functional unit manipulates and transforms signals according to its area of competence. The set of functional units thus ensures the function for which the device is designed. We are not interested in the detail of the technical processes underlying a functional unit, but in the signal transformation function that it performs.

For example, a sound card may include a digital-to-analog converter, a clock, a wave generator oscillator, an adjustable amplifier, a signal processor, and so on. Each of these elements is a functional unit participating in the function of the device.

- les "unités algorithmiques" dont la fonction de transformation digitale peut être reproduite C > C > entièrement et de façon identique par logiciel (ou de façon satisfaisante pour une fonction de transformation analogique), et

- les "unités non algorithmiques" qui réalisent une fonction de transformation du signal ZD impossible à reproduire par logiciel. We classify functional units into two categories:

- "algorithmic units" whose digital transformation function can be reproduced C>C> entirely and identically by software (or satisfactorily for an analog transformation function), and

the "non-algorithmic units" which perform a function of transformation of the signal ZD impossible to reproduce by software.

seulement des unités algorithmiques ne sont pas gérés par la machine de niveau zéro. Par ZD exemple, un coprocesseur arithmétique fonctionne uniquement avec des unités algorithmiques : il ne sera donc pas géré par la machine de niveau zéro puisque cette dernière peut reproduire totalement son comportement par programme. Parfois, l'accès direct à une unité non algorithmique est impossible sans passer par une unité algorithmique. Dans ce seul cas, la machine de niveau zéro doit gérer les unités algorithmiques permettant d'accéder aux unités non algorithmiques. Depending on the devices you will find one or the other or both categories of units. The programming interface of the device generally makes it possible to exploit all the available units, but the machine of level zero takes into consideration only the non-algorithmic units, insofar as this machine is able to ensure the operations pertaining to the algorithmic units by herself. Thus the data transformation devices using

only algorithmic units are not supported by the zero level machine. By ZD example, an arithmetic coprocessor only works with algorithmic units: it will not be managed by the zero level machine since it can fully reproduce its behavior programmatically. Sometimes, direct access to a non-algorithmic unit is impossible without going through an algorithmic unit. In this case alone, the zero-level machine must manage algorithmic units to access non-algorithmic units.

In the case of the example, the wave generator oscillator, the amplifier and the signal processing processor are algorithmic units because their behavior can be faithfully reproduced by a written program for the zero level processor.

9. 1. 1. 4-Private and public peripherals

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 Among the devices, we distinguish the "private" devices which only the processor can access for reading and / or writing. This is the case of RAM, ROM and any non-shared related memory. Note that some functional units of a device may still be accessed by other functional units of the same device to ensure its proper operation. This is the case, for example, for maintaining the information over time in a DRAM, but such access is not taken into account in the definition stated above. In all other cases, we are talking about "public" device.

When we talk about devices in this document, we include private and public devices.

 9. 1. 2-Time Machine and Machine Sequence A real processor is a machine based on the Von Neumann model that executes its operations sequentially. The execution of each step of the sequence requires a certain time. The "real time" of a sequence of instructions is generally defined as the real, continuous time required for its execution.

The virtual processor is also a machine based on the Von Neumann model that executes its operations sequentially. The time taken by the execution of a sequence is impossible to evaluate precisely, since the function of the support machine 23. Thus, for the virtual processor, we no longer speak of machine time, but of machine sequence, corresponding to a discrete time , clocked by each instruction, whose equivalence in physical continuous time is considered as non-existent. A program can still take a very rough look at the time thanks to this sequentiality, but it must never try to evaluate the flow of real time from the duration of a sequence of instructions.

9. 1. 3-Types of data exchanged with peripherals We distinguish two categories of data exchanged with a device: - the first refers to the result already processed or to be processed by its functional units ("operating data"), and - the second allows to configure its functional units, ie how they will handle the flow of data ("configuration data"). The configuration data may not exist in the case of a device with predefined and invariable behavior (eg analog-to-digital converter, ROM, ...).

9.1. 4-Programming a Device from a Processor A processor transmits and / or receives data from a device using particular signals. We are interested here in how to trigger this communication processor / device, that is to say "the programming interface", and not the detail of the electronic signals exchanged. This transmission can be done automatically on request of a

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 device, but usually it will be at the initiative of the processor. We are aware of two ways to access devices from a processor: - some portions of the address space are specialized for devices. A portion corresponds to a particular device. It suffices to execute the processor an instruction that accesses that portion of the address space to establish communication with the desired device. There is therefore a plan of memory organization (memory map). This convention is for example that adopted on Motorola 680x0 processors, - the processor has some instructions reserved for access to public devices, all other instructions are exclusively reserved for private devices (except the mass memories). There are therefore two distinct address spaces. As soon as the processor executes an instruction, it will establish communication with the public or private device concerned. This convention is the one adopted by default by Intel 80x86 processors.

espace d'adressage pour l'accès à tous les périphériques. Cependant, elle complique la ZD conception d'un ordinateur et d'un émulateur. La seconde méthode oblige à ajouter des instructions supplémentaires. The first method avoids adding instructions to the processor, and it just a single

Address space for access to all devices. However, it complicates the ZD design of a computer and an emulator. The second method requires adding additional instructions.

We chose the first method to access certain data from private devices for reasons of speed and ease of use. The management of other data is based on a single addressable register of zero-level machines. We consider that a processor can only do one thing at a time, so viewing the devices through a single registry does not pose a problem of the "bottleneck" type. If several accesses are to be done at the same time, it is necessary to use several processors operating in parallel.

9. 2-Theoretical modeling of peripherals.

From a theoretical point of view, the description of the devices aims essentially to represent uniformly the information necessary to exploit them and to facilitate the replacement of one of them by another, automatically. This description can be supplemented by ancillary information, in particular the actual modeling data, which makes it possible to precisely express the interactions between the device and its environment, using the classical tools of the Sciences.

We first seek to know, from a basic point of view, the way in which a device to be modeled apprehends its real and computer environments: it is the microscopic analysis. The second step, called macroscopic analysis, consists of organizing information to program the device (computing environment) according to a structure reflecting the device's relationship with the real world (real environment). This structure is based on a dimensional mathematical model, inspired by linear algebra.

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These analyzes are performed independently for each configuration of the function of a device. During the implementation, the different models obtained will be gathered in a single structure defining the function.

It is thus possible to model exhaustively any function of any peripheral, within the meaning of the definitions stated above.

9. 2. 1-Microscopic Structure of Devices A device seen in the broadest sense has a number of properties that distinguish it from other objects in the real world. These properties may or may not be related to the function of the device. Thus, the fact that a screen produces an image of a certain quality or that its carcass is translucent are two properties, one in relation to its function, the other not. The properties that interest us are those related to the function of the device, and resulting from the operation of the non-algorithmic units composing the device: these are the functional properties.

The functional properties result in one or more physical or symbolic phenomena (for example: the pixels of a screen) which can be a complex mixture of elementary phenomena (example: color, luminous intensity, and space portion constituting a pixel of a pixel). screen), or a single elementary phenomenon (light intensity of a light-emitting diode, sound amplitude produced by a loudspeaker, space portion, alphabetical letter, etc.).

The evaluation of the microscopic structure of a device is done from two points of view: the programmer's point of view, and the perspective of the device's environment.

From the programmer's point of view, we try to gather all the operating data into one or more exclusive sets. The collection of operating data into an exclusive set occurs when the choice of one of these data excludes all others from the expression of the function. In addition, an exclusive set is a basic source of information.

From an environmental point of view, we want to know which elementary phenomenon (s) represent (s) each exclusive set in reality. Each of these elementary phenomena or group of elementary phenomena is called phenomenal characteristic. Among the elementary phenomena of a phenomenal characteristic, one and only one is directly and completely modulated by the elementary information: it is the modulated characteristic.

We notice that we analyze the function of a device with a certain precision: the one with which the function is expressed. We therefore try to model the function of the device to the scale corresponding to it best. In this view, the elementary phenomena that participate marginally in the expression of the function (that is to say on a different scale) are

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 ignored for the microscopic structure. However, these marginal phenomena may be taken into account in the definition of the actual modeling data.

Through a selection process, the elementary phenomena of a phenomenal feature will be sorted into groups for the macroscopic description of the device. A group is called a basic characteristic.

peuvent engendrer des modèles non canoniques, qui bien que conformes aux règles que nous rD allons énoncer, ne permettront pas d'exploiter toutes les ressources des périphériques. Pour réduire au maximum ces risques d'erreur d'appréciation il est donc nécessaire, avant même de tenter de modéliser un quelconque périphérique, de se documenter sur son fonctionnement. The evaluation of exclusive sets and phenomenal features is a specialist job. Each can evaluate them differently, according to their perception and their understanding of the functioning of a peripheral (programming interface, functional units, functional properties, phenomena). The specialist must be aware that these differences of opinion

may result in non-canonical models, which, while compliant with the rules we will be stating, will not exploit all the resources of the devices. To minimize these risks of error of appreciation it is necessary, even before attempting to model any device, to document its operation.

9.2. 2-Macroscopic structure of the devices The modeling presented here is matrix because most current peripherals work according to a matrix model.

A set of elementary characteristics is represented by a dimension in the mathematical sense of the term. We speak of "dimension". The combination of all "dimensions" forms a space, in the mathematical sense of the term, in which the function of the device can be completely modeled. We are talking about "space" of device.

The "dimensions" make it possible to synthetically distinguish all the physical or symbolic phenomena governing the relationship of the device with its real environment. It is thus possible to determine a profile of the environmental parameters with which the device is able to interact.

For example, we consider a device modeled by three "dimensions". The assembly forms the space of the device, and FIG. 1 represents a device "space" with three "dimensions" D1, D2 and D3.

An elementary feature is represented on a "dimension" by a "coordinate".

In the example, the third "dimension" gathers four "coordinates" CI to C4 illustrated in FIG.

The set of "coordinates" of certain "dimensions" can express an elementary phenomenon of their elementary characteristic (the "modulated characteristic") with a certain intensity among a set of possible intensities. We speak of "intensity" of a "coordinate".

The choice of an "intensity" among all the "intensities" available for a "coordinate" of a space point "of a peripheral systematically excludes all other" intensities "of this same" coordinate " .

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Dans l'exemple, les"coordonnées"de la troisième"dimension"sont programmables grâce aux paramètres d'''intensité''. Les "coordonnées" des autres "dimensions" n'ont pas d"'intensités".

In the example, the "coordinates" of the third "dimension" are programmable through the "intensity" parameters. The "coordinates" of the other "dimensions" do not have "intensities".

The theoretical modeling of a device can be symbolized by a geometric figure illustrated in FIG. 1, in a n-dimensional space (three dimensions in FIG. 1), where n is the number of "dimensions" of the device.

9.2. 3-Method of construction of the macroscopic model The macroscopic model is constructed from microscopic analysis. The construction method is presented as a series of sequential steps to obtain a valid macroscopic model.

9. 2. 3. 1 - initial step: We consider that no "dimension", "coordinate" or "intensity" is defined. Each of the exclusive sets is associated with a set of "intensities" attached to a new "coordinate". The phenomenal feature associated with the exclusive set is associated with this new "coordinate." For an exclusive set, each "intensity" represents a distinct operating datum. The set of "coordinates" is grouped within a single "dimension".

9.2. 3. 2.-Iterative step: For each existing "dimension" (called "mother dimension"): One tries to gather all its "coordinates" in one or several group (s). a) In the case of a grouping in at least two groups: For each group, several (or only) elementary phenomena may be present identically in each "coordinate" of the group. These (or this) elementary phenomena are called intra-group characteristic.

Among the possible elementary phenomena that do not belong to the intragroup characteristics, those (or that) present identically in a coordinate of each of the groups are called inter-group characteristic. An elementary phenomenon can only participate in one inter-group characteristic. It is noted that a "coordinate" can therefore be associated with an intra-group characteristic and a maximum inter-group characteristic.

The collection of "coordinates" in "groups" must respect the following rules: Each "group" must have the same number of "coordinates".

It is forbidden to create groups consisting of a single "coordinate".

* There must be no elementary phenomenon that does not belong to either an intragroup characteristic or an intergroup characteristic.

At least two "coordinates" of the "mother dimension" must have at least one elementary phenomenon. b) In the case of a rally in a single group:

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 Several (or only) elementary phenomena can be present identically in each "coordinate" of the group. These (or this) elementary phenomena are called intra-group characteristic.

For each "coordinate", an inter-group characteristic brings together the possible elementary phenomena that do not belong to the intra-group characteristic.

The collection of "coordinates" in the group must respect the following rules: The "parent dimension" must contain at least two "coordinates".

All "coordinates" must contain "intensities".

The modulated characteristic of each "coordinate" must be part of the intragroup characteristic.

In both cases, the non respect of at least one rule prohibits the gathering of the "coordinates" in group (s). The "dimension" then becomes definitively established.

If it is possible to form groups according to these rules, then two new "dimensions" ZD are created: A "dimension" having a number of "coordinates" equal to the number of "coordinates" of a group of the "master dimension" ". The phenomenal characteristics of the "coordinates" of this new "dimension" are those of any group of the "mother dimension", from which the intra-group characteristic has been removed.

 A "dimension" having a number of "coordinates" equal to the number of groups of the "mother dimension". Each of these groups generates a "coordinate" of the new "dimension". The intra-group characteristic of each of these groups is the phenomenal characteristic of the generated "coordinate".

An "intensity" is always linked to the "coordinate" that contains the modulated characteristic, and therefore to the "dimension" that contains this "coordinate".

Once all the "dimensions" have been processed, if it has not been possible to create groups on at least one of the "dimensions", then the construction of the model is complete. The "dimensions" produced by the algorithm are grouped within the "space" of the device, and if the generated model seems incorrect, then the microscopic structure may need to be reviewed.

Otherwise the process starts again at the iterative stage.

Figure 2 summarizes the entire modeling process of a device.

9. 2. 4-Example of theoretical modeling of a device 9.2. 4. 1-Definition of the device Let's take the example of a graphic card and its associated color screen. The purpose of the set is to display a succession of color images. Note that a graphics card without screen is of no use since it can not express its information, and a single screen is unable to display an image if it is not controlled by a graphics card.

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 This is why the set is considered as a single homogeneous function device Moreover, the device is public since the information expressed by the screen can be known by other receivers than the processor (example: the user).

9.2. 4. 2-Function and Device Configurations
The purpose of this peripheral is to regularly convert digital information into analogue light signals assembled in a matrix to form a succession of images perceived as colored by a human being.

 This device is capable of displaying a matrix of 320 pixels horizontally by 200 pixels vertically, each pixel having a color defined by a red level, a green level and a blue level. On the other hand, it allows to display a matrix of 640 by 400 pixels, each pixel having a color selected from the same palette of 256 distinct colors. Each of these 256 colors is defined by a red level, a green level, and a blue level. This device can therefore operate in two different configurations (Figure 3). In all cases, the pixel matrix is updated every fiftieth of a second.

 In this example, the curvature of the display surface of the cathode ray tube is ignored because it does not significantly contribute to the display of a two-dimensional image. The tube is therefore considered flat. Similarly, the successive display of the points constituting an image is considered as simultaneous because the image resulting from this display is intended to be perceived as a whole by the user. However, these marginal phenomena may be taken into account in the definition of the actual modeling data.

9.2. 4. 3-Functional Unit Study The device's technical processes process digital data to transform it into light information. This treatment differs slightly depending on the configuration, and we refer to the technical documentation of the device to study it: - In the configuration 320 by 200 pixels, the values of red, green and blue of each pixel are saved in memory some after the others, each on one byte. The lines are then described successively (from top to bottom), presenting for each the values of red, green and blue pixels located from the smallest abscissa (x = 1) to the largest abscissa (x = 320). This description is read every fiftieth of a second to be redisplayed on the screen. The description in memory can be summarized as follows:

<Tb>
<tb> x = 1 <SEP> x = 2 <SEP> x = 319 <SEP> x = 320 <SEP> x = 1 <SEP> x = 2 <SEP> x = 320
<tb> y = 1 <SEP> y = 1 <SEP> y = 1 <SEP> y = 1 <SEP> y = 2 <SEP> y = 2 <SEP> y = 2
### > R <SEP> V <SEP> B <SEP> R <SEP> V <SEP> B <SEP> R <SEP> V
<Tb>
This description in memory is reflected on the screen by pixels composed of red spots. green, and blue. These pixels are organized as follows.

<Tb>
<tb> x = 1 <SEP> x = 2 <SEP> x = 3 <SEP> x = 318 <SEP> x = 319 <SEP> x = 320
<Tb>

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<Tb>
<tb> y = 1 <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB
<tb> y = 2 <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB
<tb> y = 3 <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB
<tb> y = 198 <SEP> RGB <SEP> RGB <SEP> RGB <SEP> ... <SEP> RGB <SEP> RGB <SEP> RGB
<tb> y = 199 <SEP> RGB <SEP> RGB <SEP> RGB <SEP> ... <SEP> RGB <SEP> RGB <SEP> RGB
<tb> y = 200 <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB <SEP> RGB
<Tb>
In the configuration 640 by 400 pixels, the color numbers (N) are stored in memory one after the other, each corresponding to one pixel. Each number is saved on one byte. The lines are then described successively (from top to bottom), presenting for each the color numbers of the pixels located from the smallest abscissa (x = 1) to the largest abscissa (x = 640). This description is read every fiftieth of a second to be redisplayed on the screen. The description in memory can be summarized as follows:

<Tb>
<tb> x = 1 <SEP> x = 2 <SEP> ... <SEP> x = 639 <SEP> x = 640 <SEP> x = 1 <SEP> x-2 <SEP> .. <SEP> x = 640
<tb> y = 1 <SEP> y = 1 <SEP> y = 1 <SEP> y = 1 <SEP> y = 2 <SEP> y = 2 <SEP> y = 2
#### <SEP> N
<Tb>

Les numéros N se réfèrent à une liste d'attribution de couleurs se présentant comme suit :

N numbers refer to a color assignment list as follows:

<Tb>
<tb> N = 1 <SEP> RGB
<tb> N = 2 <SEP> RGB
<tb> N = 255 <SEP> RGB
<tb> N = 256 <SEP> RGB
<Tb>
The aescnpuon in memore translates a) screen by these pixels whose intensities of red, green, and blue spots are described in the location of the palette pointed by N. These pixels are organized as follows:

graphique L'adressage des pixels est assure par une unité non a ! gorithmique établissant ie hcn o t-C > <Tb>
<tb> x = 1 <SEP> x = 2 <SEP> x = 3 ... <SEP> x = 638 <SEP> x = 639 <SEP> x = 640
<tb> y = 1 <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N
<tb> y = 2 <SEP> N <SEP> N <SEP> N <SEP>. <SEP> N <SEP> N <SEP> N
<tb> y = 3 <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N
<tb> y = 398 <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N
<tb> y = 399 <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N
<tb> y = 400 <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N <SEP> N
<Tb>
The data falling on an image are saved in a special memory located on the map

graphic Pixel addressing is provided by a non-a unit! gorithmic establishing hcn o tC>

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between the processor and the graphics card. The pixel display is provided by another non-algorithmic unit: the cathode ray tube. Between these two functional units there are other functional units. The functional units transform the digital electrical signal into an electrical analog signal and then into a bright analog signal.

Among these functional units, some are non-algorithmic units such as ZD digital-to-analog converters, palette color assignment unit, or CRT control signal generation unit (CRTC). Others may be Zr, algorithmic units, but to the extent that the programmer has no control over these units, they are ignored for the modeling process. However, they can be taken into account in the implementation process after modeling.

 Note that if we had to deal with a graphics card with a computing unit specialized in 3D rendering, only non-algorithmic units presented in the previous paragraph would be considered. Algorithmic units (matrix computation on three-dimensional vector coordinates, rasterization unit, texture unit, etc.) should all be ignored. However, access to non-algorithmic units can sometimes only be done using these algorithmic units. Thus to access more directly to the pixel matrix component of the cathode ray tube, it would be mandatory to define a particular polygon whose texture would allow access to the pixels. This devious way would make it possible to consider the access to the non-algorithmic units as direct, and thus to ignore the algorithmic units in the modeling process.

l'utilisateur). De même, dans la configuration 640 par 400, les données indiquant le numéro de couleur pour chaque pixel sont des données d'exploitation. Cependant les données permettant de définir les niveaux de rouge, vert et bleu des 256 couleurs de la palette sont des données de configuration car elles paramètrent le fonctionnement de l'unité d'attribution de couleurs à la palette. De plus, elles ne font qu'influencer globalement le flux de données sortant du périphérique mais n'en font pas partie. 9.2. 4. 4-Configuration and Operation Data The data for placing the device in one of two image resolutions is configuration data. In the 320 by 200 configuration, the data sent is all operating data because it is the processed data stream (ultimately perceived by

the user). Similarly, in the 640 through 400 configuration, the data indicating the color number for each pixel is operating data. However, the data for defining the red, green, and blue levels of the 256 colors in the palette are configuration data because they set the operation of the color assignment unit to the palette. In addition, they only influence the flow of data exiting the device globally but are not part of it.

9.2. 4. 5-Microscopic Modeling Configuration Modeling 320 by 200 pixels: The following functional properties can be stated: The device displays an image of 320 pixels wide by 200 pixels high.

Pixels are organized in rows and columns.

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Each pixel is a colored dot composed of a red spot, a green spot and a blue spot.

The color of each pixel is independent of the other pixels.

The intensity of each spot is variable independently of others over time.

The pixels all have the same width and the same height, but a different position.

The entire image is completely redrawn every fiftieth of a second.

From the functional properties, we can consider that each pixel is a phenomenon or that the light signal conveying the image is a phenomenon.

The information gathered so far allows to define the microscopic structure of the device.

Les données d'exploitation sont les niveaux de rouge, de vert et de bleu. Pour un pixel, et pour un z intervalle de temps unitaire de 1/50ème de seconde, l'ensemble des niveaux de rouge possibles constitue un ensemble exclusif. Les ensembles des niveaux de vert et de bleu constituent deux autres ensembles exclusifs. Il existe donc trois ensembles exclusifs par pixel et par intervalle de temps unitaire. Pour un intervalle de temps unitaire, le périphérique comporte globalement 320 * 200 * 3 = 192 000 ensembles exclusifs. Comme le périphérique peut fonctionner pendant un temps potentiellement infini, le nombre d'ensembles exclusifs est lui-même infini. Chacun de ces ensembles exclusifs correspond à une source d'information élémentaire. From the programmer's point of view:

The operating data are the levels of red, green and blue. For a pixel, and for a z unit time interval of 1 / 50th of a second, the set of possible red levels constitutes an exclusive set. The sets of green and blue levels are two other exclusive sets. There are therefore three exclusive sets per pixel and per unit time interval. For a unit time slot, the device globally has 320 * 200 * 3 = 192,000 exclusive sets. Since the device can operate for a potentially infinite time, the number of exclusive sets is itself infinite. Each of these exclusive sets corresponds to a basic source of information.

From the point of view of the environment: For a particular exclusive set, we distinguish the following elementary phenomena: The luminous intensity programmed from a low value (0) to a high value (255) The color of the light of which the intensity is programmed The area of the colored spot whose intensity is programmed The vertical position of this spot The horizontal position of this spot The duration of emission of the light whose intensity is programmed The start time of emission D ' Other elementary phenomena could be stated, but they would be strictly identical for all the exclusive sets, and thus would not modify the structure of the macroscopic model.

All these elementary phenomena constitute the phenomenal characteristic representing the exclusive set. The luminous intensity is the modulated characteristic.

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For a unit time interval, there are therefore 192 000 phenomenal characteristics, some of whose elementary phenomena vary from one phenomenal characteristic to another (examples: the vertical position, the color, ...).

The analysis of the microscopic structure for this configuration is complete. The result is summarized in Figure 4. We can proceed to the modeling of the macroscopic structure.

Modeling 640 by 400 pixel configuration: In this configuration, the color assignment unit to the palette must be set.

Each of the 256 colors of the palette can be chosen independently of the others among millions of colors. The combination of all these possible choices constitutes, in the strict sense, as many possible configurations for this unit. However, these configurations are all equivalent, and are therefore considered as a single configuration to simplify the modeling step. Subsequently, the implementation of the theoretical model obtained will take into account the different configurations.

The following functional properties can be stated: The device displays an image 640 pixels wide by 400 pixels high.

Pixels are organized in rows and columns.

Each pixel is a colored dot composed of a red spot, a green spot and a blue spot.

The color of each pixel is independent of that of the other pixels, but depends on the configuration of the color assignment unit in the palette.

The color assignment unit in the palette prohibits the presence of more than 256 colors at the same time on the screen.

The color of each pixel is variable independently of others over time.

The pixels all have the same width and the same height, but a different position.

The entire image is completely redrawn every fiftieth of a second.

From the functional properties, we can consider that each pixel is a phenomenon or that the light signal conveying the image is a phenomenon.

The information gathered so far allows to define the microscopic structure of the device.

From the programmer's point of view: The operating data is the color numbers. For a pixel, and for a unit time interval of 1I50th of a second, the set of possible color numbers constitutes an exclusive set. There is therefore only one exclusive set per pixel and per unit time slot. For a unit time slot, the device globally has 640 * 400 = 256,000 exclusive sets. As the device can work for a while

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 potentially infinite, the number of exclusive sets is itself infinite. Each of these exclusive sets corresponds to a basic source of information.

From the point of view of the environment: For a particular exclusive set, we distinguish the following elementary phenomena: The color programmed among 256 possible (physically composed of three primary colors) The area of the light spot whose color is programmed The vertical position of this task The horizontal position of this task The emission duration of the light whose color is programmed The emission start time Other elementary phenomena could be stated, but they would be strictly identical for all the exclusive sets, and would not alter the structure of the macroscopic model.

All these elementary phenomena constitute the phenomenal characteristic representing the exclusive set. Color is the modulated feature.

For a unit time interval, there are therefore 256 000 phenomenal characteristics, some of which elementary phenomena vary from one phenomenal characteristic to another (example: the vertical position).

The analysis of the microscopic structure for this configuration is complete. The result is summarized in Figure 5. We can proceed to the modeling of the macroscopic structure.

9.2. 4. 6-Construction of the macroscopic model A / Construction of the configuration model 320 by 200 pixels: 9.2. 4.6. 1 - Initial step: We consider that no "dimension", "coordinate" or "intensity" is defined.

The first "dimension" is constructed as shown in Figure 6.

9.2. 4.6. 2-First iterative stage: We try to apply the rules of assembly in groups to the first "dimension".

We choose to gather "coordinates" in groups of 192,000 "coordinates" whose elementary phenomenon T is present identically in each "coordinate" of one of the groups.

The elementary phenomena T, S, 1 and D then constitute the intra-group characteristic of a group. For any "coordinate" of a group, the other elementary phenomena Xx, Yy and Cc of the phenomenal characteristic belong to the inter-group characteristic because they are found identically in a "coordinate" of each group.

The groups being constituted, two new "dimensions" are created:

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a "dimension" having a number of "coordinates" equal to the number of "coordinates" of a group of the "mother dimension", ie 192 000 "coordinates", and a "dimension" having a number of "coordinates" equal to number of groups in the "mother dimension". This number is potentially infinite and corresponds to the number of images displayed successively by the device since its start.

These new "dimensions" are presented in Figure 7.

dans une "coordonnée" de chacun des groupes. 9. 2. 4. 6. 3-Second iterative stage: We try to apply the grouping rules in groups to each of the two "dimensions" produced in the previous step. a) For the "dimension" 1: One chooses to gather the "coordinates" in 320 groups of 600 "coordinates" whose elementary phenomenon X is present identically in each "coordinate" of the group. The elementary phenomenon X is then the intra-group characteristic of a group. For any "coordinate" of a group, the other elementary phenomena Yy and Cc of the phenomenal characteristic belong to the inter-group characteristic because they are found in identical

in a "coordinate" of each group.

The groups being constituted, two new "dimensions" are created: a "dimension" having a number of "coordinates" equal to the number of "coordinates" of a group of the "mother dimension", ie 600 "coordinates", and a "dimension" having a number of "coordinates" equal to the number of groups of the "parent dimension", ie 320 "coordinates".

These new "dimensions" are presented in figure 8. b) For the "dimension" 2: We can only gather all the "coordinates" in a single group. The elementary phenomena S, t and D constitute the intra-group characteristic because they are present identically in each "coordinate" of the group. For each "coordinate", the elementary phenomenon Tn of the phenomenal characteristic constitutes the inter-group characteristic.

"dimension mère", soit une"coordonnée". The groups being constituted, two new "dimensions" are created: a "dimension" having a number of "coordinates" equal to the number of "coordinates" of the group. This number is potentially infinite and corresponds to the number of images displayed successively by the device since it was started, and a "dimension" having a number of "coordinates" equal to the number of groups of the device.

"mother dimension", ie a "coordinate".

These new "dimensions" are presented in Figure 9.

9. 2. 4. 6. 4-Third iterative stage:

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 Attempts are made to apply the grouping rules in groups to each of the four "dimensions" produced in the previous step. a) For the "dimension" 3: One chooses to gather the "coordinates" in 3 groups of 200 "coordinates" whose elementary phenomenon C is present identically in each "coordinate" of the group. The elementary phenomenon C is then the intra-group characteristic of a group. For any "coordinate" of a group, the elementary phenomenon Yy of the phenomenal characteristic constitutes the inter-group characteristic because it is found identically in a "coordinate" of each group.

The groups being constituted, two new "dimensions" are created: a "dimension" having a number of "coordinates" equal to the number of "coordinates" of a group of the "mother dimension", ie 200 "coordinates", and a "dimension" having a number of "coordinates" equal to the number of groups of the "mother dimension", ie 3 "coordinates".

These new "dimensions" are presented in figure 10. b) For the "dimension" 4: It is impossible to gather the 320 "coordinates" of the "dimension" 4 in groups. Indeed, if one constitutes two or more groups, there is neither intra-group nor inter-group characteristic (the third rule of assembly is therefore not respected). If we constitute a single group gathering all 320 "coordinates", then there is an inter-group characteristic by "coordinate". In this case, the second and third rules are not respected. The "dimension" 4 is thus definitively established. c) For the "dimension" 5: It is impossible to gather the "coordinates" of the "dimension" in groups. Indeed, if one constitutes two or more groups, there is neither intra-group nor inter-group characteristic (the third rule of assembly is therefore not respected). If we constitute a single group gathering all the "coordinates", then there is an inter-group characteristic by "coordinate". In this case, the second and third rules are not respected. The "dimension" 5 is thus definitively established. d) For the "dimension" 6: It is impossible to form groups with the single "coordinate" of the "dimension" 6. Indeed, one could only constitute one group, but then the first rule would be not respected. The "dimension" 6 is thus definitively established.

9.2. 4.6. 5-Fourth Iterative Step: We try to apply the grouping rules in groups to each of the two "dimensions" produced in the previous step. a) For the "dimension" 7:

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par"coordonnée". Dans ce cas, les deuxième et troisième règles ne sont pas respectées. La c "dimension"8 est donc définitivement établie. It is impossible to gather the 200 "coordinates" of the "dimension" 7 into groups. Indeed, if one constitutes two or more groups, there is neither intra-group nor inter-group characteristic (the third rule of assembly is therefore not respected). If we constitute a single group gathering all 200 "coordinates", then there is an inter-group characteristic by "coordinate". In this case, the second and third rules are not respected. The "dimension" 7 is thus definitively established. b) For the "dimension" 8: It is impossible to gather the 3 "coordinates" of the "dimension" 8 in groups. Indeed, it is not possible to create three groups of a single "coordinate" because the second rule is then not respected. On the other hand it is not possible to create two groups of one and two "coordinates" because the first and second rules are then not respected. If we constitute a single group gathering the 3 "coordinates", then there is an inter-groups characteristic

by "coordinated". In this case, the second and third rules are not respected. The "dimension" 8 is thus definitively established.

9.2. 4.6. 6-End It was not possible to create groups on any of the "mother sizes" available at this stage, so the construction of the macroscopic model is complete. The "dimensions" 4, 5, 6, 7 and 8 are grouped together within the "device space" (for the configuration considered).

B / Construction of the configuration model 640 by 400 pixels: 9.2. 4.6. 7 - Initial step: We consider that no "dimension", "coordinate" or "intensity" is defined.

We build the first "dimension" as shown in the figure! 1.

9.2. 4.6. 8-First iterative stage:
We try to apply the grouping rules in groups to the first "dimension".

One chooses to gather the "coordinates" in groups of 640 "coordinates" whose elementary phenomena T and Y are present identically in each "coordinate" of one of the groups. The elementary phenomena T, Y, S, P and D then constitute the intragroup characteristic of a group. For any "coordinate" of a group, the elementary phenomenon Xx of the phenomenal characteristic constitutes the inter-group characteristic because it is identical in a "coordinate" of each group.

The groups being constituted, two new "dimensions" are created: a "dimension" having a number of "coordinates" equal to the number of "coordinates" of a group of the "mother dimension", ie 640 "coordinates", and a "dimension" having a number of "coordinates" equal to the number of groups of the "parent dimension". This number is potentially infinite because it is related to the number of images displayed successively by the device since it was started.

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These new "dimensions" are presented in figure 12.

l'on constitue un seul groupe rassemblant l'ensemble des 640 "coordonnées", alors il existe une ZD caractéristique inter-groupes par"coordonnée". Dans ce cas, les deuxième et troisième règles ne ZD sont pas respectées. La "dimension" 1 est donc définitivement établie. b) Pour la "dimension" 2 : On choisit de rassembler les "coordonnées" en groupes de 400 "coordonnées" dont le phénomène élémentaire T est présent à l'identique dans chaque"coordonnée"du groupe. Les phénomènes élémentaires T, S, P et D constituent alors la caractéristique intra-groupe d'un groupe. Pour toute "coordonnée"d'un groupe, le phénomène élémentaire Yy de la caractéristique phénoménale appartient à la caractéristique inter-groupes car il se retrouve à l'identique dans une"coordonnée" de chacun des groupes.

9.2. 4.6. 9-Second Iterative Step: We try to apply the grouping rules in groups to each of the two "dimensions" produced in the previous step. a) For the "dimension" 1: It is impossible to gather the 640 "coordinates" of the "dimension" 1 in groups. Indeed, if one constitutes two or more groups, there is neither intra-group nor inter-group characteristic (the third rule of assembly is therefore not respected). Yes

we constitute a single group gathering all 640 "coordinates", then there is a characteristic ZD inter-groups by "coordinate". In this case, the second and third rules do not ZD are not respected. The "dimension" 1 is thus definitively established. b) For the "dimension" 2: We choose to gather the "coordinates" in groups of 400 "coordinates" whose elementary phenomenon T is present identically in each "coordinate" of the group. The elementary phenomena T, S, P and D then constitute the intra-group characteristic of a group. For any "coordinate" of a group, the elementary phenomenon Yy of the phenomenal characteristic belongs to the inter-group characteristic because it is found identically in a "coordinate" of each group.

The groups being constituted, two new "dimensions" are created: a "dimension" having a number of "coordinates" equal to the number of "coordinates" of a group of the "mother dimension", ie 400 "coordinates", and a "dimension" having a number of "coordinates" equal to the number of "coordinates" of the group. This number is potentially infinite and corresponds to the number of images displayed successively by the device since its start.

These new "dimensions" are presented in figure 13.

l'on constitue un seul groupe rassemblant l'ensemble des 400 "coordonnées", alors il existe une caractéristique inter-groupes par"coordonnée". Dans ce cas, les deuxième et troisième règles ne sont pas respectées. La"dimension"3 est donc définitivement établie. d) Pour la"dimension"4 : 9.2. 4.6. 10-Third iterative step: We try to apply the grouping rules in groups to each of the two "dimensions" produced in the previous step. c) For the "dimension" 3: It is impossible to gather the 400 "coordinates" of the "dimension" 3 in groups. Indeed, if one constitutes two or more groups, there is neither intra-group nor inter-group characteristic (the third rule of assembly is therefore not respected). Yes

we constitute a single group gathering all 400 "coordinates", then there is an inter-group characteristic by "coordinate". In this case, the second and third rules are not respected. The "dimension" 3 is thus definitively established. d) For the "dimension" 4:

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 We can only gather all the "coordinates" into one group. The elementary phenomena S, P and D constitute the intra-group characteristic because they are present identically in each "coordinate" of the group. For each "coordinate", the elementary phenomenon Tn of the phenomenal characteristic constitutes the inter-group characteristic.

une"dimension"possédant un nombre de "coordonnées" égal au nombre de groupes de la CI "dimension mère", soit une"coordonnée". Ces nouvelles"dimensions"sont présentées en figure 14. The groups being constituted, two new "dimensions" are created: a "dimension" having a number of "coordinates" equal to the number of "coordinates" of the group. This number is potentially infinite and corresponds to the number of images displayed successively by the device since it was started, and

a "dimension" having a number of "coordinates" equal to the number of groups of the "parent dimension" CI, a "coordinate". These new "dimensions" are presented in figure 14.

On tente d'appliquer les règles de rassemblement en groupes à chacune des deux"dimensions" ZD produites à l'étape précédente. e) Pour la "dimension" 5 : Il est impossible de rassembler les "coordonnées" de la "dimension" 5 en groupes. En effet, si l'on constitue deux ou plusieurs groupes, il n'existe ni caractéristique intra-groupe, ni caractéristique inter-groupes (la troisième règle de rassemblement n'est donc pas respectée). Si l'on constitue un seul groupe rassemblant l'ensemble des"coordonnées", alors il existe une caractéristique inter-groupes par"coordonnée". Dans ce cas, les deuxième et troisième règles ne sont pas respectées. La"dimension"5 est donc définitivement établie. f) Pour la "dimension" 6 : Il est impossible de constituer des groupes avec l'unique "coordonnée" de la "dimension" 6. En effet, on ne pourrait constituer qu'un seul groupe, mais alors la première règle ne serait pas respectée. La"dimension"6 est donc définitivement établie. 9. 2.4. 6. 11 - Fourth step iterative:

Attempts are made to apply the grouping rules in groups to each of the two ZD "dimensions" produced in the previous step. e) For the "dimension" 5: It is impossible to gather the "coordinates" of the "dimension" in groups. Indeed, if one constitutes two or more groups, there is neither intra-group nor inter-group characteristic (the third rule of assembly is therefore not respected). If we constitute a single group gathering all the "coordinates", then there is an inter-group characteristic by "coordinate". In this case, the second and third rules are not respected. The "dimension" 5 is thus definitively established. f) For the "dimension" 6: It is impossible to form groups with the single "coordinate" of the "dimension" 6. Indeed, one could only constitute one group, but then the first rule would be not respected. The "dimension" 6 is thus definitively established.

9.2. 4.6. 12-End It was not possible to create groups on any of the "mother sizes" available at this stage, so the construction of the macroscopic model is complete. The "dimensions" 1, 3,5 and 6 are grouped together within the "device space" (for the configuration considered).

Both configurations are now organized according to a structure reflecting the device's relationship to the real world. On this structure will be grafted the information to program the device, as we will see later.

9. 3-Tree representation of the model 9.3. 1-The concept of peripheral tree We deduce from the theoretical modeling a hierarchical classification allowing to describe in a synthetic way the function of each peripheral, by organizing the models

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 theoretical devices according to a tree. This tree is made up of "nodes". The links between the nodes are symbolized by "branches" (or internodes). A node can group one (or more) other node (s). A node that does not group any other node is named "leaf". A sheet is an indivisible unitary information that does not gather other more basic information.

This tree is a set of subordinate links, an element that includes sub-elements that describe it more precisely. The links it establishes can be represented graphically by a tree, allowing the programmer faster and more intuitive access to his organization. Unlike the usual convention in computer science, the representation chosen is modeled on the living structures of the same name. Thus, going from the bottom up, this tree has a root node (called "root"), nodes and leaves. The root groups all the nodes and leaves. The further a node is from the root, the smaller the number of nodes it gathers. A leaf is located at one end of the tree.

A root node includes a large number of different nodes and leaves that can be distributed among multiple devices. A node near the ends of the tree groups a small number of nodes or sheets that can be specific to a single device.

9. 3. 2-General description of the device tree The devices are described in the form of a tree structure organized into levels. On each of these levels, all the nodes are similar. These nodes are named according to the level they occupy in the hierarchy (see Fig. 15 at the end of paragraph 11). Between two nodes of any level, there always exist all the nodes of the intermediate levels making it possible to connect them. If a node does not group any node, then it becomes leaf. This process can continue on some nodes as it progresses to the root of the tree.

To get to know a device, or to access it, we run the tree from the root to the leaves. This tree is designed to allow the configuration and programming of a device by simply running its nodes.

Depending on whether a device is available or not, the corresponding branch of the tree supporting the nodes describing that device appears or disappears.

Another tree or a portion of a tree, representing peripherals controlled by another Universal Machine, can also be grafted onto this tree. A virtual processor can thus control devices through another virtual processor. This transplant results in a link between the two trees at a specific node, but each tree retains its own structure.

Each node can provide "dependency guidelines". These are constraints on the structure of the tree as it travels, depending on the interaction between devices, their

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 possible configurations and their operating limits. Some branches of the tree can thus be available or temporarily unavailable, and therefore appear or disappear, when accessing a particular device, or when placing it in a particular configuration. Some dependence guidelines may be single-use or counted: it's called a "pruning guideline". A branch then becomes permanently available or unavailable when the condition defined by pruning directive (s) is fulfilled.

The different configurations of the function of a device give rise to as many theoretical models. These models are all gathered in the same device "space" because of the same function, although their structures may differ. In order to allow the coexistence of these models, some nodes gather at the next level several groups of nodes which correspond to the different possible configurations. These groups of nodes then mutually exclude each other by dependency directives. We speak of "variable geometry node".

These last three mechanisms give the tree a plastic structure.

9.3. 3 - Detailed description of the device tree The root of the tree represents the "universe" of the devices. This is the entry point into the device tree. If it is not present, it is considered that there are no devices accessible by the virtual processor. However, this case does not correspond to a normal operation of the machine, because the virtual processor can not work in the absence of at least one device of RAM or ROM type.

 This "universe" includes two nodes called "groups" located at the following level: the "group" of the exchange devices, and e "group" of the storage devices. These "groups" symbolize the fate of information exchanged between the processor and a device: either they will be transmitted in an open environment, accessible at any time by other receivers than the processor, thus allowing their communication with the outside of the machine (Or they will be transmitted from transmitters, located in an open environment, to the processor). This is the case of a video screen accessible by a human or a data bus accessible by another processor for example. These are actually all public devices; either they will be transmitted in an environment accessible exclusively by the processor for a certain time (a memory, a hard disk, etc.). These are mostly private devices.

As for the universe ", the absence of one of these nodes indicates that there is no available device having the specificities of the" group "concerned.

Each of these "groups" includes two "hyperespaces" located at the next level. The "hyperespaces" of the "group" of the exchange devices indicate the direction of transmission of the information. We distinguish :

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 the "hyperspace" of the output exchange devices: the information will go from the processor to its external environment, and "hyperspace" of the input exchange devices: the information will go from the external environment to the processor.

disponibilité ultérieure, sans quoi, conserver une information sans jamais pouvoir y accéder revient à la détruire. On notera toutefois que ces périphériques sont le plus souvent accessibles en entrée et en sortie. The problem is different in the case of storage devices. They are necessarily accessible in input since the notion of conservation of an information implies its

later availability, without which, to keep information without being able to access it is to destroy it. Note, however, that these devices are most often accessible in and out.

The discriminating nature of these devices is the availability of information for the processor. Indeed, some of these devices are critical for the proper functioning of the processor, especially RAM and ROM. As a result, the "hyperpaces" of the "group" of the storage devices indicate the level of availability of information for the processor. One distinguishes: the "hyperspace" of addressable storage devices: the processor has instantaneous, permanent and direct access to the peripherals, by an area of its address space, in order to exchange information, and the "hyperspace" of peripherals non-addressable storage: access to information is indirect (requires an access algorithm). It is often slower (case of the mass carriers) and / or is not guaranteed permanently (case of removable mass supports).

Each of these "groups" includes one or more "spaces" of devices located at the next level. From this level of the tree, we discuss the operation of a device.

 A "space" groups together the "dimensions" of a device modeled by macroscopic analysis.

 A "dimension" includes one or more "coordinates". A precise "coordinate", if necessary, the physical or symbolic nature of the elementary characteristic that it supports. If all the "coordinates" that a "dimension" groups are of the same nature, then this "dimension" specifies this nature.

 The "intensities" represent the level at the end of the tree. They represent the possible intensities of expression of the modulated characteristic of the "coordinate".

 The "coordinates" or "intensities" are most often the leaves of the tree.

10-Practical Aspects 1 0. 1 - Implementing Devices in the Universal Machine For each large hierarchical level of the Universal Machine, we define a device access method based on the theoretical model described. Each access method has more or less information about the devices.

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The implementation of the devices at zero level must allow to reconstruct the complete device tree as described (see Figure 15). However, it must be reduced to the essentials to maintain the simplicity of the zero level emulator. As a result, the representation of the device tree is partial, and some of its features are deduced and reconstructed by specific programs written in zero level.

de la figure 15. En effet, le niveau zéro émulant le niveau 1 reconstitue l'arborescence complète des périphériques, et met en place des fonctions qui en simplifient l'exploitation. i 0. !. 1-tmptémentation en niveau zéro L'implémentation présentée dans cette partie est prévue pour le niveau 0.4 (ou le niveau 0.2 émulant le niveau 0.4). Elle sert de base pour le système de gestion des périphériques plus élaboré du niveau supérieur (niveau 1). The implementation in the context of the level 1 machine 30 is an exact reflection of the type of tree

of figure 15. Indeed, the zero level emulating the level 1 reconstitutes the complete tree of the peripherals, and sets up functions which simplify the exploitation. i 0.!. 1-level zero leveling The implementation presented in this section is for level 0.4 (or level 0.2 emulating level 0.4). It serves as a basis for the more advanced device management system at the top level (level 1).

premier bloc établit le lien avec les adresses d'accès au périphérique sur la machine support 23. Il contient des programmes écrits dans le langage machine natif de la machine support 23 afin de transporter les données échangées aux bonnes adresses. Ces programmes permettent aussi de détecter la présence du périphérique et de l'initialiser dans un état stable permettant son bon

fonctionnement ultérieur (sous-programme d'initialisation). The information from the theoretical modeling step of a peripheral device (or several interdependent peripherals), as well as the access protocol to the latter on the support machine 23, are grouped into three distinct blocks: the first block, named "LINK" 26, makes it possible to transport and route the configuration and operating data exchanged between the zero level virtual processor and a particular peripheral of the support machine 23 via the "MER" register 27. The

first block establishes the link with the device access addresses on the support machine 23. It contains programs written in the native machine language of the support machine 23 in order to transport the exchanged data to the correct addresses. These programs can also detect the presence of the device and initialize it in a stable state allowing its good

subsequent operation (initialization routine).

the second block, named "TREE" 29, gives the main information for evaluating the function of the device and all the information for calculating and interpreting the configuration and operating data. The evaluation is allowed by the binary coding of the theoretical tree model, while the calculations and interpretations of the exploitation and configuration data are carried out by means of specific programs inserted in this coding. A "TREE" block 29 is the description of the space "of a peripheral (or several in exceptional cases, explained later) and all the nodes it encompasses (" space "," dimensions " "," coordinates "and" intensities "), therefore a portion of the tree, which indicates the" hyperspace "to which the device belongs.

 - the third block, optional, is named "FEATURE EXTENSION" or "FEXT". I) may be present when the "TREE" block 29 can not provide certain information. It can contain physical equations, symbolic representations (for example graphical), or any other type of physical, symbolic, or even logical characteristics modeling.

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de préciser le comportement dans la réalité des"dimensions","coordonnées"et"intensités" incluses dans le bloc "TREE" 29. II peut aussi contenir d'autres informations venant enrichir le bloc "TREE" 29.

to specify the behavior in reality of the "dimensions", "coordinates" and "intensities" included in the "TREE" block 29. It may also contain other information enriching the "TREE" block 29.

inchangé, et peut être réutilisé tant que les caractéristiques du périphérique restent strictement c identiques. A "TREE" block 29 or "FEXT" is specific to a particular device, but totally independent of the support machine 23 in which this device is implanted. Thus, it does not matter if a sound card is connected in a PC or Apple PC, in a personal assistant or in a mobile phone: the block "TREE" 29 or "FEXT" is

unchanged, and can be reused as long as the device's characteristics remain strictly the same.

A "LINK" block 26 is specific to a device and the support machine 23 in which this device is inserted. To be able to exploit the sound card (taken for example above) implanted in one of the support machines described, it will be necessary for a programmer to rewrite the "LINK" block 26 for this machine.

To be able to operate a device, it is necessary at least its "TREE" block 29, as well as the associated "LINK" block 26 which corresponds to the support machine 23 considered.

The "TREE" block 29 represents most of the work of accessing a device. The block "LINK" 26 is relatively short since its function is generally to carry information between the virtual processor and a device. The peripheral device management portion of a support machine 23 is thus reduced.

10. 1. 2 - Level 1 Implementation The implementation of Level 1 devices is based on a zero level program using the devices available at its level. The more complex structure of Level 1 is more in line with a more complete representation and more immediate access to peripherals. The device tree presented in Level 1 has all the nodes described in Section 9.3. 3 (especially the "groups", "universe", and "hyperespaces"). The programming of the peripherals is done thanks to a protocol allowing to navigate in the tree from branch to branch. The dependency directives are not directly accessible, but are expressed by modifying the structure of the tree according to the branches covered.

10. 2-Access to devices at zero level 10.2. 1-Schema of organization For the programmer to move to the implementation phase of the devices in the machine of level zero, it must have previously carefully modeled them, and to know all the information making it possible to describe the "dimensions", "coordinates "and" intensities ".

The establishment of the tree and its operation are supported by different processors. It is provided on the one hand by the support machine 23, through a portion of the emulation program of the zero level machine called the cartographer / enumerator 25

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(Mapper/Enumerator) qui prend en charge les protocoles d'accès aux périphériques à partir du niveau zéro. D'autre part, le processeur de niveau zéro reçoit les blocs "TREE" 29 à partir du cartographe/énumérateur 25 par l'intermédiaire du registre"MER"27 (Mapper/Enumerator Register pour"registre de cartographe/énumérateur"). Enfin, un processeur virtuel spécialisé, émulé par le processeur de niveau 0.4, prend en charge les programmes de calcul des données de configuration et d'exploitation, ainsi que les directives de dépendance insérés dans les noeuds de l'arbre. C'est le coprocesseur de périphériques 28.

(Mapper / Enumerator) that supports device access protocols from scratch. On the other hand, the Zero Level Processor receives the "TREE" blocks 29 from the Mapper / Enumerator 25 through the "MER" Register 27 (Mapper / Enumerator Register for "Cartographer / Enumerator Register"). Finally, a specialized virtual processor, emulated by the level 0.4 processor, supports the programs for calculating the configuration and operating data, as well as the dependency directives inserted into the nodes of the tree. It is the coprocessor of peripherals 28.

The zero level processor is then able to execute a program that supports the traversing of the different branches of the tree to access the peripherals, through the programs of the coprocessor 28 which access the register "MER" 27.

cartographe/énumerateur 25, par l'intermédiaire du registre"MER"27. L'ensemble de ces blocs ZD contient toutes les indications nécessaires pour pouvoir reconstruire un arbre des périphériques complet comme décrit au paragraphe 9. 3. 3. Les blocs "LINK" 26 sont installés dans la mémoire ZD de la machine support 23 par le cartographe/énumerateur 25, qui les appelle selon les"espaces" de périphériques utilisés. Les blocs"FEXT"sont chargés explicitement par un programme écrit en niveau 0.4 et viennent enrichir les descriptions des blocs "TREE" 29. In level zero, the blocks "TREE" 29 are transmitted on command by the

cartographer / enumerator 25, through the register "MER" 27. The set of these blocks ZD contains all the indications necessary to be able to reconstruct a complete peripheral tree as described in section 9. 3. 3. The "LINK" blocks 26 are installed in the memory ZD of the support machine 23 by the cartographer / enumerator 25, which calls them according to the "spaces" of peripherals used. The "FEXT" blocks are explicitly loaded by a program written in level 0.4 and enrich the descriptions of the blocks "TREE" 29.

 1 0. 2. 2-The device coprocessor 28 The simple analysis of the "TREE" blocks 29 makes it possible to evaluate the environment of the virtual processor, without having access to it. To access the devices, run programs must be run in the nodes of the "TREE" blocks. 29. These programs calculate the operating and configuration data needed to use the device, given the branch of the tree traveled. . Most of the time, only the programs located in some nodes (especially the "intensity nodes") are responsible for realizing the access to the peripherals, according to the data computed by the programs of other nodes. In addition, the browse program of a "space" node must activate the corresponding device, in particular its interrupt mechanism.

The execution of a program of course is conditioned by the result of the execution of the authorization program located in the same node.

Some devices are capable of triggering an interrupt, that is, requesting immediate special processing by the zero level program. In this case, an interrupt program must be executed by the device coprocessor 28, in order to maintain certain parameters.

Only nodes in the tree belonging to a device space ("space", "dimension", "coordinate", "intensity") can contain path and authorization programs. To work, these programs use a restricted programming environment named

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coprocesseur de périphériques 28, disposant de 25 types d'instructions, de 8 registres de données à usage général, et de quatre indicateurs binaires d'état. z 10.2. 2. 1-Organisation de l'environnement de programmation L'environnement de programmation du coprocesseur 28 s'apparente à une machine virtuelle constituée d'un processeur virtuel n'ayant accès qu'à une unique mémoire réinscriptible, appelée

mémoire données. Le programme à exécuter par le processeur est situé dans une mémoire ZD programmes séparée. Le contenu de cette mémoire est inaccessible au processeur, mais ce dernier peut se positionner à l'intérieur de la séquence des instructions, par rapport à la dernière instruction délivrée (saut relatif).

device coprocessor 28, having 25 types of instructions, 8 general-purpose data registers, and four state binary indicators. z 10.2. 2. 1-Organization of the programming environment The programming environment of the coprocessor 28 is similar to a virtual machine consisting of a virtual processor having access only to a single rewritable memory, called

memory data. The program to be executed by the processor is located in a separate program memory ZD. The content of this memory is inaccessible to the processor, but the latter can be positioned within the sequence of instructions, compared to the last instruction issued (relative jump).

The processor has eight internal registers, each 16 bits wide, named RO to R7. It is able to execute 25 types of instructions, and can keep some results characteristic of the last operation in status indicators (sign: N, nullity: Z, overflow: 0, restraint: C).

The operations are encoded as 16-bit words. There are three main groups of operations: loading, saving, terminating arithmetic operations and logical jumps conditional The rewritable memory to which the processor has access can contain 65536 distinct words at most. The size of this memory is statically set to 0 or by a power of 2 for all the programs of a "TREE" block 29. This memory can therefore be absent, or have a capacity ranging from 20 = 1 given memory word to i6 = 65536 memory words given at most. When executing a coprocessor instruction using a data memory smaller than the maximum addressable size of the instruction in question, the unused address bits are ignored.

A coprocessor program consists of a succession of instructions that are executed sequentially, except for breaks that constitute sequence breaks. The number of instructions that it can contain is not limited. This program can not in any case access the program memory containing the instructions constituting it, whether in reading or writing. It can not be modified.

All the coprocessor programs concerning the same device (thus located in the same "space" of device) access exclusively to one and the same rewritable memory, whose capacity is fixed during the installation of the tree. They will have to be planned to use this memory without conflicts between them.

10.2. 2. 2-Description of the instruction set

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 The device coprocessor 28 has twenty-five types of instructions described in the tables below.

les bits d'un mot 16 bits sont numérotés de 0 à 15. Le bit 0 étant le bit de plus faible poids, le bit
15 celui de plus fort poids. The following conventions are common to the description of all instructions. a bit of value 1 is said to be raised and a bit of value 0 is said to be lowered,

the bits of a 16-bit word are numbered from 0 to 15. The bit 0 is the least significant bit, the bit
15 the one with the highest weight.

In the coding of an instruction: "r" denotes a coding bit of the register number.

"a" denotes a coding bit of the memory address.

"i" denotes a coding bit of the immediate value.

 "?" designates a reserved bit, which has to be systematically lowered to ensure backwards compatibility with any later versions.

 "z", "o", "n" and "c" denote the update bits of the indicators Z, 0, N and C respectively: if they are raised, the corresponding indicators are updated according to the result of the operation.

 "s" means a bit of coding of the source register number.

"d" denotes a coding bit of the destination register number.

<Tb>
<Tb>

Syntax <SEP> of <SEP> Encoding <SEP> of <SEP> Description <SEP> of <SEP> Operation <SEP> of <SEP> Statement
<tb> the <SEP> statement the <SEP> statement in
<tb> binary
<tb><SEP> Instructions <SEP> Load, <SEP> of <SEP> Backup, <SEP>, and <SEP> of <SEP> Termination.
<Tb>

LD <SEP> Rd, <SEP> mem <SEP> 000rrraaaaaaaaaa <SEP> Rd <SEP><-content<SEP> of <SEP> The <SEP> memory <SEP> pointed <SEP> by <SEP> mem <SEP > (modulo
<tb> the <SEP> size <SEP> of <SEP> the <SEP> memory <SEP> data).
<Tb>

ST <SEP> mem, <SEP> Rs <SEP> 00 <SEP> J <SEP> rrraaaaaaaaaa <SEP> Memory <SEP> pointed <SEP> by <SEP> mem <SEP> (modulo <SEP> the <SEP> size <SEP> of <SEP> the
<tb> memory <SEP> data) <SEP> v <SEP> Rs.
<Tb>

LD <SEP> Rd, <SEP>&num; imm <SEP> 01 <SEP> Orrriiiiiiiiii <SEP> Rd <SEP><-value<SEP> immediate <SEP> imm <SEP> extended <SEP> by <SEP><SEP> sign <SEP> to <SEP> 16
<tb> bits.
<Tb>

The <SEP> 10 <SEP> bits <SEP> of <SEP><SEP> weight <SEP> of the <SEP><SEP><SEP><SEP> statement are
<tb> copied <SEP> in <SEP><SEP> 10 <SEP> bits <SEP> of <SEP> weight <SEP> low <SEP> of <SEP> Rd. <SEP> The <SEP> bit <SEP> de
<tb> weight <SEP> strong <SEP> of <SEP> the <SEP> value <SEP> immediate <SEP> (bit <SEP> 9) <SEP> is <SEP> copied <SEP> in
<tb> each <SEP> of <SEP> bits <SEP> 10 <SEP> to <SEP> 15 <SEP> of <SEP> Rd.
<Tb>

EOP <SEP> 0110 <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP> Ends <SEP> the <SEP> execution of the <SEP> program. <SEP> R7 <SEP> must <SEP> contain <SEP> one
<tb><SEP> code of <SEP> termination <SEP> 16 <SEP> bits. <SEP><SEP> other <SEP> registers <SEP> can
<tb> hold <SEP> a <SEP> extension <SEP> of <SEP> this <SEP> code.
<Tb>

LD <SEP> Rd, LINK <SEP> 01110rrr <SEP>? <SEP>? <SEP>? <SEP><-vitter<SEP> returned <SEP> with <SEP><SEP> subprogram <SEP> of <SEP> read
<Tb>

<Desc / Clms Page number 55>

<Tb>
<tb> dubloc "LlNK" 26.
<Tb>

ST <SEP> LINK, Rs <SEP> 01111rrr <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP>? <SEP><SEP> Write <SEP><SEP> block <SEP>"LINK"<SEP> 26 <SEP>#<SEP> Rs.
<Tb>

The instructions for accessing "MER" 27 are restricted with respect to accessing this register directly from level 0.4. This is why only the read and write functions on the "LINK" block 26 corresponding to the "space" of the device to which the program belongs are allowed.The number of the read or write command on the block " LlNK "26 is automatically sent to" MER "27 by the peripheral coprocessor emulator 28.

In general, for the arithmetic and logic instructions: the indicator N is a copy of the bit 15 of the result of the instruction the indicator Z is raised if all the bits of the result are lowered; the flag 0 is raised if the instruction generates an overflow in signed logic; and the indicator C is raised if a deduction or a loan is generated by the instruction.

<Tb>
<Tb>

<SEP> arithmetic, <SEP> logical, <SEP>, and <SEP> instructions of <SEP> moving
<tb> ADD <SEP> Rd, <SEP> Rs, <SEP> ZONC <SEP> 00000zoncsssddd <SEP> Rd <SEP> Rd <SEP> + <SEP> Rs. <SEP> The <SEP> Indicators <SEP > selected <SEP> are <SEP> set <SEP> to
<tb> day.
<Tb>

ADC <SEP> Rd, <SEP> Rs, <SEP> ZONC <SEP> 10000 <SEP> 1 <SEP> zoncsssddd <SEP> Rd <SEP><-Rd<SEP> + <SEP> Rs <SEP> + <SEP> c. <SEP><SEP><SEP> selected <SEP> indicators are <SEP> set
<tb> up to date.
<Tb>

SUB <SEP> Rd, <SEP> Rs, <SEP> ZONC <SEP> 000 <SEP>! <SEP> 0zoncsssddd <SEP> Rd <SEP><-Rd-Rs.<SEP> The <SEP><SEP> selected <SEP> indicators are <SEP> set <SEP> to
<tb> day.
<Tb>

SBB <SEP> Rd, <SEP> Rs, <SEP> ZONC <SEP> 10001 <SEP> 1 <SEP> zoncsssddd <SEP> Rd <SEP><-Rd-Rs-c.<SEP><SEP><SEP> selected <SEP> indicators are <SEP> set
<tb> up to date.
<Tb>

MUL <SEP> Rd, <SEP> Rs, <SEP> ZONC <SEP> 100100zoncsssddd <SEP> Rd <SEP><-Rd<SEP> * <SEP> Rs. <SEP> The <SEP> multiplication <SEP> is <SEP> performed <SEP> on <SEP> of
<tb> signed operands <SEP> no <SEP>. <SEP> The <SEP><SEP> selected <SEP> indicators are
<tb> put <SEP> up to the day <SEP>:
<tb> 0 <SEP> is <SEP> raised <SEP> if <SEP> the <SEP> product <SEP><SEP> can <SEP> not <SEP> be <SEP> expressed <SEP> on <SEP > 16
<tb> bits. <SEP> In <SEP> this <SEP> case, <SEP> Rd <SEP> contains <SEP><SEP> 16 <SEP> bits <SEP> of <SEP><SEP> weight low
<tb> of the <SEP> product.
<Tb>

Z <SEP> is <SEP> raised <SEP> if <SEP> one <SEP> of <SEP> two <SEP> multiplicands <SEP> is <SEP> null.
<Tb>

N <SEP> contains <SEP> the <SEP> bit <SEP> number <SEP> 17 <SEP> of the <SEP> product.
<Tb>

C <SEP> contains <SEP> the <SEP> bit <SEP> number <SEP> 6 <SEP> of the <SEP> product.
<Tb>

DIV <SEP> Rd, <SEP> Rs, <SEP> ZONC <SEP> 00 <SEP>! <SEP> 01 <SEP> zoncsssddd <SEP> Rd <SEP><-Rd<SEP> div <SEP> Rs. <SEP> Rs <SEP><-Rd<SEP> mod <SEP> Rs. <SEP> The <SEP> division <SEP> is
<tb> performed <SEP> on <SEP> signed <SEP> operands <SEP> no <SEP>. <SEP> In <SEP> cases <SEP> of
<tb> division <SEP> by <SEP> 0, <SEP> Rd <SEP> and <SEP> Rs <SEP> are <SEP> unchanged. <SEP> The <SEP> indicators
<tb> selected <SEP> are <SEP> set <SEP> to <SEP> day <SEP>:
<tb> O <SEP> is <SEP> raised <SEP> in <SEP> case <SEP> of <SEP> division <SEP> by <SEP> 0.
<Tb>

<Desc / Clms Page number 56>

<Tb>
<Tb>

Z <SEP> is <SEP> raised <SEP> if <SEP> the <SEP> quotient <SEP> is <SEP> zero.
<Tb>

N <SEP> is <SEP> the <SEP><SEP> copy of the <SEP><SEP> bit of <SEP><SEP> strong <SEP> weight of the <SEP> quotient.
<Tb>

C <SEP> is <SEP> raised <SEP> if <SEP> the <SEP> remains <SEP> is <SEP> not <SEP> null.
<Tb>

MOVE <SEP> Rd, <SE> Rs, <SEP> ZN <SEP> 1001 <SEP> fOzOn <SEP>? <SEP> sssddd <SEP> Rd <SEP><-Rs.<SEP> The <SEP><SEP> selected <SEP> indicators are <SEP> set <SEP> to <SEP> days.
<Tb>

The <SEP> flags <SEP> 0 <SEP> and <SEP> C <SEP> ne <SEP> are <SEP> never <SEP> assigned.
<Tb>

MOVE <SEP> Rd, <SEP> [Rs], <SEP> ZN <SEP> 100 <SEP> 11 <SEP> Oz <SEP> 1 <SEP> nosssddd <SEP> Rd <SEP><-mot<SEP> located <SEP> to <SEP> the address <SEP> Rs <SEP> (modulo <SEP> the <SEP> size <SEP> of <SEP>
<tb> memory <SEP> data). <SEP><SEP><SEP> selected <SEP> indicators are <SEP> set
<tb> to <SEP> day. <SEP> The <SEP> flags <SEP> 0 <SEP> and <SEP> C <SEP> ne <SEP> are <SEP> never <SEP> assigned.
<Tb>

MOVE <SEP> [Rd], <SEP> Rs, <SEP> ZN <SEP> 00110zlnlsssddd <SEP> Word <SEP> located <SEP> to <SEP> address <SEP> Rd <SEP> (modulo <SEP ><SEP> size <SEP> of <SEP> the <SEP> memory
<tb> data) <SEP><-Rs.<SEP> The <SEP><SEP> selected <SEP> indicators are <SEP> set <SEP> to
<tb> day. <SEP> The <SEP> flags <SEP> 0 <SEP> and <SEP> C <SEP> ne <SEP> are <SEP> never <SEP> assigned.
<Tb>

AND <SEP> Rd, <SEP> Rs, <SEP> ZN <SEP> 100 <SEP> 111 <SEP> z <SEP>? <SEP> n <SEP>? <SEP> sssddd <SEP> Rd <SEP>#<SEP> Rd <SEP> AND <SEP> Logic <SEP> Rs. <SEP> The <SEP> Selected <SEP> Indicators
<tb> are <SEP> set <SEP> to <SEP> day. <SEP> The <SEP> flags <SEP> 0 <SEP> and <SEP> C <SEP> ne <SEP> are <SEP> never
<tb> affected.
<Tb>

OR <SEP> Rd, <SEP> Rs, <SEP> ZN <SEP> \ <SEP> 0 <SEP> \ <SEP> OOOz <SEP>? <SEP> n <SEP>? <SEP> sssdddRd <SEP><-Rd<SEP> OR <SEP> Logic <SEP> Rs. <SEP> The <SEP> Selected <SEP> Indicators
<tb> are <SEP> set <SEP> to <SEP> day. <SEP> The <SEP> flags <SEP> 0 <SEP> and <SEP> C <SEP> ne <SEP> are <SEP> never
<tb> affected.
<Tb>

XOR <SEP> Rd <SEP> Rs <SEP> ZN <SEP> 01001 <SEP> z <SEP>? <SEP> n <SEP>? <SEP> sssdddRd <SEP><-Rd<SEP> OR <SEP> logical <SEP> exclusive <SEP> Rs. <SEP> The <SEP> flags
<tb> selected <SEP> are <SEP> set <SEP> to <SEP> day. <SEP> The <SEP> flags <SEP> 0 <SEP> and <SEP> C <SEP> do not
<tb> are <SEP> never <SEP> assigned.
<Tb>

ASR <SEP> Rd, <SE> Rs, <SEP> ZNC <SEP> 01010z <SEP>? <SEP> ncsssddd <SEP> Offset <SEP> arithmetic <SEP> of <SEP> Rs <SEP> bits <SEP> (modulo <SEP> 16) <SEP> to <SEP>
<tb> Right <SEP> of the <SEP> registry <SEP> Rd. <SEP> The <SEP><SEP> selected <SEP> flags are
<tb> set <SEP> to <SEP> day. <SEP> The <SEP> 0 <SEP> flag is <SEP> never <SEP> assigned.
<Tb>

The <SEP> C <SEP> flag is <SEP> to the last <SEP> last <SEP> bit <SEP>.
<Tb>

ASR <SEP> Rd, <SEP>&num; imm, <SEP> ZNC <SEP> 101011 <SEP> z <SEP>? <SEP> nciiiddd <SEP> Offset <SEP> arithmetic <SEP> of <SEP> (imm + 1) <SEP> bits <SEP> to <SEP> the <SEP><SEP> of the
<tb> register <SEP> Rd. <SEP> The <SEP><SEP> selected <SEP> indicators are <SEP> set <SEP> to <SEP> days.
<Tb>

The <SEP> 0 <SEP> flag is <SEP> never <SEP> assigned. <SEP> The <SEP> C indicator
<tb> matches <SEP> at the last <SEP> last <SEP> bit <SEP>.
<Tb>

LSL <SEP> Rd, <SEP> Rs, <SEP> ZONC <SEP> 01 <SEP> 100zoncsssddd <SEP> Offset <SEP> Logic <SEP> of <SEP> Rs <SEP> Bit <SEP> (modulo <SEP > 16) <SEP> to <SEP> the <SEP> left
<tb> of <SEP> registry <SEP> Rd. <SEP> The <SEP><SEP> selected <SEP> indicators are <SEP> set <SEP> to
<tb> day. <SEP> The <SEP> C <SEP> flag is <SEP> to the last <SEP><SEP> bit <SEP>.
<Tb>

LSL <SEP> 10 <SEP> 1 <SEP> 10 <SEP> 1 <SEP> zonciliddd <SEP> Offset <SEP> logical <SEP> of <SEP> (imm + <SEP> 1) <SEP> bits <SEP> to <SEP> the <SEP> left <SEP> of
<tb> Rd, <SEP>&num; imm, <SEP> ZONC <SEP> register <SEP> Rd. <SEP> The <SEP><SEP> selected <SEP> indicators are <SEP> set <SEP> to <SEP> day
<tb> The <SEP> C <SEP> Maker <SEP> is the <SEP> denver <SEP> btt <SEP> output
<Tb>

<Desc / Clms Page number 57>

<Tb>
<tb> LSR <SEP> Rd, Rs, ZONC <SEP> 101110zoncsssddd <SEP> Offset <SEP> Logic <SEP> From <SEP> Rs <SEP> Bit <SEP> (modulo <SEP> 16) <SEP> To <SEP> the <SEP> right
<tb> of <SEP> registry <SEP> Rd. <SEP> The <SEP><SEP> selected <SEP> indicators are <SEP> set <SEP> to
<tb> day. <SEP> The <SEP> C <SEP> flag equals <SEP> at the <SEP> last <SEP> bit <SEP> output
<tb> LSR <SEP> 101111zonciiiddd <SEP> Logical <SEP> Offset <SEP> of <SEP> (imm + 1) <SEP> bits <SEP> to <SEP> The <SEP><SEP><SEP>
<tb> Rd, &num; imm, ZONC <SEP> register <SEP> Rd. <SEP> The <SEP> selected <SEP><SEP> indicators are <SEP> set <SEP> to <SEP> days.
<Tb>

The <SEP> C <SEP> flag is <SEP> to the last <SEP> last <SEP> bit <SEP>.
<Tb>
In the encoding of a jump instruction: 'j' designates an encoding bit of the jump condition, and 'p' denotes a coding bit of the relative jump address in the program.

<Tb>
<Tb>

<SEP><SEP><SEP><SEP> Separation Instructions
<tb> Jcc <SEP> move <SEP> 11jjjjppppppppp <SEP> Jump, <SEP> Relative <SEP> to <SEP> the following <SEP> statement, <SEP> to <SEP> a <SEP> word <SEP > from
<tb> program. <SEP> The <SEP> move <SEP> allowed <SEP> is <SEP> from -512 <SEP> to <SEP> +511
<tb> words <SEP> of instructions.
<Tb>

The <SEP><SEP><SEP><SEP> conditions can <SEP> be <SEP> the following <SEP><SEP>:
<tb> Condition <SEP> Encoding <SEP> Details <SEP> of <SEP> The <SEP><SEP><SEP> condition
<tb> (cc) <SEP> (ÜÜ)
<tb> AC <SEP> 0000 <SEP> Z = 0
<tb> ZS <SEP> 0001 <SEP> Z = 1
<tb> CC <SEP> 0010 <SEP> C = O
<tb> This
<tb> NC <SEP> 0100 <SEP> N = 0
<tb> NS <SEP> 0101 <SEP> N = l
<tb> OC <SEP> 0110 <SEP> 0 = 0
<tb> OS <SEP> 0111 <SEP> 0 = 1
<tb> UG <SEP> 1000 <SEP>><SEP> (no <SEP> Signed) <SEP>: <SEP> C = 0 <SEP> and <SEP> 2 = 0
<tb> ULE <SEP> 1001 <SEP><SEP> (no <SEP> Signed) <SEP>: <SEP> C = <SEP> or <SEP> 2 = 1
<tb> SG <SEP> 1010 <SEP>><SEP> (signed) <SEP>: <SEP> 2 = 0 <SEP> and <SEP> N = O
<tb> SGE <SEP> 1011 <SEP> (signed) <SEP>: <SEP> N = O
<tb> SL <SEP> 1100 <SEP><<SEP> (signed) <SEP>: <SEP> N <SEP>;<SEP> toO
<tb> SLE <SEP> 1101 <SEP><<SEP> (signed) <SEP>: <SEP> Z = 1 <SEP> or <SEP> N # O
<tb> NCS <SEP> 1110 <SEP> N = I <SEP> and <SEP> C = I
<tb> MP <SEP> 1111 <SEP> Always
<Tb>
10.2.2.3 - How to run a coprocessor program

<Desc / Clms Page number 58>

 When starting the zero level machine, each "TREE" block 29 is installed in memory.

The data memory space required for the coprocessor programs of each "TREE" block 29 is allocated, and the words of this space are initialized with the value 0.

The set of coprocessor programs of the same block "TREE" 29 are considered to be put end to end, so that they can, if necessary, jump to portions of code coprocessors programs not belonging to their branch . They therefore share the same memory space programs.

When a level 0.4 program traverses the tree to access a device, it must first run the authorization program of the current node to check if the path is valid. If this is the case, then the route program can be executed with possibly a parameter transmitted via the registers RO to R7. The branch is then considered as traveled. The process can be repeated on the following nodes until reaching a leaf of the tree.

To execute a coprocessor program, the program of level 0. 4 uses the emulator t> ZD 33 of the coprocessor of peripherals 28 by supplying it the exact location of the program and data memories of the coprocessor program. Before passing a possible parameter, the registers RO to R7 and the status indicators are in an indeterminate state each time a new coprocessor program is started.

When the coprocessor program is terminated (by encountering the EOP instruction), the program of level 0.4 retrieves a termination code in the register R7 (and possibly other parameters in the other registers).

la valeur"$FFFE"indique une directive d'élagage dont le nombre d'autorisations d'accès restant est supérieur ou égal à"$FFFE". If it is an authorization program, the values of the termination code have the following conventional meaning: "0" means the prohibition of access to the node, "$ FFFF" means an unconditional authorization, the values "I" to "$ FFFD" indicates a pruning directive, that access is only allowed for the specified number of times, and

the value "$ FFFE" indicates a pruning directive whose number of access permissions remaining is greater than or equal to "$ FFFE".

If it is a course program, the value 0 indicates a success of the course. Any other value indicates an error number made available at level 0.4.

10. 2.2. 4-Insert coprocessor programs in the tree Each coprocessor program is inserted into the binary description of the node for which it is designed. A coprocessor program can be inserted only in the nodes of the device tree belonging to a device "space" ("space", "dimension", "coordinate" or "intensity"). There can only be one course program and one program

<Desc / Clms Page number 59>

 per node, and each node of a device "space" may contain none, either, or both programs. The absence of an authorization program indicates that the path of the node concerned is still authorized. The node representing space can additionally contain the interrupt program, there can only be one interrupt program for a device "space." The absence of an interrupt program means that the device is not able to trigger an interrupt.

 1 0. 2, 3 - "LINK" blocks 26 A "LINK" block 26 is specific to a support machine 23 and the device for which it is designed. It consists of four subroutines provided for interfacing with the mapping / enumerator 25: an initialization, a read, a write and an interrupt detection. The first three subprograms must be able to be called from the cartographer / enumerator 25, with possible transmission of parameters during their call or on their return.

The first is responsible for initializing the device that it has control in order to place it in a known state for its use. In this state, the device is ready for operation, but should not trigger a zero level machine interrupt.

The second and the third are responsible for establishing the link between the device of the support machine 23 and the zero level machine. The second returns data directly or indirectly from the device to the zero level machine via the mapmaker / enumerator 25. The third retrieves data from the zero level machine via the mapmaker / enumerator 25. and send it directly or indirectly to the device.

The fourth routine is installed but disabled by the initialization routine, and calls the mapping / enumerator 25 if an interrupt is triggered by the device to be taken into account. It is activated by the path coprocessor program of the node representing "space".

A "LINK" block 26 must have a data exchange protocol with its sub-programs, compatible with the protocol of the coprocessor programs of the associated "TREE" block 29.

All the "LINK" blocks 26 corresponding to a particular support machine 23 must follow the same conventions of interface with the cartographer / enumerator 25 (example: locating and calling the four subroutines, passing parameters, etc.).

10.2. 4-The "TREE" blocks 29 A device "space" is encoded in a "TREE" block 29 in the form of a sequence of 16-bit words whose organization reflects the hierarchy of the nodes in "space". describe this organization, certain notions are essential.

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10. 2.4. 1 - Notions prior to the encoding of the "TREE" blocks 29 A "TREE" block 29 is a succession of "fields" of data. A field is a group of words participating in the expression of the same information. Any data field is organized in a particular format.

A 16-bit word alone can only express limited amplitude values. Some values included in the description of a "TREE" block 29 can not be expressed in 16 bits only. A fixed-size data field for the expression of values is not suitable because it may be too small in some cases, or take up a useless place to represent low values. Thus, to reconcile a minimum memory occupation with a coding width that may be important, certain values are encoded as a variable size field. We speak of "gradual coding".

Each elemental characteristic corresponds to a "coordinate". Some basic features can be classified into large physical or symbolic types. The type of an elementary characteristic is encoded in the field representing the corresponding "coordinate" node.

Device modeling often leads to sets of nodes of the same hierarchical level (example: "intensities") and of the same type. Rather than encode each node individually, we use factorizing encoding, in order to save memory. We are talking about "node repetition".

In some cases, different devices modeled separately have interdependent operation: we speak of "interdependent peripherals". It is therefore necessary to present these devices in a single "TREE" block 29 so that the coprocessor programs can share the same data memory and thus manage this interdependence.

10.2. 4. 2-Formats of the basic fields These fields are frequently used in the description of the nodes of the "TREE" blocks 29.

Numbers We distinguish two categories of numbers: simple numbers and "gradual" numbers.

A gradual number can take two special values: the infinite and the unknown number.

A simple number is a positive value between 0 and 65535. It is directly encoded in a SIMP field of a size of a word.

Une valeur positive susceptible de ne pas pouvoir être encodée par un nombre simple est représentée par un nombre graduel, encodé dans un champ"GRAD"occupant plusieurs mots. Ce champ est composé d'un mot indiquant le nombre de fenêtres (i. e. le nombre de mots de 16 bits) | SIMP field value

A positive value that may not be encoded by a simple number is represented by a gradual number, encoded in a "GRAD" field occupying several words. This field consists of a word indicating the number of windows (ie the number of 16-bit words)

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 on which is encoded the value. The words representing this value follow from the word of greatest weight to the word of least weight.

If the word representing the number of windows is $ FFFF, then the number is considered infinite. Similarly, if this word is 0, then the number is considered unknown: its value is variable and may be determined by some other means. In both cases, the GRAD field contains only this word.

succession des mots constituant le programme coprocesseur. Le mot suivant le dernier mot du programme prend la valeur réservée $6FFF, indiquant la fin du champ.

Number of Window Window Wt Wt Low GRAD Field Coprocessor Programs A coprocessor program is encoded in a field called "PCP". This field is the

succession of words constituting the coprocessor program. The word following the last word of the program takes the reserved value $ 6FFF, indicating the end of the field.

Le champ PCPA représente un programme d autonsatton, te champ PCPP représente un programme de parcours, et le champ"PCPI"représente un programme d'interruption. 11er 2 """'word ... Last word $ 6FFF PCP field' -

The PCPA field represents a program of autonsatton, the field PCPP represents a program of course, and the field "PCPI" represents an interrupt program.

un champ appelé"TYP"occupant un mot de 16 bits. Les 8 bits de poids fort du mot indiquent la grande catégorie du type, les 8 bits de poids faible précisent cette catégorie. Physical or symbolic types The "coordinate" nodes indicate the physical or symbolic type of the elementary characteristic that they represent. A type is encoded by a conventional value stored in

a field called "TYP" occupying a 16-bit word. The 8 most significant bits of the word indicate the big category of the type, the 8 bits of low weight specify this category.

The table below shows the coding of the main categories and subcategories.

Code category 0 indicates an unknown type. A subcategory of code 0 indicates that only the category is known.

<Tb>
<Tb>

Physical <SEP> Category <SEP> or <SEP> Subcategory <SEP> Encoding
<tb> symbolic
<tb> Time <SEP> $ 0101
<tb> Space <SEP> X <SEP>: <SEP> horizontally <SEP> by <SEP> report <SEP> to <SEP> the observer <SEP> $ 0201
<tb> Y <SEP>: <SEP> vertically <SEP> by <SEP> report <SEP> to <SEP> the observer <SEP> $ 0202
<tb> Z <SEP>: <SEP> perpendicular <SEP> to <SEP> plan <SEP> set <SEP> with <SEP> X <SEP> and <SEP> Y <SEP> $ 0203
<tb> AX <SEP>: <SEP> variation <SEP> of <SEP> position <SEP> according to <SEP> X <SEP> $ 0211
<tb> AY <SEP>: <SEP> variation <SEP> of <SEP> position <SEP> according to <SEP> Y <SEP> $ 0212
<tb>#Z<SEP> variation <SEP> of <SEP> position <SEP> according to <SEP> Z <SEP> $ 0213
<tb> Information <SEP> digital <SEP> Storage <SEP> in <SEP> read <SEP> $ 0301
<Tb>

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<Tb>
<tb> Storage <SEP> volatile <SEP> in <SEP> read / write <SEP> $ 0302
<tb> Storage <SEP> no <SEP> volatile <SEP> in <SEP> lecrease / write <SEP> $ 0303
<tb> Transfer <SEP> in <SEP> read <SEP> $ 0310
<tb> Transfer <SEP> to <SEP> Write <SEP> $ 0311
<tb> Electro-Magnetic <SEP> Wave <SEP> Adding <SEP> a <SEP> Spectrum <SEP> Luminous <SEP> $ 0401
<tb><SEP> Filtering of a <SEP> Spectrum <SEP> Bright <SEP> $ 0440
<tb> Issuing <SEP> of <SEP> Red <SEP> $ 0402
<tb><SEP> Issue of <SEP> Green <SEP> $ 0403
<tb> Issuing <SEP> of <SEP> blue <SEP> $ 0404
<tb> Filtering <SEP> cyan <SEP> $ 0441
<tb> Filtering <SEP> magenta <SEP> $ 0442
<tb> Filtering <SEP> yellow <SEP> $ 0443
<tb> Filtering <SEP> Black <SEP> $ 0444
<tb> Vibration <SEP> in <SEP> a <SEP> Medium <SEP> Sound <SEP> $ 0501
<tb> hardware
<tb> Manipulation <SEP> of <SEP> material <SEP> Adding <SEP> of <SEP> material <SEP> $ 0601
<tb> Remove <SEP> from <SEP> Matter <SEP> $ 0602
<tb> Character <SEP> cu <SEP>! <SEP> ture <SEP>! <SEP> or <SEP> ASCH <SEP> 7 <SEP> bits <SEP> $ 0701
<tb> symbolic <SEP> UNICODE <SEP> $ 0702
<tb> Characteristic <SEP> symbolic <SEP> Code <SEP> of error <SEP> $ 0801
<tb><SEP> keys of <SEP> keyboard <SEP> $ 0802
<tb><SEP> button $ 0901
<Tb>

Type Champ TYP dz

Identificateur d"'hyperespace" Le numéro identifiant l "'hyperespace" auquel appartient un"espace"est encodé par un champ "HYP"d'une taille de un mot. Un champ HYP prend la valeur : "$FFFF"pour f'hyperespace"des périphériques d'échange en sortie.

Type Field TYP dz

Hyperspace identifier The number identifying the "hyperspace" to which a "space" belongs is encoded by a "HYP" field of a size of a word. A HYP field takes the value: "$ FFFF" for the "hyperspace" of the output exchange devices.

"$ 8000" for hyperspace "input exchange devices.

"0" for the "hyperspace" of non-addressable storage devices.

"I" for the "hyperspace" of addressable preservation devices.

Fin de descnption d'''espace''de périphérique ? d "hyperspace" Field HYP yperespace "

End of 'peripheral' space clearance

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The field "FEP", of a size of a word, indicates the end of a succession of descriptions of nodes (end of a field EP).

Le champ"CRC", d'une taille de un mot, représente une somme de contrôle permettant de vérifier l'intégrité d'un bloc "TREE" 29.

$ FFFF Field FEP / Checksum

The field "CRC", of a size of a word, represents a checksum making it possible to check the integrity of a block "TREE" 29.

10. 2. 4. 3-Formats des champs encodant les noeuds Les noeuds représentant un"espace", une"dimension", une"coordonnée", ou une"intensité"sont encodés dans des champs spécifiques. Checksum CRC Field --- Yi

10. 2. 4. 3-Formats of the fields encoding the nodes The nodes representing a "space", a "dimension", a "coordinate", or an "intensity" are encoded in specific fields.

Each field representing a node starts with an "ENT" field. Such a field includes a word "RNH", possibly followed by a GRAD field. The three least significant bits of the word RNH, called "NH", identify the hierarchical level of the node. If the most significant bit "R" of the word RNH is raised, then the described node is repeated. The other bits of the word RNH must be dropped. The GRAD field appears only if the node is repeated. It corresponds to the number of repetitions of the field representing the repeating node.

Format du champ NI représentant un noeud"intensité". OOOOOOOOOOOOONH Field ENT representing a node nonet IOOOOOOOOOOOONH GRAD 1 Field ENT representing a necu ,,, "intensity"

NI field format representing an "intensity" node.

NH = 0 in the ENT field.

ENT PCPA PCPP NI Field "V" "coordinate" Format of the NC field representing a "coordinated" node.

NH = 1 in the ENT field.

Format du champ ND représentant un noeud"dimension". ENT ITYP IPCPA PCPP NC field "dimension"

Format of the ND field representing a "dimension" node.

NH = 2 in the ENT field.

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Format du champ NE représentant un noeud"espace". ENT PCPA PCPP ND field "space"

Format of the NE field representing a "space" node.

* NH = 3 in the ENT field.

ENT HYP PCP! PCPA PCPP Field NE 10. 2. 4. 4-Encoding Device Set "" "Space" Peripheral "" device "nodes are described one after the other in order of routing of the tree commonly called "deep first". Figure 16 shows the first step in depth of an example device "space". The numbers indicate the order in which the nodes are encountered.

The nodes of "dimensions", "coordinates" and "intensities" should if possible be presented in a conventional order.

The ordered description of all the nodes of a device "space" is a field named "EP", terminated by a "FEP" field.

Un bloc "TREE" 29 comporte un en-tête"EBT", un champ NS indiquant le nombre d''espaces" de périphériques, la description du ou des "espace (s) " de périphérique (s) interdépendant (s) EP, et enfin une somme de contrôle CRC calculée sur l'ensemble du bloc "TREE" 29, et permettant de vérifier l'intégrité des données du bloc. NE (1) ND (2) NC (3) NI (4) NI (5) NI (6) NC (7) NI (8) NI (9) ND (IO) NC (II) NC (12) NC 1 3) FEP BRamp EP corresponding to the example of FIG. 16 10. 2. 4. 5-Encoding a TREE Block 29

A "TREE" block 29 comprises an "EBT" header, an NS field indicating the number of "spaces" of peripherals, the description of the "space (s)" of the interdependent peripheral device (s). , and finally a CRC checksum calculated over the entire block "TREE" 29, and to verify the integrity of the block data.

bits de poids faible contiennent l'exposant P de la puissance de 2 indiquant la taille de la mémoire données qui doit être réservée pour l'exécution des programmes coprocesseurs du bloc. Ces 5 bits peuvent prendre les valeurs 0 à $10. La valeur $1 F signifie que la mémoire données est absente.

The EBT header is a field of a size of a word whose! most significant bits are initialized with the binary standard value 1010 1011001, making it possible to identify a block "TREE" 29. The 5

bits of low weight contain the exponent P of the power of 2 indicating the size of the data memory which must be reserved for the execution of the coprocessor programs of the block. These 5 bits can take the values 0 to $ 10. The value $ 1 F means that the given memory is missing.

Le champ NS vaut ! a ptupart du temps 1 car les périphériques interdépendants sont très peu fréquents. La valeur 0 est interdite pour NS. Le format d'un bloc "TREE" 29 est le suivant. I lool lp: 1 EBT field <V

The NS field is worth! over time 1 because interdependent devices are very infrequent. The value 0 is forbidden for NS. The format of a "TREE" block 29 is as follows.

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Le cartographe/énumérateur 25 fait partie, avec l'émulateur du processeur de niveau zéro et les blocs "LINK" 26, des trois modules que l'on doit obligatoirement programmer pour la machine support 23 afin d'obtenir une machine de niveau zéro fonctionnelle. La création des blocs "TREE"29 correspondant (et éventuellement des blocs"FEXT") est également à faire si les périphériques de la machine support 23 n'ont jamais été modélisés. &verbar; EBT l NS &verbar; EP &verbar; - &verbar; EP &verbar; CRC IEBT INS EP ... EP CRC Block! 0. 2. 5-The cartographer / enumerator 25

The cartographer / enumerator 25 is, together with the emulator of the zero level processor and the "LINK" blocks 26, of the three modules that must be programmed for the support machine 23 in order to obtain a functional level zero machine. . The creation of corresponding "TREE" blocks 29 (and possibly "FEXT" blocks) is also to be done if the peripherals of the support machine 23 have never been modeled.

Universelle. Il établi le lien entre le registre "MER" 27 (et l'interruption de la machine 21 de niveau 0.4) d'une part et les blocs "LINK" 26 et "TREE" 29 d'autre part. 10. 2.5. 1-Principle of operation Cartographer / Enumerator 25 is the basis of the Machine's Device Management System

Universal. It establishes the link between the register "MER" 27 (and the interruption of the machine 21 level 0.4) on the one hand and the blocks "LINK" 26 and "TREE" 29 on the other hand.

The cartographer / enumerator 25 performs several functions: it installs the "LINK" blocks 26 on the support machine 23, including its own "LINK" block 26 allowing it to be reset (by calling the initialization routine). It calls the initialization subprograms of these blocks; it provides level zero programs with four commands allowing access to the "LINK" blocks 26, plus a command that transmits the contents of the "TREE" blocks 29 available on the support machine 23 to the zero level machine; it manages the requests for interrupts sent by the peripherals via the "LINK" blocks 26 and transmits them to the zero level machine at the request of the latter.

10.2. 5. 2 - Detailed Operation The zero level machine and the mapmaker / enumerator 25 interact exclusively through the "MER" register 27 (and the interrupt mechanism at level 0. 4). A zero-level program must adhere to the command usage protocols, otherwise the exception will be thrown.

When a command from the cartographer / enumerator 25 is in progress, it must first be terminated in order to execute another command. Only the exception can interrupt an order at any time. When the cartographer / enumerator 25 does not execute a command, he waits for a command number to be executed and can transmit on request of the zero level program the number of a device having requested an interruption.

When the cartographer / enumerator 25 transmits the number of the device causing an interruption by the "MER" register 27, an interrupt is triggered at level 0.4. When no interrupt is pending, the transmitted number is $ FFFF (and no interrupt is triggered at level 0.4).

The five accessible commands are:

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 the initialization of the "LINK" block 26 selected (command 0), the selection of a "LINK" block 26 (command 1), the writing of a word to the selected "LINK" block 26 (command 2), the reading of a word from the block "LINK" 26 selected (command 3), and reading blocks "TREE" 29 (command 4).

cartographe/énumérateur 25 numérote chaque bloc "TREE" 29 envoyé en partant de 1 et en z ajoutant 1 à chaque nouveau bloc "TREE" 29 envoyé. La valeur 0 désigne systématiquement le cartographe/énumérateur 25 lui-même. On execution of the read command of the blocks "TREE" 29, the cartographer / enumerator 25 then presents the blocks "TREE" 29 one after the other, cut into slices of 128 words. Each slice begins with a word indicating whether the slice is the first of a "TREE" block 29 ($ DEBE code) or not ($ CEAB code), or if the last slice of the last "TREE" block 29 has been returned (code $ FEDB). Any other value for this word is prohibited. The

Cartographer / Enumerator 25 numbers each "TREE" block 29 sent starting from 1 and adding 1 to each new "TREE" block 29 sent. The value 0 consistently designates the cartographer / enumerator 25 itself.

When starting the zero level machine, the zero device (cartographer / enumerator 25) is selected by default.

10. 2. 5. 3-Algorithm of operation The cartographer / enumerator 25 is composed of five subroutines, called by the emulator of the processor of level zero or by the blocks "LINK" 26.

Initialization: MAXPERIPH <-0 Assignment of a first base address in the memory of the support machine 23.

For each detected LINK block (up to 32767 LINK blocks) MAXPERIPH <-MAXPERIPH + 1 From the LINK block base installation address in the memory of the support machine 23: MAXPERIPH Backup Saves the address of the LINK block subprogram of the Cartographer / Enumerator that the LINK block must call in the event of an interruption (queuing).

Read the LINK block Call the LINK block initialization subroutine If the initialization failed MAXPERIPH f- MAXPERIPH - 1 Otherwise Save the base address in the LINK block list (located in the address space of the LINK block the support machine 23).

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 Save the identifier in the list of LINK blocks (example: the name of the file containing the LINK block).

Assignment of a new base address in the memory of the support machine 23.

Réinitialisation : ETAPE < -0 {Etat par défaut : attente de commande} Ferme un éventuel bloc "TREE" 29 ouvert par la commande 4. NUMPERIPH <-0 (Return of subroutine)

Reset: STEP <-0 {Default state: wait for command} Closes any "TREE" block 29 opened by command 4.

(Subroutine return) Pending interrupt backup {Subroutine called by "LINK" 26 on interrupt.} Addition of the interrupt number in the queue of pending interrupts.

(Return of subroutine) Reading: If STEP = 0 {Waiting for command} If an interrupt is present in the queue MER e Number of the first device of the interrupt queue.

 Remove the processed interrupt from the queue.

In the case of a level 0.4 processor: interrupt jump
If not
SEA # $ FFFF If STEP = 1
If COMMAND <3
Jump to Exception If COMMAND = 3 "MER" 27 receives the value returned by the input subroutine of "LINK" 26 n NUMPERIPH STEP <-0
If COMMAND = 4
If PREMIERE = 1
If NUMLINK> MAXPERIPH
SEA # $ FEDB
STEP 0
Otherwise Open the "TREE" block 29 associated with the "LINK" block 26 nONUMLINK (by its identifier)
TREEOFFSET <-1

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NUMLINK -NUMLINK + 1
PREMIERE ex
Sinon TREEOFFSET 0 (retour de sous-programme) Ecriture : Si ETAPE = 0 {Attente de commande}
COMMANDE # MER {Méorise le numéro de commande}
Si COMMANDE > 4 {Commande inexistante}
Saut à l'exception Si COMMANDE = 0
Appel au sous-programme d'initialisation du "LINK" 26 n NUMPERIPH
Si COMMANDE = 4 NUMLINK # 1 {Numéro du bloc "LINK" 26 dont le bloc "TREE" 29 associé est en cours d'envoi} PREMIERE # 1 {Première tranche du bloc "TREE" 29 à envoyer}
Si COMMANDE > 0
ETAPE # 1 Si ETAPE = 1
Si COMMANDE > 2 Saut à l'exception Si COMMANDE = 1 {Changer de numéro de périphérique courant}
Si MER > MAXPERIPH
Saut à l'exception FIRST # 0 SEA # $ DEBE Else if TREEOFFSET = 0
TREEOFFSET # 1 SEA # $ CEAB Otherwise
MER <-Next word in the block "TREE" 29 open
If TREEOFFSET <128
TREEOFFSET e TREEOFFSET + 1
If not
If End of block TREE
Close the TREE block

NUMLINK -NUMLINK + 1
FIRST ex
Otherwise TREEOFFSET 0 (subroutine return) Write: If STEP = 0 {Waiting for command}
COMMAND # MER {Crates the order number}
If ORDER> 4 {Non-existent order}
Jump to the exception if COMMAND = 0
Calling the LINK initialization subroutine 26 n NUMPERIPH
If COMMAND = 4 NUMLINK # 1 {Number of the "LINK" block 26 whose associated "TREE" block is being sent} FIRST # 1 {First block of the "TREE" block 29 to be sent}
If ORDER> 0
STEP # 1 If STEP = 1
If COMMAND> 2 Exceeds if COMMAND = 1 {Change current device number}
If MER> MAXPERIPH
Jumping except

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(retour de sous-programme) ZD 10. 3 - Fonctions évoluées sur les périphériques 10.3. !-Méthode générale d'accès aux périphériques en niveau zéro via l'arbre Pour gérer un périphérique, il faut d'abord charger en mémoire le bloc "TREE" 29 qui le représente en utilisant la commande de lecture des blocs "TREE" 29 du cartographe/énumérateur 25. On sauvegarde alors le numéro d'identification qui a été attribué au bloc par le cartographe/énumérateur 25.

Otherwise NUMPERIPH e SEA STEP 0
If COMMAND = 2 Sending the value contained in "MER" 27 to the output subroutine of "LINK" 26 nO NUMPERIPH STEP <-0

(subroutine return) ZD 10. 3 - Advanced Features on Devices 10.3. ! -General method for accessing devices at zero level via the tree To manage a device, it is first necessary to load in memory the "TREE" block 29 that represents it using the "TREE" block reading command. From the cartographer / enumerator 25. The identification number assigned to the block by the cartographer / enumerator 25 is then saved.

It is then possible to analyze the structure of the tree (s) included in the "TREE" block 29 or to refer to the "FEXT" block to determine the type of function performed by the device.

When the device performing the desired function has been identified, it can then be used. According to the hyperspace "to which belongs the space" describing the device, the permitted operations are different: in the case of a "hyperspace" of exchange output, one can only send data to the device, in the case of a "hyperspace" exchange input, we can only receive data from the device, in the case of an "hyperspace" addressable conservation, no operation is allowed since the device is directly accessible by t address space of the machine; In this case, the "space" of this device is only there to indicate the characteristics of the device, and in the case of a non-addressable "hyperspace" of conservation, the permitted operations can be the sending and / or the receiving data.

10.3. 1. 1-Sending data to a device by route of the tree The sending of data is performed by traversing the tree according to the data that the programmer wishes to transmit to the device. The coprocessor programs of each node are responsible for converting each step of the path to correct configuration and operating data transmitted to the device.

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The sending process consists firstly of locating the "space" node at the base of the tree. The authorization coprocessor program must be run. If the authorization is given, then we execute the path program of the node. We then look for the "dimension" nodes attached to this "space" node, and we apply the same procedure to the chosen "dimension" node. The process continues, and ends when the coprocessor program of a node of 'intensity' has been executed: faction corresponding to the path of the tree has been made.

10. 3. 1. 2 - Receiving data from a device by tree path Data reception is performed by traversing the tree according to the instructions returned by the coprocessor programs of each node. Some nodes contain programs that ask the device for the operating data: they convert it into a coherent path of the tree resulting in an "intensity" node representing the received value. The course of other nodes makes it possible to memorize possible parameters in order to select operating data when several are proposed (example: to choose a particular pixel in an image coming from a digital video camera).

The reception process consists firstly of locating the 'space' node at the base of the tree. The authorization coprocessor program must be run. If the authorization is granted, one reads data returned by this program, identifying the role of the node.

If you want to read a given one of a set, we first browse the nodes to store the location parameters of this data (example: choose the horizontal and vertical positions of a pixel). Once the possible location has been completed, the nodes are scanned to be guided to the "intensity" node corresponding to the value received from the device.

10. 3. 2-Examples of instruction sequences 0.4 emulating the instructions of the coprocessor 28 The processor of level 0.4 is responsible for emulating the instructions of the coprocessor of peripherals 28. This emulation is carried out by a complete program, which is not shown. here only a few sequences reproducing certain operations.

For the following instruction sequences, we consider that: the address ranges $ 100 to $ IFF contain values ranging from $ FFOO to $ FFFF, the address ranges $ 200 to $ 2FF contain values ranging from $ 0000 to $ OOFF , the address ranges $ 300 to $ 3FF contain values ranging from $ OOFF to $ FFFF, in increments of $ 100, Rd and Rs are addresses containing the operands Rd and Rs as described for the coprocessor instructions 28, and tmp and tmp2 are any two rewritable memory addresses.

10.3. 2. 1-Sequence reproducing the logical OR AND $ 200

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AND R SBB AND Rs SBBtmp ST tmp LD Rd AND Rs ST tmp2 LD $1 FF SBB tmp2 AND tmp ST Rd (A ce stade la retenue est annulée) 10.3. 2. 3-Séquence reproduisant le chargement d'une valeur immédiate dans un registre On considère le chargement d'une valeur immédiate positive $0ijk (j et k étant des chiffres hexadécimaux quelconques, i étant un chiffre hexadécimal valant 0 ou 1). SBB Rd ST tmp SBB SBR $ 201 AND Rs SBBtmp ST Rd (At this point the hold is undefined, an "AND R" statement can be inserted to clear it) 10.3. 2. 2-Sequence reproducing the exclusive logical OR AND $ 200 SBB Rd STmtp

AND R SBB AND Rs SBBtmp ST tmp LD Rd AND Rs ST tmp2 LD $ 1 FF SBB tmp2 AND tmp ST Rd (At this point the holdback is canceled) 10.3. 2. 3-Sequence reproducing the loading of an immediate value in a register One considers the loading of a positive immediate value $ 0ijk (j and k being any hexadecimal digits, i being a hexadecimal digit worth 0 or 1).

LD $ 30i AND $! jk ST Rd (At this stage the hold is canceled) 10. 3. 2. 4-Sequence reproducing the backup of a register to the memory We consider any memory address of binary value% abcdefghij. It is considered that the register MP contains the address of the last word of the address space of the coprocessor 28, and that this address space is aligned on a page of 8 Kb in zero-level memory.

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LD Rs ST &% 000abcdefghij (Holdback remains unchanged)
10.3. 2. 5-Sequence Reproducing the Unrestrained Addition AND $ 200 SBB Rd Tmp AND R LD Rs SBBtmp ST Rd (At this point the holdback is undetermined) 10. 3. 2. 6-Sequence Reproducing Unrestrained Subtraction AND R LD Rd SBB Rs ST Rd (At this stage the restraint is positioned according to the result of the subtraction) 10.3. 2. 7-Sequences reproducing the update of the status indicators (N, Z, 0 and C) Each indicator is saved in zero-level memory in a word whose value 0 means that the indicator is lowered, and of which the value $ FFFF means that it is raised.

The addresses containing the N, Z, 0 and C indicators are named NCOP, ZCOP, OCOP, and CCOP respectively.

We call "res" the address containing the result of the last operation.

At the output the restraint is positioned according to the value of the indicator that has been calculated.

Indicator N Update (If the holdback is not canceled: AND R) LD $ 37F SBB SBB R R ST NCOP Update Z Indicator AND $ 200 SBB SBB R SBB $ l FE

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 SBB R ST ZCOP Update indicator 0 The algorithm for updating indicator 0 is different according to the instructions. Here we give the example of the update of the indicator 0 in the unrestrained subtraction instruction.

LDRs AND $ 37F ST LD SB tmp and $ 37F SBB tmp SBB R ST tmp R AND Rd SBB Rd Rs ST SBB Rd R (ST CCOP if the C indicator must also be updated) AND R SBB ST tmp tmp AND $ 200 SBB tmp SBB R ST OCOP Updating indicator C The algorithm for updating the indicator C differs according to the instructions. Two examples are given here.

Example of the update during the unrestrained subtraction instruction: AND R LD Rd SBB Rs STRd SBB R ST CCOP

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 Example of the update during the unrestrained addition statement: AND $ 200 SBB Rd ST SBB R SBB R $ 200 ST tmp2 LD Rs SBBtmp ST Rd SBB R SBB tmp2 SBB R ST CCOP 10. 3. 3-Contents "FEXT" blocks A "FEXT" block contains a set of optional information that supplements that provided by the associated "TREE" block 29.

A "FEXT" block may contain one or more of the following: the actual modeling data provides equations or other types of information that accurately define the physical, symbolic, and logical relationships that the branches of the device tree maintain between they and the real world, so-called "perceptual modeling" data, providing equations or other types of information precisely defining the physical relationships between the physical limit of interaction of the device with the outside world and the transmitter / recipient of the information.

For example, one may wish to model how a valid human being, or on the contrary having eye problems, perceives the colors produced by a screen, and a specific coprocessor program, called "rapid traverse program", replacing the coprocessor programs. some nodes of the associated "TREE" block 29. This program makes it possible to access the device in an optimized manner in terms of speed according to a predefined and invariable tree path which must be explained in the "FEXT" block.

10.3. 4-Self-adaptation of devices 10. 3.4. -Definition and uses For a device "A" given, not available on the machine support 23, the self-adaptation of the Universal Machine is a software mechanism that allows: firstly to find the device "B" available on the support machine 23 and fulfilling the function as close as possible to that of the device A,

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 on the other hand to adapt the data stream initially processed by the device A in a different data stream, processed by the device B, and which will give a result as close as possible to what it would have been if it had been directly processed by the A device.

The process of self-adaptation is based on a philosophy contrary to that usually adopted for the management of peripherals: it is the machine that complies with the requirements of the programmer. The latter offers a type of device with a precise operating data format and the machine gives it access to the device as close as possible to its request, if necessary by adapting "on the fly" the data flows exchanged. In the event of an unexpected change in the state of a device (failure, shutdown) the machine can automatically search for a way to redirect information to or from the nearest device. There is therefore automatic adaptation of the virtual machine to the hardware environment.

10.3. 4. 2-Principle of operation One begins by analyzing the structure of space "describing the device A, in particular the hyperspace" to which it is attached, as well as the number and the type of the nodes of "dimension", of "coordinate "and" intensity ".

We then browse all the "spaces" of available devices and we look for the one with the closest tree structure. The evaluation of the proximity of two tree structures is based on very selective comparison algorithms (a strictly identical structure is sought) with allocation of one or more coefficients expressing the similarity between each device "space" analyzed and The tolerance of these algorithms is then modulated by prioritizing some parameters over others, and by grouping or ignoring certain parameters that are considered to contribute little to the function of the device. The "space of device B with the strongest similarity coefficients with the space" of device A is retained.

When the "space" A (source) and 1 "space (destination) are known, a conversion algorithm is generated, in order to take the directions of the tree of 1" space and convert them at best The algorithm is based on the number and type of nodes in each "space", and groupings or priorities established in the search for similarity. also on the "FEXT" blocks as well as on a database listing standard algorithms allowing conversions between different physical and symbolic types.

10. 3.4. 3-Program responsible for these operations The self-adaptation mechanism is implemented by a program responsible for performing the operations of comparison and conversion between peripherals. This program is called "scout" (or "pathfinder"), it is written for a given level of the Universal Machine and does not

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 does not operate autonomously for this level: it is the other programs of the level that will have to use them if needed. Programs written for a higher level will use these features transparently, if the emulator at that higher level uses scout for device management.

 This program is the most complex part of the device management, but its presence is absolutely not essential to exploit the devices. All applications do not need a self-adaptation of devices.

When an application needs a device that performs a particular function and does not want to search for it by itself (or it can not find a device that matches its needs), it can call the scout by transmitting the profile of the searched device. The scout takes care of finding the best device and becomes the exclusive interlocutor of the application for all transmissions with the device.

10. 3. 5-Definition of reserved zones of the address space of level 0.4 The following table presents the data fields associated with the address ranges reserved for them.

<Tb>
<Tb>

<SEP> Ranges of Reserved <SEP> Addresses <SEP><SEP><SEP> Data Fields
<tb> (denoted <SEP> in <SEP> hexadecimal)
<tb> 0000 <SEP><SEP> 0 <SEP> Window of <SEP><SEP><SEP><SEP> Return Address of <SEP> or <SEP> Exception of Exception
<tb> 0001 <SEP> - <SEP> 003F <SEP> Program <SEP> of <SEP> Management <SEP> of <SEP> Interrupt
<tb> 0040-007E <SEP> Variables
<tb> 0080-008F <SEP> Address <SEP> Maximum <SEP> Addressable <SEP> (at <SEP> format "big <SEP>endian"),<SEP> in <SEP>
<tb> limit <SEP> of <SEP> 16 <SEP> windows
<tb> 0090-009E <SEP><SEP><SEP> Return <SEP> Address of <SEP> or <SEP> Interrupt possibly <SEP> of Exception <SEP> (at
<tb> format <SEP> It <SEP> big <SEP> endian <SEP>"),<SEP> in <SEP> the <SEP> limit <SEP> of <SEP> 16 <SEP> windows
<tb> 00A0 <SEP> Maximum <SEP> Maximum <SEP> Allowed <SEP> for <SEP> MPS <SEP> and <SEP> IPS
<tb> OOA) -OOBFReserved
<tb> OOCO-OOFF <SEP><SEP> State <SEP> Status Indicators <SEP>
<tb> 0100 <SEP> - <SEP> 01 <SEP> FF <SEP> Values <SEP> $ FF00 <SEP> to <SEP> $ FFFF <SEP> by <SEP> increments <SEP> of <SEP> 1
<tb> 0200 <SEP> - <SEP> 02FF <SEP> Values <SEP> $ 0000 <SEP> to <SEP> $ 00FF <SEP> by <SEP> Increments <SEP> of <SEP> 1
<tb> 0300 <SEP> - <SEP> 03FF <SEP> Values <SEP> $ 00FF <SEP> to <SEP> $ FFFF <SEP> by <SEP> increments <SEP> of <SEP> $ 100
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The innovations brought by the Universal Machine make it possible to envisage multiple industrial applications. This document presents some of them.

machine support 23, moyennant un effort de programmation minimal. Les programmes peuvent c !) - Free from applications of the Universal Machine as a whole The architecture of the Universal Machine is based on a very simple basis. It allows you to develop programs of any complexity that will work on any

support machine 23, with a minimum programming effort. Programs can c

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 therefore be considered as realized once and for all. Thus, a game software or an operating system is programmed only once, and will be converted in a few days on any type of support machine 23. The speed and ease of conversion are particularly useful for groups of users. machines that are not yet fully standardized and standardized. These include digital personal assistants (PDAs) for personal digital assistants, mobile phones, and smart cards.

12-Examples of applications of certain levels of the Universal Machine, directly exploited (without relying on the lower levels) 12. 1-Level 0.2 Thanks to its extreme simplicity, the level 0.2 processor can be melted in the form of a microprocessor of very small size. In this case, it may be suitable for applications requiring extreme miniaturization, good reliability of electronic operation, low power consumption and not requiring much computing power.

processeur 0. 2 accompagné d'un ou plusieurs dispositifs mécaniques miniaturisés (capteur, ZD pompe avec réservoir, électrodes,...) dans un volume suffisamment réduit pour être implanté dans le corps humain. Par exemple, chez des malades, ces machines miniatures pourraient libérer des substances pharmaceutiques selon la teneur dans le sang d'un composé quelconque. This is for example the case of certain medical applications: one could imagine to hold a

processor 0. 2 accompanied by one or more miniaturized mechanical devices (sensor, ZD pump with reservoir, electrodes, ...) in a sufficiently small volume to be implanted in the human body. For example, in patients, these miniature machines could release pharmaceutical substances according to the content in the blood of any compound.

Another application would be the creation of artificial neurons implanted in the brain, compensating for certain neurological deficiencies: a 0.2 processor can simulate a set of neurons.

In other areas the interest of a 0.2 processor is different. This is the case of applications in extreme environments: instead of favoring miniaturization, the simplicity of level 0.2 allows to melt it in the form of a "macro" processor, that is to say a processor with circuits very coarse electric. This processor, while remaining of reasonable size (of the order of the size of a very complex current processor) would be very tolerant to cosmic ray induced disturbances, extreme temperature variations or mechanical stresses.

Aerospace and aeronautics are examples of application fields.

Other applications are possible in the field of "computers of clothing" (wearable computers, ie computers incorporated in clothes to better integrate into the daily life of the user). A 0.2 processor melted on a flexible insulating base could be integrated at low cost clothing, and withstand common use (deformation, cold, humidity, shock, etc.).

Finally, the extreme miniaturization of a level 0. 2 processor would free up space on the silicon surfaces for other electronic components, especially for memory. This would be interesting for smart cards whose memory can be limited by the size of the processor.

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12. 2-Level 0.4 The simplicity of the 0.2 level results in a slow execution of the programs which can make the complex applications quasi-unusable because of the inappropriate computation times. Level 0.4 is a better compromise between speed and simplicity. The extra complexity is minimal compared to level 0.2 so that the industrial applications that can be envisaged are very close. The execution speed of the programs is however about 100 times faster. Thus very complex programs are executed within a reasonable time.

ordinateur (applications graphiques, sonores, bureautiques, etc.). z : l Le niveau 1 représente le meilleur compromis entre simplicité de conception et rapidité d'exécution. 11 requiert cependant une machine support 23 ayant des capacités suffisantes pour l'accueillir, et n'est donc pas toujours adapté à certaines machines support aux capacités très limitées. De plus, le temps nécessaire pour réaliser une machine matérielle ou logicielle de niveau 1 peut être relativement long comparé à l'utilisation que t'en va en faire. C'est pourquoi ce niveau convient pour des machines largement diffusées et qui ne seront pas obsolètes trop rapidement. 12. 3 - Level 1 The simplicity of the 0.2 and 0.4 levels makes their direct use difficult. On the other hand the level 0.4 remains relatively slow which may be unsuitable for certain applications. Level 1 is of an intermediate level of complexity. It is capable of executing high level applications with a low loss of efficiency compared to their direct execution on the support machine 23. This level is therefore suitable for most common applications of a micro-machine.

computer (graphics, sound, office applications, etc.). z: l Level 1 represents the best compromise between simplicity of design and speed of execution. However, it requires a support machine 23 having sufficient capacity to accommodate it, and is therefore not always suitable for some support machines with very limited capabilities. In addition, the time required to make a hardware or software machine level 1 may be relatively long compared to the use that you will make. This is why this level is suitable for widely distributed machines that will not be obsolete too quickly.

12. 4-Machine 31 Level 2 Most of the time, it is not necessary to directly implement an implementation of this level.

Indeed, the realization of a hardware or software level 2 requires a significant investment of work, while its emulation by level 1 leads to a negligible loss of efficiency.

However, the direct use of this level can be interesting, for example for intensive computing. Indeed, the mass of necessary calculations multiplies the number of operations to be executed.

The loss of time, negligible during the emulation of this level by the level 1, can then become important. Examples include scientific computing, computer graphics calculation, artificial intelligence, or real-time compression of video data.

Claims (10)

An information processing device, characterized by: interleaved virtual machines (20, 21, 30, 31), i.e. one machine is emulated by another, hierarchically from the simplest to the more complex, that is to say that a given machine fully emulates another more complicated and elaborate machine, each virtual machine having an original architecture, that is to say, differentiating itself from the architecture of the other machines of the hierarchy of virtual machines, each virtual machine being adapted to execute an emulation or dynamic compilation program simulating the more complex virtual architecture of next higher level, a virtual machine of a given level in the hierarchy thus having a higher architecture simple as those of all higher-level virtual machines; the machine languages of the two lowest levels of virtual machines in the hierarchy (20,21) are specifically designed to allow all top-level operations to be performed; a level in the hierarchy, constituting the top of the hierarchy, emulates no other level of the hierarchy; and any level of the hierarchy can be linked to a real general-purpose machine (the support machine 23) by means of an executable program of emulation or dynamic compilation specific to this real machine.  2. Device according to claim I, characterized in that the machine language of the virtual machine at the base of the entire hierarchy (20) comprises only two elementary operations.  3. Device according to any one of claims 1 or 2, characterized in that the two instructions of the lowest level virtual machine are a subtraction and a memory backup.  4. Device according to any one of claims 1 to 3, characterized in that the machine language of the virtual machine immediately higher level (21) to the virtual machine at the base of the entire hierarchy comprises four elementary operations.  5. Device according to claim I, characterized in that the machine language of the virtual machine at the base of the entire hierarchy (21) comprises only four elementary operations. <Desc / Clms Page number 80>  6. Device according to any one of claims 4 or 5, characterized in that said four instructions are a subtraction, a memory backup, a Boolean logic function and a loading from the memory.  7. Device according to claim 6, characterized in that the Boolean logic function is one of the functions "and" or "or".  8. Device according to any one of claims 1 to 7, characterized in that it implements a tree of device representations, tree in which a device is apprehended following a path from the root of the tree and passing through at least one sheet, the information necessary to control said device being collected during said path, at least each leaf of the tree encountered.  9. Device according to any one of claims 1 to 8, characterized in that an infinite memory space is managed using addresses comprising information of length of the address and a value information of said address.  10. Device according to any one of claims 1 to 9, characterized in that it implements at least three virtual machines nested hierarchically from the simplest to the most complex.