FR2823397A1 - Extraction of a private datum to authenticate an integrated circuit, uses network parameters and noise to generate datum which has a transient life span, for transmission by circuit to allow its authentication - Google Patents

Abstract

The private datum is generated on request and is transient, existing in memory (21) for a brief time. The datum lifetime is variable, and shortens with successive generations. The private datum is obtained at least partly from a network of physical parameters, partly by a word supplied from a memory, and partly by circuit noise.

Description

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La présente invention concerne l'utilisation d'une quantité secrète issue d'un circuit intégré ou d'un élément de sous-ensemble électronique contenant un tel circuit. Par exemple, l'invention concerne l'utilisation d'une telle quantité secrète par des programmes en tant que clé de chiffrement, ou en tant que quantité secrète d'un processus d'identification ou d'authentification du circuit intégré. L'invention concerne plus particulièrement les circuits intégrés susceptibles d'exécuter plusieurs programmes d'application différents, que ces programmes soient contenus dans le circuit intégré ou le sousensemble électronique qui le contient ou soient logés dans des systèmes distants. DIVERSIFICATION OF A SINGLE IDENTIFIER OF AN INTEGRATED CIRCUIT

The present invention relates to the use of a secret quantity originating from an integrated circuit or from an electronic subassembly element containing such a circuit. For example, the invention relates to the use of such a secret quantity by programs as an encryption key, or as a secret quantity of an identification or authentication process of the integrated circuit. The invention relates more particularly to integrated circuits capable of executing several different application programs, whether these programs are contained in the integrated circuit or the electronic subassembly which contains it or are housed in remote systems.

An example of application of the present invention relates to chip cards where the integrated circuit chip can be used for several purposes (for example, electronic payment, identification of the holder, etc.). In this case, it is desirable not to use the same secret quantity (digital data) (of integrated circuit authentication or data encryption) for all the application programs likely to use this chip. Indeed, if a hacker tries to execute a fraudulent application program from the chip of the integrated circuit, the secret quantity of the

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 chip is also used. The remote system executing the fraudulent application can recover the quantity or secret key of the chip. This quantity can then be used fraudulently for other applications.

 To avoid this kind of fraud, conventional systems using smart cards in which the transmission with the operating terminal can be carried out with or without contact, provide that the secret quantity of the chip is not read by the program application but is generated at the request of the application program by the operating system of the smart card (for example, an operating system known by the trade name JAVACard).

 These conventional solutions require significant resources in terms of programming to execute the authentication or encryption processes.

 The present invention relates more particularly to the generation of separate secret quantities according to the applications.

 Among the means for generating a secret quantity within an integrated circuit, a distinction is essentially made between solutions using memory elements and those causing a generation of a binary word on the basis of a network of physical parameters. linked to the manufacturing of the integrated circuit.

 We could think of multiplying the number of networks of physical parameters so that they correspond to the number of applications that the integrated circuit can process. However, such a solution requires a lot of space and involves a significant risk of obtaining identical secret quantities generated by the network of physical parameters.

 In addition, each application may require a minimum size of the secret quantity greater than the size of the quantity coming directly from the network of physical parameters.

 The invention aims to overcome the drawbacks of known solutions requiring individualization of quantities

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 secret according to the application programs implementing an integrated circuit chip.

 The invention aims more particularly to propose a solution which is compatible with the use of a network of physical parameters for the generation of the secret quantity.

 The invention also aims to propose a solution which is compatible with conventional methods of exploiting secret quantities in authentication or encryption applications. In particular, it aims to remain compatible with authentication by the application programs themselves, without requiring complex authentication protocols by a central system.

 The invention further aims to propose a solution which is compact on the integrated circuit chip.

 To achieve these and other objects, the present invention provides a method of generating several secret quantities by an integrated circuit according to the destination of these secret quantities, consisting in taking into account a first digital word constituting a unique identifier of the integrated circuit chip and coming from a network of physical parameters, and to individualize this identifier according to the application.

 According to an embodiment of the present invention, the first digital word is combined with a second word from a non-volatile memory containing several.

 According to an embodiment of the present invention, the word from the network of physical parameters is used in a feedback shift register.

 According to an embodiment of the present invention, several feedback shift registers are used.

 According to an embodiment of the present invention, the shift register (s) are linear feedback.

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 The invention also provides a cell for generating several secret quantities by means of a unique identifier of an integrated circuit originating from a network of physical parameters, comprising means for individualizing a first digital word originating from the network of physical parameters to from a parameter depending on the desired quantity.

 According to an embodiment of the present invention, the cell comprises at least one feedback shift register, intended to be loaded with the first word from the network of physical parameters, and to supply one of said secret quantities.

 According to an embodiment of the present invention, the cell comprises a combiner of the first word from the network of physical parameters with a second digital word, extracted from a non-volatile memory and selected according to a parameter chosen according to the desired quantity .

 According to an embodiment of the present invention, the cell further comprises a scrambler for the words contained in the non-volatile memory, from the network of physical parameters.

 These objects, characteristics and advantages, as well as others of the present invention will be explained in detail in the following description of particular embodiments and embodiments given without limitation in relation to the attached figures among which: the FIG. 1 represents, by a very schematic view and in the form of blocks, a first embodiment of a cell for generating a secret quantity as a function of the current application according to the present invention; Figure 2 illustrates a variant of the cell of Figure 1; FIG. 3 represents, very schematically and in the form of blocks, a second embodiment of a cell for generating a secret quantity according to the application according to the present invention;

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 Figure 4 shows an embodiment of a shift register of the embodiment of Figure 3; and Figure 5 shows a simplified linear feedback shift register of four bits.

 The same elements have been designated by the same references in the different figures. For reasons of clarity, only the elements and process steps which are necessary for understanding the invention have been shown in the figures and will be described later. In particular, the application programs using the quantities (digital data) generated by the invention have not been detailed and are not the subject of the present invention.

 A feature of the present invention is to generate a secret quantity taking into account an identifier based on a network of physical parameters of the integrated circuit chip and the application concerned. In other words, the invention provides for individualizing the secret quantities supplied according to the application requiring the secret quantity, always using the same network of physical parameters as a basis.

 FIG. 1 represents, very schematically and in the form of blocks, a first embodiment of a cell 1 for generating a quantity, key or secret data KEYi from a network of physical parameters 2 (PPN) and depending on the application program (or application) claiming this quantity. The information relating to the application program is supplied to cell 1 in the form of a numerical parameter APPLi.

 Cell 1 is part of an integrated circuit 3 constituting, for example, the chip of a smart card.

 The network of physical parameters 2 is associated with a circuit 4 for extracting (EXTRACT) the signals from the network 2 to generate a first digital word stored in a temporary storage element 5 (REG1) and constituting a unique identifier of the chip. integrated circuit.

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 According to the first embodiment of the invention illustrated in FIG. 1, the first digital word is combined in a combination circuit 6 (COMB) with a second digital word (owl, W2, ... Wn) stored in a memory non-volatile 7 and function of the application. Is assigned to each application likely to require a digital authentication word, an encryption key or any other secret quantity KEYi specific to cell 1, a word Wi intended to be combined with the unique identifier of the integrated circuit chip . The result of the combination is stored in a temporary storage element 8 (REG2).

The selection of the word for personalizing the quantity according to the application is carried out by means of a selector 10 controlled by the signal APPLi. If the word table 7 corresponds to a space of a ROM or EEPROM memory of the integrated circuit, the selector naturally corresponds to the addressing circuit of this memory.

The generation (for memorization) of the Wi words associated with the different applications is made during a personalization phase prior to the use of the chip. The words Wi can come from a generator 11 of random words, or from a preset table. It is also possible to provide for the generation of an additional word Wi when adding a new functionality, that is to say when the smart card is configured to operate with a new application. As a variant, the generator 11 is external to the cell 1.

 The cell 1 further comprises a central unit 9 (CU) responsible for controlling and synchronizing the operation of all of its constituents. In FIG. 1, the various connections of the central unit to the other elements have not been detailed. This unit 9 communicates in particular with the rest of the integrated circuit 3 to, at the very least, execute instructions corresponding to the request for supply of the secret quantity by the cell 1.

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 An advantage that there is in combining the identifier from the network of physical parameters with a word which is a function of the application is that this optimally secures the exploitation of the secret quantities. In particular, if a hacker implements a fraudulent application and requests a secret quantity, the quantity which will be delivered to him will not allow him to use this quantity, for example, to authenticate fraudulently on other application systems.

 According to a simplified embodiment, the number n of words to be stored in the memory 7 is predefined during manufacture and the words are generated during the manufacture or of a first use of the chip. Thereafter, for each new application requiring an amount of authentication, an encryption key or the like, a serial number is assigned to the word table 7.

 The network of physical parameters may consist of any conventional network. It could be, for example, a network for measuring electrical parameters in the form of a measurement of a threshold voltage of a transistor, a measurement of resistance or a measurement of stray capacitance, a current measurement produced by a current source, a time constant measurement (for example, an RC circuit), a measurement of an oscillation frequency, etc. As these characteristics are sensitive to technological and manufacturing process dispersions, it can be considered that the electrical parameter (s) taken into account are specific to the chip and constitutes a signature of the latter.

 In the example of a measurement of electrical parameters, the signals are converted into digital signals by means of an analog-digital converter that includes the extractor 4 and are if necessary multiplexed to constitute the first digital word stored in the register. 5.

 As a network of physical parameters, it will also be possible to use circuits calling on a time measurement. For example, we measure the read / write time

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 an EEPROM type memory. An example of a network of physical parameters of this type is described in US Patent No. 5,818,738.

 We can also use a network of physical parameters based on flip-flops as described in French patent application No. 0104585 of the applicant.

 FIG. 2 illustrates a variant of the cell shown in FIG. 1. According to this variant, the binary word from the network of physical parameters which is stored in the register 5 is used, when writing the words in the table 7 of non-memory volatile, to confuse these words. The cell therefore also comprises a jammer or coder 12 (SCRAMB) to which the random generator 11 is connected as well as the register 5 and the combiner 6. The coder 12 is also connected to the table 7.

 In use, the circuit 12 serves as a decoder for the word Wi extracted from the table 7 so that it is used by the combiner 6. The decoding is again carried out on the basis of the word contained in the register 5 and extracted from the network of physical parameters.

 Preferably, in the embodiment of FIG. 1, the non-volatile memory used for storing the table 7 is secure (SECURE) like all the rest of the cell 1. On the other hand, in the embodiment illustrated by the FIG. 2, it is easier to dispense with integrating the non-volatile memory used for storing the table 7 in the secure area containing the rest of the cell. The variant of Figure 2 therefore allows the use of an external memory (not secure). By secure zone is meant an area of the circuit which is not liable to be hacked by detection of electrical signals. For example, it is a cell embedded in a resin whose melting temperature is higher than the deterioration temperature of the circuits, which prevents any analysis by electrical contact.

 Note that the word used to scramble the words wi can, while coming from the network of physical parameters, be

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 different from the word used by the combiner 6. For example, one can use part of the word contained in register 5 or provide another register for temporary storage of a word from the network of physical parameters which is different from the word used by the combiner 6.

 FIG. 3 very schematically shows in the form of blocks a second embodiment of a cell 20 for generating a secret quantity depending on the application in an integrated circuit chip 21. As in the first mode As an embodiment, cell 20 receives, as a parameter, an APPLi code representing the application program requesting the key KEYi that cell 20 generates in a register 8. Likewise, cell 20 comprises a network of physical parameters 2 associated with a extraction circuit 4 and to a register 5, as well as a central unit 9 having the same functions as those described in relation to FIG. 1.

 According to this second embodiment, the binary word extracted from the network of physical parameters is used to program at least one shift register with linear feedback 22 (LFSRi). In the example of FIG. 3, n registers 22 are provided, the number n corresponding to the number of different quantities which it is desired to be able to supply by means of cell 20. A selector 23 (SEL), for example a multiplexer, receives the outputs of the registers 22 and supplies a digital word to the register 8. The selector 23 is, for example, directly controlled by the signal APPLi parameterizing the cell 20 according to the application concerned. As a variant, the selector 23 can be located upstream of the registers 6 rather than downstream.

 Preferably, the signal APPLi for selection is combined (combiner 30) with a word from the network of physical parameters. It can be all or part of the register 5 or, as illustrated by FIG. 3, a word from an additional shift register 24 (LFSRO). The combiner 30 can be any set of logic gates. For example, we can apply an OU-Exclusive combination

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 a word from register 5 or 24 and the word APPLi. The word APPLi can consist of a number of bits taken from the start of the code of the application program. By choosing a sufficient number of bits (for example, 512 or 1024), it is guaranteed that two applications have little risk of providing identical APPLi words.

 This preferred variant is therefore a combination or scrambling of the parameter word APPLi by means of the network of physical parameters. It can also be implemented in the embodiment of FIG. 1.

 An example of application of the embodiment of FIG. 3 is the differentiation of the secret quantity coming from the network of physical parameters according to the applications in a network of Internet type. This embodiment is particularly effective against "Trojan horse" type attacks where a hacker tries to extract the key by means of a fraudulent program. Indeed, the combination of the word APPLi with a word from the network of physical parameters makes it possible to differentiate the selection codes for each chip.

 FIG. 4 shows, in more detail, a shift and feedback register 22. This register 22 is composed of a shift register 25 and of a feedback function 26. The number m of bits Bl, B2, B3, ..., Bm-1, Bm of the shift register corresponds to the number of bits of the first word contained in the register 5. The feedback function 26 combines several bits of the register 25 to calculate the leftmost bit Bm, each time a bit is output at the output OUT of the shift register 25 (supposed to go from left to right).

 Preferably, the feedback function used is a linear function consisting of an exclusive OR of several bits of the shift register. The bit register of the shift register taken in the feedback function constitutes the derivation sequence of the linear feedback register or Fibonacci configuration. We can also consider using

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 a non-linear feedback function provided that this makes it possible to generate a reproducible word at output.

m des quantités secrètes ayant des tailles allant jusqu'à 2-1 bits. Cela constitue le mot le plus long avant répétition. Le fait d'utiliser un déchargement en série du code fourni par le registre à décalage à rétroaction linéaire permet d'allonger la quantité secrète par rapport à la longueur du mot fourni par le réseau de paramètres physiques. In a linear feedback shift register of m bits, there are 2m-1 separate binary sequences. In other words, by loading the successive bits supplied on the output OUT in a register of suitable size, one can obtain

m secret quantities having sizes up to 2-1 bits. This is the longest word before repetition. The fact of using a serial download of the code supplied by the linear feedback shift register makes it possible to extend the secret quantity with respect to the length of the word supplied by the network of physical parameters.

 According to the invention, the identifier from the network of physical parameters is used to set the start word of the shift register. Thereafter, the central unit 9 controls a certain number of offsets of the register, which makes it possible to supply the word constituting the key as an output. As for the loading of register 25, it is possible to provide either a parallel unloading of the word (on n bits), or a serial unloading. If the word is loaded in series into register 25, an input selector will simply be provided for choosing between the output of the feedback function and the loading at the most significant bit Bm.

 Two integrated circuit chips having different identifiers by means of their physical parameter networks will provide, with the same shift register, different quantities. Likewise, the different shift registers 22 used by the invention in the circuit of FIG. 3 correspond to different derivation sequences which will therefore give different results for the same input word.

 As a variant, rather than using several shift registers with linear feedback, it is possible to use the same register, the derivation sequence of which is programmed as a function of the parameter identifying the application. It could be

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 directly from the APPLi parameter or from a parameter derived indirectly from this quantity.

 According to another variant, a single linear feedback shift register is always used and the parameter identifying the application conditions the number of shift cycles applied to the register 25.

contenu dans le registre 25'sur quatre bits sont combinés par une porte de type OU Exclusif 26'constituant la fonction de rétroaction. La sortie de la porte 26'constitue l'entrée du registre à décalage, donc l'entrée de la valeur B4. La séquence de sortie OUT est fournie par le bit de poids le plus faible (bel). FIG. 5 represents, for a better understanding of the operation thereof, a simplified linear feedback shift register 22 of four bits in which the derivation sequence is B1, B4. In other words, the least significant and most significant bits B1 and B4 of the word, respectively

contained in the register 25 'on four bits are combined by an Exclusive OR type gate 26' constituting the feedback function. The output of gate 26 ′ constitutes the input of the shift register, therefore the input of the value B4. The output sequence OUT is provided by the least significant bit (bel).

1000 ; 1100 ; 1110 ; 1111 ; OUI ; 1011 ; 0101 ; 1010 ; 1101 ; 0110 ; 0011 ; 1001 ; 0100 0010 0001, avant de se répéter. The successive contents of register 25 will be, assuming an initialization with the value 1000, that is to say a loading of a state 1 in bit B4 after initialization at 0 of all the other bits:

1000; 1100; 1110; 1111; YES ; 1011; 0101; 1010; 1101; 0110; 0011; 1001; 0100 0010 0001, before repeating itself.

 The choice of the derivation sequence according to the number of possible combinations before repetition is within the reach of the skilled person depending on the application. The creation of a linear feedback shift register, whether in hardware or software, is perfectly conventional. We can refer, for example, to the book "Applied Cryptography" by Bruce Schneier edited by Wiley, second edition, pages 395 to 401.

 An advantage of the present invention is that it preserves the volatile (ephemeral) character of each of the

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 secret quantities based on the extraction of a word from physical parameters.

 Of course, the present invention is susceptible of various variants and modifications which will appear to those skilled in the art. In particular, the practical realization of the circuit which is the subject of the invention is within the reach of those skilled in the art from the functional indications given above.

 In addition, although the invention has been explained with more relation to hardware elements, it can be implemented by software means provided to retain the use of a network of physical parameters of an integrated circuit chip. .

 In addition, the respective sizes of the different digital words used are defined according to the application.

In this regard, it will be noted that the implementation of the invention does not require any modification of the application programs.

 Finally, functions other than those set out by way of example to individualize the identifier may be used. In particular, any one-way and reproducible function may be used, such as the so-called one-way hash functions. By one-way, we mean a transformation whose knowledge of the output word does not allow to determine the input word (from the network of physical parameters). By reproducible is meant a transformation always providing the same output word for a given input word. The different embodiments can also be combined according to the types of application.

Claims (9)

1. Method for generating several secret quantities (KEYi) by an integrated circuit according to the destination of these secret quantities, characterized in that it consists in taking into account a first digital word constituting a unique identifier of the circuit chip integrated and coming from a network of physical parameters (2), and to individualize this identifier according to the application.  2. Method according to claim 1, characterized in that it consists in combining the first digital word with a second word (Wi) from a non-volatile memory containing several.  3. Method according to claim 1, characterized in that it consists in using the word from the network of physical parameters (2) in a feedback shift register (22, 32).  4. Method according to claim 3, characterized in that it consists in using several feedback shift registers (22,32).  5. Method according to claim 3 or 4, characterized in that the shift register (s) (22,32) are linear feedback.  6. Cell for generating several secret quantities (KEYi) by means of a unique identifier of an integrated circuit originating from a network of physical parameters (2), characterized in that it includes means for individualizing a first word digital from the network of physical parameters from a parameter (APPLi) depending on the desired quantity.  7. Cell according to claim 6, characterized in that it comprises at least one feedback shift register (22,32), intended to be loaded with the first word from the network of physical parameters (2), and to provide one of said secret quantities (KEYi). <Desc / Clms Page number 15>  8. Cell according to claim 6, characterized in that it comprises a combiner (6) of the first word from the network of physical parameters (2) with a second digital word, extracted from a non-volatile memory (7,37) and selected according to a parameter (APPLi) chosen according to the desired quantity.  9. Cell according to claim 9, characterized in that it further comprises a scrambler (12) of the words (wi) contained in the non-volatile memory, from the network of physical parameters (2).