FR2820523B1 - Microprocesseur comportant une instruction d'inversion des bits d'un mot binaire - Google Patents

Microprocesseur comportant une instruction d'inversion des bits d'un mot binaire

Info

Publication number
FR2820523B1
FR2820523B1 FR0101681A FR0101681A FR2820523B1 FR 2820523 B1 FR2820523 B1 FR 2820523B1 FR 0101681 A FR0101681 A FR 0101681A FR 0101681 A FR0101681 A FR 0101681A FR 2820523 B1 FR2820523 B1 FR 2820523B1
Authority
FR
France
Prior art keywords
microprocessor
binary word
word bit
bit reverse
reverse instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0101681A
Other languages
English (en)
Other versions
FR2820523A1 (fr
Inventor
Franck Roche
Nicolas Lafargue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0101681A priority Critical patent/FR2820523B1/fr
Priority to US10/068,568 priority patent/US20020156818A1/en
Publication of FR2820523A1 publication Critical patent/FR2820523A1/fr
Application granted granted Critical
Publication of FR2820523B1 publication Critical patent/FR2820523B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
    • G06F7/575—Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/768—Data position reversal, e.g. bit reversal, byte swapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30025—Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Executing Machine-Instructions (AREA)
FR0101681A 2001-02-08 2001-02-08 Microprocesseur comportant une instruction d'inversion des bits d'un mot binaire Expired - Fee Related FR2820523B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0101681A FR2820523B1 (fr) 2001-02-08 2001-02-08 Microprocesseur comportant une instruction d'inversion des bits d'un mot binaire
US10/068,568 US20020156818A1 (en) 2001-02-08 2002-02-06 Microprocessor comprising an instruction for inverting bits in a binary word

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0101681A FR2820523B1 (fr) 2001-02-08 2001-02-08 Microprocesseur comportant une instruction d'inversion des bits d'un mot binaire

Publications (2)

Publication Number Publication Date
FR2820523A1 FR2820523A1 (fr) 2002-08-09
FR2820523B1 true FR2820523B1 (fr) 2003-05-16

Family

ID=8859750

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0101681A Expired - Fee Related FR2820523B1 (fr) 2001-02-08 2001-02-08 Microprocesseur comportant une instruction d'inversion des bits d'un mot binaire

Country Status (2)

Country Link
US (1) US20020156818A1 (fr)
FR (1) FR2820523B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008235992A (ja) * 2007-03-16 2008-10-02 Matsushita Electric Ind Co Ltd リコンフィギュラブル回路、リコンフィギュラブル回路システムおよびリコンフィギュラブル回路の配置配線方法
US9817791B2 (en) 2015-04-04 2017-11-14 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word
US11847427B2 (en) * 2015-04-04 2023-12-19 Texas Instruments Incorporated Load store circuit with dedicated single or dual bit shift circuit and opcodes for low power accelerator processor

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3768077A (en) * 1972-04-24 1973-10-23 Ibm Data processor with reflect capability for shift operations
US4075704A (en) * 1976-07-02 1978-02-21 Floating Point Systems, Inc. Floating point data processor for high speech operation
CA2007059C (fr) * 1989-01-27 1994-05-24 Steven P. Davies Registre et unite arithmetique et logique
US4931974A (en) * 1989-01-30 1990-06-05 Integrated Device Technology, Inc. Sixteen-bit programmable pipelined arithmetic logic unit
US5926644A (en) * 1991-10-24 1999-07-20 Intel Corporation Instruction formats/instruction encoding
US5682340A (en) * 1995-07-03 1997-10-28 Motorola, Inc. Low power consumption circuit and method of operation for implementing shifts and bit reversals
KR20000016448A (ko) * 1997-04-08 2000-03-25 도쿠나까 테루히사 연산 장치 및 연산 방법
US5987603A (en) * 1997-04-29 1999-11-16 Lsi Logic Corporation Apparatus and method for reversing bits using a shifter
US6163836A (en) * 1997-08-01 2000-12-19 Micron Technology, Inc. Processor with programmable addressing modes
JP4558879B2 (ja) * 2000-02-15 2010-10-06 富士通株式会社 テーブルを用いたデータ処理装置および処理システム

Also Published As

Publication number Publication date
US20020156818A1 (en) 2002-10-24
FR2820523A1 (fr) 2002-08-09

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20071030