FR2814560A1 - Data transmission method for data forwarding between components of computer system involves producing clock signal as unequal square-wave signal to recognize content of predetermined signal sent to data line - Google Patents

Abstract

A clock signal is produced in a clock line as an unequal square-wave signal with different cycles forming various pulse duty factors, to recognize the content of the signal transferred to the data lines including a semantic content address signal, a data signal and a control signal. The method involves allocating one of the signal lines of each channel between two components (10,20) of a computer channel system as a clock line for defining a clock signal, a start signal and a final signal. The remaining signal lines of the channel are allocated as the data lines. An Independent claim is also included for a data transmission arrangement.

Description

DESCRIPTION

  The invention relates to a structure for an inter-element channel transmission and to a method thereof, and more particularly to a model of the channel transmissions and a design of respective methodology, which are suitable for being implemented. independently and the channel arrangement of which can be adjusted in any way according to practical requirements. In a conventional structure of a computer system, various buses could be used to form a communications network between the elements of the computer system. As shown in FIG. 1, a plurality of conventional buses are used to connect a first element 10 and a second element 20, in which the first or the second element 10 or 20 can take the form of a central unit, of a memory, a device, or some other element. In general, the bus can be classified into three categories as follows. These categories are: 1. A control bus intended to generate particular signals to control the system, mainly used to establish communication between a central unit (CPU) and a peripheral or between a central unit and a memory, 2. A bus address intended to define the target address, which represents a memory or an input / output device of a particular signal, and 3. A data bus intended for a unidirectional or bidirectional data transmission, capable of reading data and / or write data with respect to a CPU, peripheral, or memory. By providing the control bus, the signal flows in the computer can be predetermined. By providing the address bus, the signal can be routed to the target device. Likewise, by planning the data bus,

  read or written data can be transmitted.

  However, these conventional buses have the following drawbacks. 1. Uniqueness: while a transmit task occupies a particular bus, all other tasks must wait in an ordered queue until the bus is released from the previous task. That is, the conventional bus cannot send and receive data in

same time.

  2. Most of the data lines used for data / address buses in a computer system are 64-bit wide data lines. However, it is foreseeable in the near future that a bus presenting data lines with width of 128 bits will constitute the main stream. Such an increase in bit width implies the inevitable increase in the number of pins for the data line as well as for the bus, and will result in packaging difficulty and an increase in size. In particular, the system controller is mainly affected by the increase in the number of pins, due to its connection with the

the most important elements.

  3. In a simultaneous switching state (from 0 to 1, or 1 to 0 at the same time) at the parallel data / address lines, higher power consumption is inevitable and therefore more noise will affect the transmission. Consequently, it is an object of the present invention to provide a structure and a corresponding method for transmission by inter-element channels, in which various channels are used as means of communication between elements, so as to construct a plurality of connection channels between these elements and so that system data can be allocated reasonably in accordance with practical requirements. In the present invention, each channel includes a plurality of signal lines for transmitting control, data and address signals in accordance with a

  predetermined communications protocol.

  In a preferred embodiment of the present invention, one of the signal lines of the channel can be assigned or used to transmit clock or start indicator signals (definition of a clock signal, a start signal and an end signal). According to the present invention, the clock signal can be an incoherent square signal, presenting various cycles which define various respective duty cycles and intended to determine the formats of the data transmitted on the data lines by evaluating the duty cycle of each cycle of wave. By providing a duty cycle detector to detect the duty cycle, the implicit meaning of the signals transmitted in the signal lines

  respective (data) can then be apprehended, i.e.

  say that the signal lines intended to transmit address signals, data signals or control signals can thus be clearly defined and said

  signals have implicit meaning.

  According to other characteristics of the invention, it can be provided that: when a cycle of said clock signal has a duration for the value "1" longer than for the value "0", and has a substantial ratio for these two durations, said transmission begins and said data lines transmit said address signals or said control signals; - Said ratio is preferably 3: 1; - When a cycle of said clock signal has a duration for the value "1" substantially equal to that for the value "0", said data lines transmit said data signals; - When a cycle of said clock signal has a duration for the value "1" significantly shorter than for the value "0", said transmission ends. The subject of the invention is also a structure for transmission by channels between elements, characterized in that it comprises: a data locking circuit intended to store signals (comprising data signals (DATA), of address ( ADDRESS) and command (CONTROL)) transmitted on a data line by being triggered by a negative edge of a clock signal, and a duty cycle detector intended to detect a respective duty cycle of each cycle of said signal clock, said duty cycle and said signals from said data latch circuit being used to define corresponding signal sequences for obtaining said respective data, address and control signals for further processing in an element reception, and said detection of said duty cycle detector being completed while an end of condition

transmission is encountered.

  In addition, in another preferred embodiment of the present invention, an A / C line (address / command line) of the signal lines of the channel can be used to define the start and end of a transmission.

  and to transmit the address and control signals.

  The remaining signal lines of the same channel are then left as data lines for transmitting data signals. By evaluating the variation of the signals transmitted on the A / C line, data line storage sequences can then be performed. Furthermore, by evaluating the variation of the signals of the data lines, the differences or switching of the bits of the address signals transmitted on the A / C line can also be measured or determined. In the present invention, by providing a data line switching detector and an edge and start signature detector, the characteristics of the signals transmitted on the data lines and the A / C line can then be detected. According to other characteristics of the invention, it can be provided that: - said storage of said data line is triggered by an edge of said A / C line, said edge being either a rising edge or a falling edge; - said A / C line uses a start signature to initiate said transmission, and bits of said address signal are transmitted after said start signature is transmitted in said A / C line; - when identical signals are transmitted in two consecutive cycles, said A / C line duplicates the signal

transmitted.

  The invention also relates to a structure for transmission by channels between elements, characterized in that it comprises: a data line switching detector intended to detect and determine a variation of the signal in the data lines, and generating a switch command to a data locked circuit while detecting any variation, an edge and start signature detector, in order to detect a start signature in the A / C line in order to generate a command address to the data line switching detector in order to ensure a departure of the effective data in the data lines, in order to detect the appearance of the edges in the A / C line in order to generate a required command for triggering of front to a data latch circuit via a delay buffer, to control the data latch circuit for storage r the signals in the data lines, and in order to generate a start command intended to determine the effective data in the data buffer memory, a serial buffer intended to collect the effective address data originating from the data locking circuit and then transmit the effective address data, and a data buffer, controlled by the start command to determine the effective data

  in the data buffer.

  According to the above-mentioned arrangement of the transmission model and methodology, each channel of the present invention can operate as a complete bus, characterized by independent operation and one-way transmission

  unique for both address and data signals.

  Likewise, the channels of the present invention can be appropriately adjusted to meet practical requirements. Thereby, the mobility of signal transmission between the various elements can be obtained, so that the transmission waiting time for each element can be greatly reduced and therefore an optimal transmission efficiency can be obtained. By realizing the channel structure of the present invention, many benefits can be obtained by the

  construction of a complete hardware package.

  The present invention will now be specified with reference to its preferred and nonlimiting embodiments, illustrated in the drawings, in which Figure 1 is a simplified view of a conventional bus structure, Figure 2 is a simplified view of a structure of a channel transmission system according to the present invention, FIG. 3 represents a time sequence of a first preferred embodiment according to the present invention, FIG. 4 is a block diagram representing the end receiving the transmission model of Figure 3, Figure 5 is a flow diagram of the first preferred embodiment according to the present invention, Figure 6 shows a time sequence of a second preferred embodiment according to the present FIG. 7 is a block diagram representing the reception end of the transmission model of FIG. 6, and FIG. 8 is a flow diagram of the second mode of

  preferred embodiment according to the present invention.

  The invention described here is concerned with a respective structure and method for transmission by channels

  inter-element. In the following description, many

  details are presented so as to allow an exhaustive understanding of the present invention. Those skilled in the art will realize that variations on these particular details are possible while still obtaining the results of the present invention. In other cases, the well-known components are not described in detail in

  so as not to unnecessarily mask the present invention.

  Referring now to Figure 2, the difference between the channels of the present invention and the conventional bus shown in Figure 1 can be easily explained. As indicated, the first element 10 and the second

  element 20 are connected by a plurality of channels 30.

  Each channel 30 which comprises a plurality of lines of

  signals, is activated independently of the other channels 30.

  In practice, each channel 30 can be considered to be a localized data stream. Due to the nature of independent operation, the combination of channels 30 in a system can then be appropriately adjusted to meet any practical requirement. Regarding the example shown on the

  Figure 2, channels A, B and C are assigned to session 1.

  However, channels D and E are assigned to session 2.

  To clarify, channel A is a unidirectional channel transmitting signals from the first element 10 to the second element 20, while channels B and C are also unidirectional channels, but transmitting

  signals from second element 20 to first element 10. That is

  say that although each channel 30 of the present invention may have the same structure (i.e. a structure comprising a plurality of signal lines), the transmission sequence (e.g. direction of transmission) for each channel 30 can however be different but predetermined to meet the practical needs of the system. Consequently, it is the object of the present invention to provide a transmission model by particular channels and a respective method suitable for the

  channel structure mentioned above.

  In the description which follows, two embodiments

  are used for demonstration of the channel transmission protocol of the present invention, in which each channel 30 thereof comprises a plurality of signal lines and is characterized by one-way transmission. Signal lines are mainly used to transmit address and data signals. The following represents the first and second preferred embodiments of the present invention presented to demonstrate two types of models of

  transmission by channels according to the present invention.

  [First Embodiment] In the first channel transmission model, a signal line of channel 30 is used as a clock to transmit a start signal and an end signal. The rest of the signal lines of channel 30 are used as data lines to transmit data signals. As shown in Figure 4, channel 30 of the first embodiment has 9 signal lines, and 8 of them are data lines. Of course, in practice, the number of signal lines as well as data lines can exceed this. Referring now to the time sequence illustrated in Figure 3, the clock is not a traditional coherent square signal. By evaluating the duty cycle of each clock cycle, the respective data sequence transmitted by the data line can then be determined. Referring now to Figure 5, the positive logic of the

  first embodiment can be demonstrated as follows.

  (a) In a specific cycle such that the duration for "1" is greater than that for "0" (for example, a duty cycle "+": "-" = 3: 1), the transmission of data signals is started. Then, address or control signals are transmitted over the data line. As regards the example shown in FIG. 3, an address signal A followed by a control signal C is transmitted on the data line. The fact that an address signal or a control signal is transmitted on the data line can be defined according to the following criteria. These are: 1. The control signal always follows the address signal, as in the example shown in the

figure 3.

  2. If a certain duty cycle, for example 4: 1, exists between the address signal and the control signal, the signal with a longer cycle is an address signal and the signal with a shorter cycle is a control signal. (b) In a specific cycle such that the duration for "1" is approximately equal to that for "0" (for example a duty ratio of 1: 1 with a percentage of errors of less than 25 percent), one can know that data signals are transmitted on the data line. Regarding the example shown in Figure 3, the third to seventh signals in the data line are data signals D. (c) In a specific cycle such that the duration for "1" is less than that for "0" (for example a duty ratio of 1: 3, the transmission of

data signals ends.

  In accordance with the above criteria, the signals transmitted on the clock signal line of the present invention mainly comprise two major parts

which are as follows.

  1. Start of transmission and end of transmission.

  2. Signal sequence for the signals transmitted on the data line (such as the data signal D, the address signal A, or the control signal C), and the signal sequence for the signals of the

data line.

  In the example shown in Figure 3, the negative edges of the clock signals are used to trigger the acquisition of the data signals from the data line. During the first non-symmetrical cycle at the start of the transmission, it is known that the data line transmits a signal of address A. During the second non-symmetrical next cycle, the data line transmits a control signal C. For the rest of the symmetrical cycles until the end of the transmission, D data signals are

  identified as circulating in the data line.

  FIG. 4 illustrates the manner in which a reception end of the channel transmission model of the first embodiment receives the above-mentioned clock signals as well as the data signals. The receiving end comprises: A data locking circuit 40 intended to memorize the signal (data signal D, address signal A, or control signal C) transmitted on the data line, triggered by falling edges of the clock signals, and performing storage on the respective signal of the data line while the clock signal line encounters any negative edge, and A duty cycle detector 41 for detecting

  the duty cycle of each clock cycle.

  In which the duty cycle defined by the duty ratio detector 41 will be used to define whether the signals stored by the data latch circuit 40 are address signals A, control signals C, or data signals D in accordance to the definitions cited above (the dashed line in the figure). The signals after the previous identification will then be sent to the respective target element for further processing. Such duty cycle detection and determination of the signal sequence will be performed

  until an end signal is detected.

  In the previously mentioned channel transmission model, the implicit meaning of the signals transmitted in the data signal line (i.e. the sequence of signals) can be understood by evaluating the variation of the duty cycle of each cycle d clock of the clock signal line. In this embodiment, the number of data lines and / or criteria for determining the implied meaning of the signals in the data lines with respect to various duty cycles can be adjusted appropriately to meet relevant practical requirements. Such an adjustment should be seen as an equivalent realization of this channel transmission model. [Second preferred embodiment] We are asked to refer to the time sequence which is illustrated in FIG. 6. In the second channel transmission model, an A / C line (address / command line) is used to define start of transmission, end of transmission, and transmission of address and / or control signals. The rest of the signal lines on the same channel are used to transmit

data signals.

  The channel transmission model of the second embodiment is characterized in that the storage sequence can be defined by evaluating the variation of the signal on line A / C and the switching of the bits of the address signal transmitted in line A / C can be determined by evaluating the variation of the data signal in the data line. Similarly, in this channel transmission model, the number of A / C lines (1 in this embodiment) and the number of data lines (8 in this embodiment) are both subject to

  variation without contravening the implementation of this model.

  In the embodiment shown in FIG. 6, the instant of triggering of storage on the data lines is determined in accordance with the criteria for triggering by an edge. That is, the storage of the data lines will be triggered when a falling edge or a rising edge is encountered. The triggering as a function of both the falling and rising edges of this embodiment represents the main characteristic of this embodiment which differs from the first embodiment in which only the

  Falling edge can trigger memorization.

  Line A / C uses a starting signature "1010" to start the transmission sequence (in the form of a step a, shown in Figure 8). After the starting signature is transmitted in line A / C, the bits of the address signal (aO, al, a2, a3, a4, ... in FIG. 6) are then transmitted (in step b shown in Figure 8). In this embodiment, the variation of the data on the data line is used to define the switching of the address bits. At the same time, when the rising or falling edges of the signals on the A / C line are encountered, the bits DO, D1, D2 and D3 of the data line can be memorized (as indicated in step c represented on Figure 8). By applying the same sequence in time, other signals in the rest of the data lines of the same channel can be stored in order as well. It is interesting to find a particular situation in Figure 6. That is to say that when an identical signal is transmitted in two consecutive cycles in the form D7 and D8 in Figure 6, the line A / C does not that duplicate the output (at the level of the second a2 represented

  in Figure 6) to satisfy this situation.

  Referring now to Figure 7, a block diagram is shown to explain how the receiving end of the channel transmission model interprets the time sequence mentioned above. As explained above, three situations must be detected. It is:

  1. Start of transmission (or end of transmission).

  2. The signal edges of the A / C line for memorizing the signals on the data lines, comprising both the rising and

descending.

  3. The variation of the signal transmitted itself on the data line to define the variation of the bits

signals from the A / C line.

  As the structure shown in Fig. 7, the embodiment includes: A data line switching detector 50 for detecting and defining the variation of signals on the data lines, by generating a switching command 501 while a variation is detected, and the switching command 501 being sent to a data latching circuit 52 via a delay buffer memory 51; A start and edge signature detector 53, which reacts in the following way: 1. Detect the start signature on the A / C line in order to generate an address command 531 to the data line switching detector 50 to indicate the start of the actual data transmitted on the data lines, 2. Detect the appearance of the edges on the A / C line, in order to generate a triggering command on a required edge 532, the command 532 being propagated towards a data latch circuit 55 via a delay buffer 54 for controlling the data latch circuit 55 to store the signals transmitted on the data lines, and 3. Generate a start command 533 intended to determine the actual effective data in a data buffer memory 56, A serial buffer memory 57, intended to transmit signals of effective addresses by collecting the memorized data received from the data latch circuit 52, and a data buffer 56, controlled by the start command 533 to determine the data

  effective in data buffer 56.

  In this embodiment, after a start signature "1010" is detected in the A / C line by the start and edge signature detector, the transmission of the effective data on the data lines is then started. Therefore, the start and edge signature detector 53 can also detect the appearance of the edges of the A / C line in order to generate a trigger command by a respective edge 532. After the delay buffer 54 delays the edge trigger command 532 for a predetermined period of time, the edge trigger command 532 is further used to trigger the data latch circuit 55 for the purpose of storing the signals of the data lines. The data stored by the data latch circuit 55 will then be propagated to the data buffer 56. The start command 533 generated by the start and edge signature detector 53 will then be used to determine the propagation of the actual effective data collected in the data buffer 56. Furthermore, the A / C line will transmit an address signal at the same time. Due to the single signal line assigned to the A / C line, the address signals are generated as a series of individual bits. The start and edge signature detector 53 will propagate the address signal 531 to the data line switching detector 50 in order to instruct the data line switching detector 50 to receive

  sequentially each bit of the address signals.

  When a signal variation is encountered in the data lines, a switching command 501 is generated and propagated to the data latch circuit 52 in order to receive the current bits of the A / C line. These bits will be collected by the serial buffer 57 and will then be propagated until a next stop, after

  an effective address signal is formed.

  In this channel transmission model, the A / C line and the data lines serve as a mutual reference for data storage. With the exception of the fact that line A / C is responsible for indicating the start or end of the sequence, the memorization of the signals on the data lines is triggered when the edges of the signals transmitted on line A meet. / C, and furthermore the variation of the data on the data lines is also applied to execute the storage of the bits of the address signals transmitted on the line A / C. Similarly, the specific requirements applied to this preferred embodiment are not particularly used to restrict the structure of this transmission model

by channels.

  As explained, the respective structure and method for inter-element channel transmission according to the present invention are capable of transmitting address / data signals by

  through a plurality of channels defined above.

  Data transmission can be optimized in accordance with the practical requirements of data flow. In applying the present invention, the disadvantages of buses

  classics are obviously improved.

  Although the present invention has been particularly presented and described with reference to preferred embodiments, those skilled in the art will understand that various variants of form and detail can be made without departing from the spirit and the scope of the

present invention.

Claims (11)

  1. A method of transmission by channels between elements (10, 20) constructing a plurality of connection channels (A to E) between the elements, each of the channels comprising a plurality of signal lines j characterized in that one of channel signal lines is assigned as a clock line (CLOCK) to define a clock signal, a start signal and an end signal, the rest of the channel signal lines being assigned as lines data signal, the clock signal being an incoherent square signal having various cycles which define various respective duty cycles in order to obtain an implicit meaning of the signals of the data lines, and the implicit meaning comprising address signals, signals of data and control signals. 2. A method of transmission by channels between elements (10, 20) according to claim 1 / characterized in that when a cycle of said clock signal has a duration for the value "1" longer than for the value "0 ", and has a substantial relationship for these two durations, said transmission begins and said data lines transmit said address signals or said control signals. 3. A method of transmission by channels between elements according to claim 2) characterized in that   said ratio is preferably 3: 1.   4. A method of transmission by channels between elements according to claim 1 / characterized in that when a cycle of said clock signal has a duration for the value "1" substantially equal to that for the value "0", said lines of data transmit said signals of data.   5. A method of transmission by channels between elements according to claim 1) characterized in that when a cycle of said clock signal has a duration for the value "1" substantially shorter than for the   value "0", said transmission ends.   6. Transmission structure by channels between elements, characterized in that it comprises: a data locking circuit (40) intended to store signals (comprising data (DATA), address (ADDRESS) and (CONTROL)) transmitted on a data line by being triggered by a negative edge of a clock signal, and a duty cycle detector (41) intended to detect a respective duty cycle of each cycle of said signal clock, said duty cycle and said signals from said data latch circuit being used to define corresponding signal sequences for obtaining said respective data, address and control signals for further processing in an element reception, and said detection of said duty cycle detector being completed while an end of condition transmission is encountered.   7. A method of transmission by channels between elements (10,20) constructing a plurality of channels (A to E) for connection between the elements (10, 20), each channel comprising a plurality of signal lines) characterized in that 'an address / control line (A / C) of the signal lines of the channel is used to define a start of transmission and an end of transmission and to transmit signals of address and control, the rest of the signal lines of the channel being assigned as data lines, the storage sequence of the data line being determined by a variation of the signal of the A / C line, and a switching of the bits of the address signals transmitted in the line A / C being determined by a   variation of the data line signal.   8. A method of transmission by channels between elements (10, 20) according to claim 7) characterized in that said storage of said data line is triggered by an edge of said A / C line, said edge   being either a rising edge or a falling edge.   9. A method of transmission by channels between elements (10, 20) according to claim 7 j characterized in that said line A / C uses a starting signature to initiate said transmission, and bits of said address signal are transmitted after that said departure signature   is transmitted in said A / C line.   10. A method of transmission by channels between elements (10, 20) according to claim 7; characterized in that when identical signals are transmitted in two consecutive cycles, said A / C line duplicates the transmitted signal. 11. Channel transmission structure between elements (10, 20), characterized in that it comprises: a data line switching detector (50) intended to detect and determine a variation of the signal in the data lines , and generating a switch command (501) to a data latch circuit (52) while detecting any variation, an edge and start signature detector (53), to detect a start signature in the A / C line in order to generate an address command (531) to the data line switching detector (50) in order to ensure a departure of the effective data in the data lines, in order to detect the appearance of the edges in the A / C line to generate a required edge trigger command (532) to a data latch circuit (55) via a delay buffer (54), to control the do lock circuit data (55) for storing the signals in the data lines, and for generating a start command (533) for determining the actual data in the data buffer (56), a serial buffer (57) for collecting the effective address data from the data latch circuit (52) and then transmitting the effective address data, and a data buffer (56), controlled by the start command (533) to determine data   effective in the data buffer (56).