FR2811829B1 - Procede et dispositif pour regler le temps mort entre des signaux d'horloge sans chevauchement - Google Patents

Procede et dispositif pour regler le temps mort entre des signaux d'horloge sans chevauchement

Info

Publication number
FR2811829B1
FR2811829B1 FR0109355A FR0109355A FR2811829B1 FR 2811829 B1 FR2811829 B1 FR 2811829B1 FR 0109355 A FR0109355 A FR 0109355A FR 0109355 A FR0109355 A FR 0109355A FR 2811829 B1 FR2811829 B1 FR 2811829B1
Authority
FR
France
Prior art keywords
adjusting
clock signals
dead time
overlap clock
overlap
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0109355A
Other languages
English (en)
Other versions
FR2811829A1 (fr
Inventor
Rajakrishnan Radjassamy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of FR2811829A1 publication Critical patent/FR2811829A1/fr
Application granted granted Critical
Publication of FR2811829B1 publication Critical patent/FR2811829B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
    • H03K5/1515—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs non-overlapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
FR0109355A 2000-07-17 2001-07-13 Procede et dispositif pour regler le temps mort entre des signaux d'horloge sans chevauchement Expired - Fee Related FR2811829B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/617,373 US6310499B1 (en) 2000-07-17 2000-07-17 Methods and apparatus for adjusting the deadtime between non-overlapping clock signals

Publications (2)

Publication Number Publication Date
FR2811829A1 FR2811829A1 (fr) 2002-01-18
FR2811829B1 true FR2811829B1 (fr) 2004-10-29

Family

ID=24473409

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0109355A Expired - Fee Related FR2811829B1 (fr) 2000-07-17 2001-07-13 Procede et dispositif pour regler le temps mort entre des signaux d'horloge sans chevauchement

Country Status (2)

Country Link
US (1) US6310499B1 (fr)
FR (1) FR2811829B1 (fr)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6331800B1 (en) * 2000-07-21 2001-12-18 Hewlett-Packard Company Post-silicon methods for adjusting the rise/fall times of clock edges
JP3980431B2 (ja) * 2002-07-19 2007-09-26 Ｎｅｃエレクトロニクス株式会社 バッファ回路とバッファツリー及び半導体装置
US6809570B2 (en) * 2003-01-21 2004-10-26 Hewlett-Packard Development Company, L.P. Clock gater circuit
US20050050494A1 (en) * 2003-09-02 2005-03-03 Mcguffin Tyson R. Power estimation based on power characterizations of non-conventional circuits
US7109776B2 (en) * 2004-09-23 2006-09-19 Intel Corporation Gating for dual edge-triggered clocking
KR100890041B1 (ko) * 2006-12-29 2009-03-25 주식회사 하이닉스반도체 반도체 소자의 클럭 버퍼 회로
US7710155B2 (en) * 2007-04-20 2010-05-04 Oracle America, Inc. Dynamic dual output latch
US20090108875A1 (en) * 2007-10-24 2009-04-30 International Business Machines Corporation Structure for a Limited Switch Dynamic Logic Cell Based Register
US7414436B1 (en) * 2007-10-24 2008-08-19 International Business Machines Corporation Limited switch dynamic logic cell based register
US8570068B2 (en) * 2010-04-28 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit for reducing negative bias temperature instability
US8476947B2 (en) * 2011-11-14 2013-07-02 Altera Corporation Duty cycle distortion correction circuitry
US8975936B2 (en) 2012-08-31 2015-03-10 Advanced Micro Devices, Inc. Constraining clock skew in a resonant clocked system
US8836403B2 (en) 2012-08-31 2014-09-16 Advanced Micro Devices, Inc. Programmable clock driver
US8742817B2 (en) 2012-08-31 2014-06-03 Advanced Micro Devices, Inc. Controlling impedance of a switch using high impedance voltage sources to provide more efficient clocking
US8941432B2 (en) 2012-08-31 2015-01-27 Advanced Micro Devices, Inc. Transitioning between resonant clocking mode and conventional clocking mode
US8854100B2 (en) * 2012-08-31 2014-10-07 Advanced Micro Devices, Inc. Clock driver for frequency-scalable systems
US10809757B2 (en) * 2018-10-04 2020-10-20 Mediatek Inc. Clock buffer having low power, low noise and low spur
US11218137B2 (en) 2020-04-14 2022-01-04 Globalfoundries U.S. Inc. Low clock load dynamic dual output latch circuit
US11050414B1 (en) 2020-05-22 2021-06-29 Globalfoundries U.S. Inc. Dynamic single input-dual output latch

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2837855C2 (de) * 1978-08-30 1984-03-29 Siemens AG, 1000 Berlin und 8000 München Impulswandler zur Taktversorgung von digitalen Halbleiterschaltungen
US5306962A (en) 1990-11-27 1994-04-26 Hewlett-Packard Company Qualified non-overlapping clock generator to provide control lines with non-overlapping clock timing
US5124572A (en) 1990-11-27 1992-06-23 Hewlett-Packard Co. VLSI clocking system using both overlapping and non-overlapping clocks
US5083049A (en) * 1991-05-10 1992-01-21 Ast Research, Inc. Asynchronous circuit with edge-triggered inputs
US5675273A (en) * 1995-09-08 1997-10-07 International Business Machines Corporation Clock regulator with precision midcycle edge timing
US5760610A (en) 1996-03-01 1998-06-02 Hewlett-Packard Company Qualified universal clock buffer circuit for generating high gain, low skew local clock signals
US5726596A (en) 1996-03-01 1998-03-10 Hewlett-Packard Company High-performance, low-skew clocking scheme for single-phase, high-frequency global VLSI processor
US6111447A (en) * 1998-05-01 2000-08-29 Vanguard International Semiconductor Corp. Timing circuit that selectively triggers on a rising or falling input signal edge
US6181185B1 (en) * 1999-07-14 2001-01-30 Agilent Technologies Low mismatch complementary clock generator

Also Published As

Publication number Publication date
FR2811829A1 (fr) 2002-01-18
US6310499B1 (en) 2001-10-30

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090331