FR2810449A1 - Procede de formation de protuberances cylindriques sur un substrat pour circuits integres - Google Patents
Procede de formation de protuberances cylindriques sur un substrat pour circuits integres Download PDFInfo
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- FR2810449A1 FR2810449A1 FR0012770A FR0012770A FR2810449A1 FR 2810449 A1 FR2810449 A1 FR 2810449A1 FR 0012770 A FR0012770 A FR 0012770A FR 0012770 A FR0012770 A FR 0012770A FR 2810449 A1 FR2810449 A1 FR 2810449A1
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- substrate
- screening material
- forming
- galvanizing
- integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
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Abstract
Ce procédé de formation de protubérances cylindriques sur un substrat pour circuits intégrés comprend les étapes consistant à : former des circuits en cuivre (12) sur une plaquette (11) d'un substrat (1) à l'aide d'un procédé de galvanoplastie; couvrir la plaquette (11) d'un matériau de masquage; former des ouvertures dans le matériau de masquage en alignement avec les circuits en cuivre (12) qui se trouvent sur la plaquette (11); remplir les ouvertures de cuivre pur ou d'un métal à haut point de fusion par un procédé de galvanoplastie pour former des protubérances cylindriques; former une couche (16) d'alliage de soudure sur l'extrémité supérieure de chacune des protubérances cylindriques pour être à niveau avec la surface supérieure dudit matériau de masquage; et retirer le matériau de masquage pour ne laisser que les protubérances cylindriques (17), grâce à quoi l'opération d'accrochage de la matrice au substrat peut être facilitée.
Description
Procéde de formation de protubérances cylindriques sur un substrat pour circuits intégrés le procédé technologique classique des puces à bosses pour connecter une matrice 2' à un substrat l' (voir figures la et 1b), il est nécessaire de former des couches 21' de "métallurgie sous bosses" (UBM) à partir de l'entrée/sortie (E/S) de la matrice 2' et des bosses 22' d'alliage de soudure sur les couches UBM 21', puis de retourner la matrice 2' pour accrocher le substrat l' (des circuits en cuivre 12' ont déjà été formés sur la plaquette 11' du substrat 1'). Ensuite, on insère une matière de remplissage 3' entre 1e substrat l' et la matrice 2'.
Toutefois, les bosses 22' faites d'un alliage de soudure vont fondre dans un procédé à 100---350 degrés Celsius si bien que la force gravitationnelle va abaisser la matrice 2', réduisant ainsi la distance séparant les bosses 22' de la matrice 2' et du substrat l' ce qui accroît par conséquent la difficulté à insérer la matière de remplissage 3'. Par conséquent, ce procédé donne toujours lieu à des bosses cylindriques défectueuses, dont le nombre ne peut pas être réduit.
Par conséquent, un objet de la présente invention est de pro poser un procédé de formation de bosses cylindriques sur un substrat pour circuits intégrés qui peut éviter et réduire les inconvénients sus mentionnés.
La présente invention concerne un procédé de formation de protubérances cylindriques sur un substrat pour circuits intégrés qui comprend les étapes consistant à couvrir le substrat d'un matériau de masquage, former des ouvertures dans le matériau de masquage pour s'aligner avec les circuits en cuivre du substrat, remplir les ouvertures de cuivre pur ou d'un métal à haut point de fusion pour former des bosses cylindriques, puis former une couche d'alliage de soudure au sommet de chacune des bosses cylindriques.
L'invention sera mieux comprise à la lecture de la description détaillée d'un exemple non limitatif illustré par les dessins d'accompa gnement, dans lesquels les figures la et lb illustrent un procédé classique d'encapsu- lation de puces à bosses; les figures 2a, 2b, 2c, 2d, 2e et 2f illustrent un exemple de procédé de formation de protubérances cylindriques sur un substrat pour circuits intégrés; et la figure 3 illustre comment une matrice est accrochée au substrat selon la présente invention au moyen d'une technique de puce à bosses.
En référence aux figures 2a à 2f, le procédé de formation de protubérances cylindriques sur un substrat selon la présente invention comprend les étapes consistant à a. former des circuits en cuivre 12 sur une plaquette 11 d'un substrat 1 à l'aide d'un procédé de galvanoplastie classique (figure 2a); b. couvrir la plaquette 11 d'un matériau de masquage 13 (fi gure 2b), le matériau de masquage 13 ayant une épaisseur égale à la hauteur de la protubérance cylindrique 17 mentionnée plus loin; c. former des ouvertures 14 en alignement avec les circuits en cuivre 12 sur le matériau de masquage 13 (figure 2c); d. remplir les ouvertures 14 de cuivre pur ou d'un métal à haut point de fusion 15 par un procédé de galvanoplastie classique pour former des protubérances cylindriques (figure 2d); e. former une couche d'alliage de soudure sur l'extrémité supérieure de chaque protubérance cylindrique pour être à niveau avec la surface supérieure du matériau de masquage 13 (figure 2e); et f. retirer le matériau de masquage 13 pour ne laisser que les protubérances cylindriques 17 (figure 2f).
Les protubérances cylindriques 17 sont connectées à une ma trice 2 à l'aide d'une technologie de puce à bosses. Etant donné que les protubérances cylindriques 17 sont obtenues par galvanoplastie, la hauteur des protubérances cylindriques 17 peut être contrôlée avec précision, ce qui permet d'obtenir une distance adaptée entre le sub strat 1 et la matrice 2 et donc de faciliter l'insertion de la matière de remplissage. En outre, puisque l'extrémité supérieure de la protubéran ce cylindrique 17 comporte une couche d'alliage de soudure 16, il n'est nécessaire que de former une couche UBM 21 sur la matrice 2 et il n'est plus nécessaire de former des bosses en alliage de soudure sur la matrice 2, ce qui prévient tout risque d'endommager la matrice lors du processus de formation des bosses sur cette dernière.
Claims (1)
1. Procédé de formation de protubérances cylindriques sur un substrat pour circuits intégrés qui comprend les étapes consistant à a. former des circuits cuivre (12) sur une plaquette (11) d'un substrat (1) à l'aide d'un procédé de galvanoplastie; b. couvrir ladite plaquette (11) d'un matériau de masquage (13); c. former des ouvertures (14) dans ledit matériau de masqua- ge (13) en alignement avec les circuits en cuivre (12) qui se trouvent sur ladite plaquette (11); d. remplir lesdites ouvertures (14) de cuivre pur ou d'un mé tal à haut point de fusion (15) par un procédé de galvanoplastie pour former des protubérances cylindriques; e. former une couche (16) d'alliage de soudure sur l'extrémité supérieure de chacune desdites protubérances cylindriques pour être à niveau avec la surface supérieure dudit matériau de masquage (13); et f. retirer ledit matériau masquage (13) pour ne laisser que les protubérances cylindriques (17).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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TW089111780A TW447060B (en) | 2000-06-15 | 2000-06-15 | Method for growing a columnar bump on an integrated circuit substrate |
Publications (1)
Publication Number | Publication Date |
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FR2810449A1 true FR2810449A1 (fr) | 2001-12-21 |
Family
ID=21660101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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FR0012770A Pending FR2810449A1 (fr) | 2000-06-15 | 2000-10-06 | Procede de formation de protuberances cylindriques sur un substrat pour circuits integres |
Country Status (5)
Country | Link |
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US (1) | US6390356B1 (fr) |
JP (1) | JP2002012997A (fr) |
DE (1) | DE10051140A1 (fr) |
FR (1) | FR2810449A1 (fr) |
TW (1) | TW447060B (fr) |
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JP3735526B2 (ja) | 2000-10-04 | 2006-01-18 | 日本電気株式会社 | 半導体装置及びその製造方法 |
TWI313507B (en) | 2002-10-25 | 2009-08-11 | Megica Corporatio | Method for assembling chips |
TWI245402B (en) | 2002-01-07 | 2005-12-11 | Megic Corp | Rod soldering structure and manufacturing process thereof |
US8294279B2 (en) | 2005-01-25 | 2012-10-23 | Megica Corporation | Chip package with dam bar restricting flow of underfill |
WO2007074351A1 (fr) * | 2005-12-29 | 2007-07-05 | Infineon Technologies Ag | Substrat avec plots de contact de qualité améliorée |
CN101590998B (zh) * | 2009-06-25 | 2011-04-13 | 上海交通大学 | 毛细管电泳芯片制备方法 |
US20150195912A1 (en) * | 2014-01-08 | 2015-07-09 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Substrates With Ultra Fine Pitch Flip Chip Bumps |
CN105448716B (zh) * | 2014-06-20 | 2018-09-04 | 中芯国际集成电路制造(上海)有限公司 | 基于金属纳米点沟道的晶体管的制造方法及制得产品 |
CN105895580A (zh) * | 2016-06-30 | 2016-08-24 | 华进半导体封装先导技术研发中心有限公司 | 半导体封装金属互连结构的制作工艺 |
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US5759737A (en) * | 1996-09-06 | 1998-06-02 | International Business Machines Corporation | Method of making a component carrier |
US5775569A (en) * | 1996-10-31 | 1998-07-07 | Ibm Corporation | Method for building interconnect structures by injection molded solder and structures built |
US5902686A (en) * | 1996-11-21 | 1999-05-11 | Mcnc | Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures |
US5984166A (en) * | 1997-07-09 | 1999-11-16 | Mask Technology, Inc. | Process for creating fine and coarse pitch solder deposits on printed ciruit boards |
-
2000
- 2000-06-15 TW TW089111780A patent/TW447060B/zh not_active IP Right Cessation
- 2000-10-06 FR FR0012770A patent/FR2810449A1/fr active Pending
- 2000-10-16 DE DE10051140A patent/DE10051140A1/de not_active Withdrawn
- 2000-10-23 US US09/693,951 patent/US6390356B1/en not_active Expired - Fee Related
- 2000-10-26 JP JP2000326797A patent/JP2002012997A/ja active Pending
Non-Patent Citations (1)
Title |
---|
YAMADA H ET AL: "A FINE PITCH AND HIGH ASPECT RATIO BUMP FABRICATION PROCESS FOR FLIP-CHIP INTERCONNECTION", 1995 JAPAN IEMT SYMPOSIUM. PROCEEDINGS OF THE 1995 JAPAN INTERNATIONALELECTRONIC MANUFACTURING TECHNOLOGY SYMPOSIUM. OMIYA, DEC. 4 - 6, 1995, PROCEEDINGS OF THE (JAPAN) INTERNATIONAL ELECTRONIC MANUFACTURING TECHNOLOGY SYMPOSIUM, NEW YORK, IEEE, US, 4 December 1995 (1995-12-04), pages 121 - 124, XP000686760, ISBN: 0-7803-3623-2 * |
Also Published As
Publication number | Publication date |
---|---|
DE10051140A1 (de) | 2001-12-20 |
US6390356B1 (en) | 2002-05-21 |
JP2002012997A (ja) | 2002-01-15 |
TW447060B (en) | 2001-07-21 |
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