FR2805058A1 - COMPUTER STRUCTURE FOR A PORTABLE DATA MEDIUM - Google Patents

Abstract

It includes the arrangement of a portable data medium with means for storing an application program consisting of a sequence of instructions as well as a processor unit which processes each of the instructions on which a data indicator is directed. A transfer unit (60), which is connected with the processor unit (10) and the memory means, passes the instruction indicator (22) to the next instruction to be processed and the setting of the instruction. The instruction indicator (22) for the next instruction to be processed is activated by the execution of each instruction last processed.

Description

DU0 SPICATA, X2805058

FROM PL! IC; ATA &

  IT STRUCTURE FOR A SUPPORT

PORTABLE DATA

  The invention relates to the arrangement of a portable data medium for the execution of interpretive program codes. In particular, the invention relates to a computer structure for a portable data carrier, a method for producing and interpreting an application program as well as a set of operating means for the computer structure. In addition, the invention relates to a portable data carrier with a computer structure for execution

an application program.

  It is common practice to carry out data processing processes in which useful data fixed in advance is processed by the use of portable data carriers, in particular in the form of smart cards. A development trend tends to improve the flexibility of such intelligent portable data carriers as well with regard to the achievable functionalities.

  as regards the compatibility of the participating components. According to a proposal

  sition known from document EP-A-794 519, the operating system of a smart card must be trained as an interpretation system so that the program code to be supported is transformed into specific code of processor and executable by the card processor. The interpretation system proposed allows the reloading of program codes on a smart card and makes it possible to execute a program by different processors. The interpretation of the program codes to be supported, however, results in a noticeable reduction in the speed of support, for example compared to a program code obtained by compilation.

  To make possible a higher execution speed, the document USA-

  367 685 proposes the use of a hybrid interpretation-compilation system, compilation and interpretation being activated one behind the other. The code of

  application program is first transmitted by compilation in an intermediate format

  executable diary, which is then interpreted. In the intermediate format program code, the symbolic references contained are replaced in a l145FRdoc - 5 féwricr2001 - 1113

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  first interpretation loop with numerical references. Interpretation is controlled by a main interpretation routine. During the execution of the interpretation, the main interpretation routine reads an instruction to be taken in charge then calls a corresponding program sequence, written in machine language and which is immediately executable by the processor unit, program sequence which is then executed by the processor unit. After the execution starts, the processor unit continues with the interpretation of the following instruction. During the execution of a program sequence in machine language in a memory, the address of the next instruction to be interpreted is generally kept in the stacked memory area of the main memory associated with

the processor unit.

  The problem which the invention proposes to solve is to obtain an interpretive computer structure for a portable data medium, so that the

  execution speed of an application program is further increased.

  This problem is solved by a computer structure for a portable data medium with memory means for memorizing an application program consisting of a sequence of instructions and with a processor unit for the interpretative execution of the application program, each instruction, to which an instruction indicator is directed, being processed, characterized by a unit

  transfer device connected with the processor unit, with the memory means

  the application program and with the instruction indicator, transfer unit

  which includes at least one logic program element, which indicates an ampli

  adjustment step study, and transfer unit which adjusts the instruction indicator after the execution of the processing of an instruction each time at the amplitude of adjustment step indicated in a logic program element. The computer structure according to the invention is characterized in that it provides for the setting of the instruction indicator designating the next application program instruction to be supported, a transfer unit specially provided for this. It makes it unnecessary to store the return address in the memory stack. Thus, the economy of transfer and return operations decreases the processing time of a program instruction. For this, the transfer unit is produced under the

  form of an invariable program inside the processor unit.

  According to another embodiment of the invention, the transfer unit is connected to a machine code memory unit, in which there is a program code, written in machine language and corresponding to each instruction to be interpreted from the program d 'application. The transfer unit is connected to a table storage unit which associates a program element of the machine code memory unit with each instruction of the application program. The unit of 1I145FRdoc - 5 Feb 2001 - 2/13

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  transfer is carried out in the form of a non-modifiable and achievable program by

the processor unit.

  The problem also is solved by a method for carrying out the interpretation of an application program composed of a sequence of instructions by a computer structure formed from a portable data medium, each of the instructions to be processed being indicated by an instruction indicator, characterized in that setting the instruction indicator to indicate the next instruction to

  process is produced by the execution of each instruction processed last. The Treaty-

  instruction occurs while a program element matches

  laying, written in machine language, is detected and executed. The corresponding program elements written in machine language are stored separately from the application program. At least one logic program element written in machine language is applied which produces a setting of

the instruction indicator.

  The program elements written in machine language and corresponding to the instructions are each isolated by a sequence of order, which produces the execution of a logical program element. A table is used to detect a program element written in machine language and corresponding to an instruction of an application program, a table which associates the address of a program element written in machine language with each possible instruction of a application program. The method according to the invention has the advantage, for linking the support of an application program, that no main attack interpretation program is necessary. The adjustment of the instruction indicator to designate each of the instructions to be taken care of is carried out from each of the

  instructions executed last.

  The problem posed above is also solved by a set of operating means for the implementation of a computer structure of a portable data carrier for the interpretive execution of an application program composed of a sequence of instructions, with a first program unit which makes a processor unit executing the computer structure capable of finding each instruction to be processed next, of the application program, with a second program unit which comprises program elements, represented in machine language immediately executable by the processor unit, program elements which each correspond to an instruction fixed in advance in an application program and the execution of which they produce, as well as with a third program unit which includes at least one logic program element written in machine language, and which constrains the IT structure to 18145ENdoc - 5 f Évrie 2001 - 3/13

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  transmit the rest of the program execution to the first program unit.

  The program elements are isolated from the second program unit each by an order sequence which compels the executing processor unit to execute a logic program element. The first program unit of the processor unit prepares information which indicates in the second memory unit the program element to be processed next. The first program unit forces the processor unit to determine an indicator, so that it indicates in the application program the next instruction to be processed. The first unit of

  program uses the instruction to be processed and designated by the indicator to determine

  information on the program element to be executed next.

  The invention includes a program unit containing the program code.

  gram which can be executed by the processor unit and at least one logic program element, which sets the instruction indicator on each

  instructions executed thereafter. A main routine interpretation device

  cipal causing the support of the application program is therefore no longer necessary. Each program element obtained from a program code executable by the processor unit includes a program sequence, which

  branches off to a logical program element.

  The invention also relates to: - a portable data medium with an IT structure for the execution of an application program, characterized in that the IT structure is constituted as described above; the use of the method for carrying out the interpretation of an application program described above for the operation of a portable data medium having a computer structure for the execution of an application program ; the use of all the operating means constituting a computer product for a computer structure device of a support

  portable data suitable for executing an application program.

  An exemplary embodiment of the invention is explained below with reference to the drawing in which:

  Figure 1 shows the structure of a proposed IT structure.

  Figure 2 shows the operating mode of this IT structure.

  Figure 3 shows the process of taking over a program

of application.

  Figure I shows the proposed IT structure, with the efficient links

  these functional and the elements involved. A physical production platform for the structure represented can be, in particular, the computer system of an 18145ENdoc - February 5, 2001 -4/13

2805058

  portable data carrier, preferably in the form of a smart card,

  say a considerably reduced system with regard to its physical resources

  ques. The heart of the structure shown in Figure I constitutes a process unit

  seur 10 central, which is formed in a conventional manner per se for the execution of s interpretation of program codes written in machine language. In the central processor unit 10 (CPU) are made a first indicator setting device (IP) 20 for setting an instruction indicator 22 as well as a second indicator setting device (PC) 30 for setting a program indicator 32. The instruction indicator 22 designates an address of a first memory area 40 (application program memory), in which is located

  an application program consisting of a plurality of simple instructions.

  The program indicator 32 indicates a starting address in a second memory area 50 in which there is a machine code written in language

  machine and executable by the central processor unit 10.

  The instruction indicator adjuster 20 is connected to a transfer unit 60 by a bidirectional signal link 24, transfer unit 60 which is designated subsequently as internal interpreter. The instruction indicator device communicates to the interpreter the position of the instruction indicator 22 by the signal link 24. In the opposite direction, the internal interpreter 60 causes the adjustment of

instruction indication 22.

  The internal interpreter 60 is connected to the second indicator adjustment device by means of another signal link 34. The interpreter thus constrains the device

  indicator setting to activate program indicator 32.

  The internal interpreter 60 is linked to the memory area 40 of the application program by means of another signal link 62. The signal link 62 thus serves to extract the content of the address designated by the instruction indicator 22 in

  the storage area of the application program 40.

  Starting from the internal interpreter 60, an address indicator 64 is additionally directed to a third memory area (of starting addresses) 70. To do this,

  finds a table, which associates a starting address with each of the instructions extracted

  tes of the storage area 40 of the application program, starting address which designates a program element 500, 520 executed in machine language in the second memory area 50. The program indicator 32 coming from the unit

  of central processor 10 is directed to the starting address.

  A fourth memory area 80 (stacking) is associated with the second memory area 50 by a bidirectional data link 52, and serves as

  processor unit memory 10.

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  The technical realization of the structure shown in Figure I in a hardware base is carried out taking into account as good an opportunity as possible adapting to the given hardware devices. In an advantageous embodiment, the first, second and third memory areas 40, 50, 70 are produced in the form of an EEPROM memory, the stack 80 in the form of a

  RAM memory. The internal interpreter 60 is suitably represented by a micro-

  program stored in a ROM memory, the indicating devices 20, 30

  being registers of the central processor unit 10.

  FIG. 2 shows the operating mode of the system represented in FIG. I. The first memory area 40 is occupied by an application program, whose instructions have the form of a byte code and whose instruction indicator 22 is pointed to a first instruction 42 in byte code of

application program.

  The internal interpreter 60 extracts the instruction 42 in the form of byte code designated by the instruction indicator 22 and determines a program element 500, 520 written in machine code and moving the instruction 42 in byte code in the second zone memory 50. For this, it uses the table stored in the third memory area 70, a table which associates with each instruction 42, 44 in byte code included in the syntax in byte code, the starting address 76, 78 of a program element 500, 520 in machine code carrying out the instruction in the second memory area 50. The instructions 42, 44 in byte code are represented on the table in the third memory area 70 in continuous order by an offset value brought back at the start of the table, offset value which constitutes a continuous index 72, 74. The index 72, 74 is directly derived in an appropriate manner from the representation of the instructions 42, 44 in byte code in the first memory area 40 pa r taking into account the word length of the starting addresses 76, 78. In the case of a representation in current byte code of the starting addresses, it results, as shown in FIG. 2, from the multiplication of instructions 42, 44 in byte code in the first memory area 40 with the number 2. The internal interpreter 60 directs the address indicator 64 to the index 72, 74 corresponding each time to an instruction 42, 44 in code byte in the third memory area 70, and it extracts the associated starting address 78.

  In accordance with the starting address 78 found, the internal interpreter 60 trans-

  puts a command to the indicating device 30 in the process unit

  central unit 10 by signal link 34, control instruction on which the indicating device 30 directs the program indicator 32 to the starting address designated in the second memory area 50. The program element 500, 520 I18145EN .doc - February 5, 2001 - 6/13

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  which is deposited in this area and which is formed by a sequence of machine code sequences, is executed by the central processor unit 10. Each program element 500, 520 includes for this program steps, which carry out the instruction 42, 44 in byte code at the base. At the end of each program element 500, 520, there is a following sequence of instructions 540, 550, which the central processor unit 10 compels to execute a logic program element 600,

610, 620.

  The logic program element 600, 610, 620 does not correspond to an instruction in byte code of an application program, but acts as part of the internal interpreter 60. The logic program element is preferably also located in the second memory area 50 and is composed, like the program elements 500, 520, of a code written in machine language and executable directly by the central processor unit 10 . A first sequence of instructions 612, 622 of the logic program element 610, 620 forces the indicator device 20 of the central processor unit 10 to direct the instruction indicator 22 to the next instruction 44 in byte code in the first memory area 40. Another instruction sequence 614, 624 acts so that the internal interpreter 60 sets the address indicator 64 directed to the third memory area 70 to detect the starting address 76 , 78, belonging to an instruction 44 in byte code, of an executable program element 500, 520, and to cause the execution of

this instruction.

  Frequently, different instructions of an application program require

  try different steps to adjust the instruction indicator. Of

  jump instructions pretty much generally define the position of the

  instruction tutors, so adjustment by a logic element is not necessary

  to be. In a typical application program present in the form of byte code, instructions 42, 44 in byte code generally show operands with different byte digits. In such cases, there are suitably provided several logic program elements 600, 610, 620, which cause an adjustment

  of the instruction indicator 22 according to different progression steps.

  A first logic element 600 is used for this to execute the jump instructions. It does not have an instruction indicator 22 setting, but only has an instruction sequence which acts so that the internal interpreter 60

  sets the address indicator 64 for the detection of the starting addresses 76, 78 appear-

  relating to an instruction in predetermined byte code of an executable program element 500, 520, in order to constrain its execution. Other program elements

  logic 610, 620 result from the structure of the syntax in byte code. If the instruc-

  byte code have a preferred length, significantly predominate 18145EN.doc - 5 fwier 2001. 7/13

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  instructions with one or two bytes, which are appropriately placed on the logic elements 610, 620 selected and of preferred length. A logic program element 610 causes by an instruction indicator 26 acting on the first adjusting device (IP) 20, the setting of the instruction indicator 22 to one byte and another logic program element 620 causes the adjustment two bytes. Firstly, the instruction sequence 612 acting on the position of the instruction indicator 22 consists of an incrementation, and secondly consists of an addition 622 of the number two. Similarly, other logic program elements can be installed allowing other steps to be obtained

progress.

  In accordance with the different jump amplitudes caused by the various logic program elements 600, 610, 620, the program elements 500, 520 corresponding to the instructions 42, 44 in byte code, are isolated by different program sequences 540, 550 for calling the logic program elements 600, 610, 620. A first program sequence 540 causes the calling of a logic program element 610 which leads to the incrementation of the instruction indicator 22 by a byte, while another program sequence 550 calls a logic program element 620,

  which leads to a setting of the instruction indicator 22 to two bytes.

  Figure 3 shows on a flowchart the sequence of general steps when taking charge of an application program with the help of the proposed internal interpreter. The sequence of steps begins, in step 100, with the positioning of the instruction indicator 22 on the first instruction, that is to say on the first instruction in byte code, of the application program by the indicator adjustment device 20 arranged in the central processor unit 10. The central processor unit 10 mentions the position of the instruction indicator 22 subsequently reached, to the internal interpreter 60, which corresponds to step 102, which continues taking over. The internal interpreter 60 then extracts into the first memory area 40

  the instruction in byte code designated by the instruction indicator 22, which corresponds to

  lays at step 104, and determines the index 72 corresponding to the instruction in byte code on the table in the third memory area 70. In accordance with the determined index, the interpreter draws from the table in the area of memory 70 the starting address of a program element in machine code, carrying out the instruction in byte code, in the second memory area 50, which corresponds to step 106, and

  constrains the indicating device 30 in the central processor unit 10 to position-

  ner program indicator 32 on the starting address found, which corresponds to step 108. The program element in machine code 500, 520 designated by 18145EN.doc - 5 fvrir 2001 - 8/13

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  the starting address is executed by the central processor unit 10, which corresponds to

  lays in step 110. Constraint by the program sequences 540, 550 each sent to a logic program element 600, 610, 620 at the end of each program element 500, 520, the central processor unit 10 calls for new each time the internal interpreter 60 upon completion of the execution of a program element 500, 520, which corresponds to step 112 and delivers to the internal interpreter 60 the continuation of the management of the program, which corresponds to step 114. The internal interpreter 60 then constrains, in accordance with the proposal by the logic program element 540, 550 executed last, the indicator adjustment device 20 to adjust the instruction flag 22 and starts again

  the execution of step 100 and following.

  The instructions in steps 100 to 114 of the flowchart shown in Figure 3, can be summarized as follows - in step 100 in the central processing unit CPU, adjust the first adjustment device (IP, 20) according to the proposal of the 'logical element; - in step 102: in the central unit, announce the first IP adjustment device to the internal interpreter (II, 60); - in step 104: in the internal interpreter II, read the byte code designated by the first IP adjustment device; - in step 106 in the internal interpreter II, determine the starting address from the table; - in step 108: in the internal interpreter, place the second adjustment device (PC, 20) on the starting address; - in step 110: in the central processing unit CPU, execute the program element in machine code; - in step 112: in the central processing unit CPU, go to the logic program element; in step 114: in the central processing unit CPU, implement the logic element. Of course, the present invention is not limited to the embodiments described and shown, but it is susceptible of numerous variants accessible to

  a person skilled in the art without departing from the invention.

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Claims (14)

  1.- Computer structure for a portable data carrier with memory means for storing an application program consisting of a sequence of instructions and with a processor unit for the interpretive execution of the application program, each instruction to which is directed an instruction indicator being processed, characterized by a transfer unit (60) connected with the processor unit (10), with the memory means comprising the application program and with the instruction indicator (22), transfer unit (60) which comprises at least one logic program element (600, 610, 620), which indicates a range of adjustment steps, and which sets the instruction indicator (22) after the execution of the processing of an instruction (42) each time the step amplitude   indicated in a logic program element (600, 610, 620).   2. Computer structure according to claim 1, characterized in that the transfer unit (60) is connected to a unit (50) of machine code memory, in which there is a program code (500, 520), written in machine language and corresponding to each instruction (42, 44) to be interpreted in the application program. 3. Computer structure according to claim 1 or 2, characterized in that the transfer unit (60) is connected to a unit (70) for storing tables which associates a program element (500, 520) of the machine code memory unit (50)   at each instruction (42, 44) of the application program.   4.- IT structure according to any one of claims 1 to 3,   characterized in that the transfer unit (60) is designed as a   program not modifiable and achievable by the processor unit (10).   5.- Method for producing and interpreting an application program composed of a series of instructions by a computer structure formed of a portable data medium, each of the instructions to be processed being indicated by an indicator d instruction, characterized in that the setting of the instruction indicator (22) to indicate the next instruction (44) to be processed is produced by the execution of   each instruction (42) processed last.   18145EN.doc - 21 nmai 2001 - 10/13 l 2805058 6.- Method according to claim 5, characterized in that the processing of an instruction (42, 44) occurs while a program element (500, 520 )   correspondent, written in machine language, is detected and executed.   7.- Method according to claim 5 or 6, characterized in that the corresponding program elements written in machine language are stored so   separate from the application program.   8.- Method according to any one of claims 5 to 7, characterized in that   that at least one logical program element (600, 610, 620) written in   machine language and which produces an adjustment of the instruction indicator (22).   9.- Method according to any one of claims 5 to 8, characterized in that   that the program elements (500, 520) written in machine language and corresponding   laying down instructions are each isolated by an order sequence, which produces   execution of a logic program element (600, 610, 620).   10.- Method according to any one of claims 5 to 9, characterized in that   that a table is used to detect a program element (500, 520) written in machine language and corresponding to an instruction of an application program, a table which associates the address of a program element written in machine language at   each possible instruction of an application program.   I1.- Set of operating means for the implementation of a computer structure of a portable data carrier for the interpretive execution of an application program composed of a series of instructions, the instruction being processed being indicated by an instruction indicator, with a first program unit (60) which makes an executing processor unit (10) of the computer structure capable of finding each instruction (42, 44) to be processed next, of the application program, with a second program unit (50) which comprises program elements (500, 520) represented in machine language and immediately executable by the processor unit (10), program elements which each correspond to an instruction (42, 44) fixed in advance in an application program and the execution of which they produce, as well as with a third program unit (50) which comprises at least one logic program element (6 00, 610, 620) written in machine language, which indicates an amplitude of step of adjustment for the adjustment of the instruction indicator (22) and which constrains the 1I145EN doc - 21 ri201.11 / 13 12 2805058   IT structure to transmit following the execution of the program to the first program unit (60).   12.- set of operating means according to claim 11, characterized in that the program elements (500, 520) are isolated from the second program unit (50) each by an order sequence (540, 550) which forces the executing processor unit (10) to execute a logic program element (600, 610, 620). 13.- set of operating means according to claim 11 or 12, characterized in that the first program unit (60) of the processor unit (10) prepares information which indicates in the second memory unit (50 )   the program element (520) to be processed next.   14.- Set of operating means according to any one of the claims   tions 11 to 13, characterized in that the first program unit (60) forces the processor unit (10) to determine an indicator (22), so that it indicates   in the application program the next instruction to be processed.   15.- set of operating means according to claim 14, characterized in that the first program unit (60) uses the instruction (42, 44) to be processed and designated by the indicator (22) to determine the element information   program (500, 520) to be executed in succession.   16.- Portable data carrier with an IT structure for   the execution of an application program, characterized in that the structure informs   material is produced according to claim 1.   17. Use of the method according to claim 5, for the exploitation of a portable data medium having a computer structure for the execution an application program.   18. Use of the computer product according to claim 11, for a computer structure device of a portable data carrier capable of   running an application program. 18145EN.doc- 21 mn 2001 - 12/13