FR2803150A1 - Terminal adaptor format ISDN bus/USB bus converter having pin series selective earth/different potential connected indicating adaptor power consumption class. - Google Patents

Abstract

The terminal adaptor converts formats circulating on an ISDN bus (S) and information on a USB bus (18). There are a series of pins (61) which are selectively connected to earth or potential differences which indicate the class of power consumption of the adaptor.

Description

 The present invention relates to the field of modems, and more particularly to a terminal adapter providing the interface between a service integration digital network and a universal serial bus.

 An integrated services digital network ("ISDN", also referred to as "ISDN" - Integrated Service Digital Network) enables data such as voice or computer files to be transmitted at a high rate to terminals such as phone or computer.

FIG. 1 schematically represents a conventional terminal 2 of an integrated services digital network. The data comes from the communication network, for example the telephone network, via a switch 8, located upstream of the user. The terminal 2 comprises a digital network terminal 4 (TNR) connected on the one hand to the switch 6 via a bus 8 and on the other hand to various devices via another bus generally. These devices, on the user side, can be for example an equipment terminal 12 (TE) such as a telephone, or a terminal adapter 14 (TA) or modem, connected to a microprocessor device 16, such as a computer, the terminal adapter for adapting the format of the data on the bus S to make them assimilable by the microprocessor device 16. In Figure 1, the terminal adapter 14 is connected to the microprocessor device 16 by the 18. Although several types of connection are possible, it is advantageous to connect the microprocessor device 16 to the terminal adapter 14 via a universal serial bus (USB) 18. In this case , the bus S transport e data in ISDN format and the bus 18 data in USB format.

Figure 2 schematically illustrates how the data is transmitted on the S bus (ISDN standard) and 18 (USB standard). According to the ISDN standard (FIG. 2, line A), the transmission rate is 192 kilobauds, that is to say 192 kilobits / s, the information being distributed over three channels. Two trans channels carry data (B1 and B2 channels) and one channel (D channel) carries signaling data, such as B1 and B2 data interpretation protocols, control signals, etc. Among the 192 kilobits / s (kbits / s), 64 kbit / s are assigned to channel B1, 64 kbit / s are allocated to channel B2 (this corresponds to the bandwidth of a telephone channel), and 16 kbit / s are assigned to the channel D. The Bi, B2, and D channels are grouped in 250 microsecond frames, each consisting of a Bi channel, a B2 channel, and a D channel. The remaining 48 kbit / s are used to identify frames, synchronize, and so on. Finally, note that the bus S consists of two differential pairs, a differential pair ensuring the go of the data, and the other the return of the data.

 The USB standard (Figure 2, line B) provides a much higher data rate, currently equal to 12 Megabits / s (Mbps). Indeed, the microprocessor device 16 provides data processing much faster than the transmission on the communication network. In addition, the USB bus is a so-called "universal" bus, used for many devices. The microprocessor device, via its USB bus, therefore interrogates the various peripherals, including the adaptation terminal TA, in turn. It should be noted that the amount of information transmitted in one millisecond according to the ISDN standard is transmitted in less than 10 microseconds according to the USB standard. The scales used in Figure 2 have been expanded for reasons of clarity.

Figure 3 schematically shows the main elements of a conventional terminal adapter 20. The terminal adapter 20 comprises a line interface 22, receiving the bus S, connected to an ISDN interface 24. The ISDN interface 24 is a specific circuit adapted to write and read on the bus S. The interface 24 is furthermore connected to a microcontroller 26, one of whose roles is to interpret the information received from the interface 24. The microcontroller 26 writes the received received data into a RAM memory 28. Inversely, the microcontroller can read the data in FIG. memory 28 and formatting them for sending to the ISDN interface 24. All the memories necessarily associated with the microcontroller 26 have not been represented. A DMA ("Direct Memory Access") controller, connected to the microcontroller 26, reads and writes to the memory 28 and serves as a connection means between the memory 28 and a USB controller 30, also connected to the microcontroller 26. The USB controller is conventionally a programmable controller configurable in all the possibilities offered by the USB standard and it transmits the data B1, B2 interpreted to the downstream microprocessor device 16 via a line interface 32 and the bus 18. In addition, the Microcontroller 26 performs the stripping and coding / decoding according to the HIDLC format of the bits of the D channel, which are conveyed on the bus S according to this format, which is the data presentation format defined for the D channel in the 1431 standard of the ITU (International Telecommunication Union).

The function of the interface 24 is mainly to provide the microcontroller 26 data B1 and / or B2 received successively at each interval of 250 microseconds from the bus S, or to provide the data B1 and / or B2 from the microcontroller 26 to the S bus at a rate and duration compatible with the ISDN standard. The function of the USB controller 30 is mainly to store in the memory 28 data received from the USB bus, or to provide the USB bus data read in the memory 28, compatible with the USB standard. The microcontroller 26 has the main function of reading the information stored in the memory 28, interpreting it, and consequently controlling the USB controller 30 or the interface 24, the control of the interface 24 being done by applying the protocol defined in the ITU 1430 standard.

The previous terminal adapter has many disadvantages. Thus, it is bulky because it has many components, themselves voluminous. Moreover, most of these components, such as the microcontroller, are expensive and have a high consumption, which may be incompatible with the specifications of the USB and ISDN standards, and require external power supply. In addition, the USB controller used is oversized because it can be configured to all the possibilities of the USB standard.

Therefore, an object of the present invention is to provide a simple and economical terminal adapter.

 Another object of the present invention is to provide a reduced power terminal adapter.

Another object of the present invention is to provide a reduced size terminal adapter.

To achieve these objects, the present invention provides a terminal adapter adapted to ensure a format conversion between information flowing on an ISDN bus according to the ISDN standard and information flowing on a USB bus according to the USB standard, said ISDN bus connecting the terminal adapter to a communication network and said USB bus connecting the terminal adapter to a microprocessor device. The management of the terminal adapter and the processing of said information are exclusively provided by the microprocessor device, the only autonomous function of the terminal adapter being, when a communication arrives on the ISDN bus and said device is in a standby state, to switch said device from the state of standby state to activated. According to one embodiment of the present invention, the terminal adapter includes an ISDN interface for receiving a network or providing the network with ISDN information and a USB interface for providing or receiving information from said device according to the ISDN standard. USB standard.

According to one embodiment of the present invention, the terminal adapter comprises an access point accessible by said device, in which are stored interrupts for said device to interrupt its activities and manages the adapter terminal.

According to one embodiment of the present invention, the terminal adapter further comprises buffers for storing data waiting to be sent on the ISDN bus or the USB bus.

According to an embodiment of the present invention, said buffer memories have high and low filling thresholds, and a particular interruption is sent to the microprocessor device when one of said buffer memories has a filling greater than its upper filling threshold, or below its low fill threshold.

According to one embodiment of the present invention, the terminal adapter includes a subset for moving the microprocessor device from a sleep state to an enabled state when the network seeks to establish communication with said device.

According to one embodiment of the present invention, the power supply of the terminal adapter comes from the USB bus.

According to one embodiment of the present invention, the terminal adapter further comprises a first set of pins accessible by the microprocessor device and selectively connected to ground or potentials present in the terminal adapter to indicate the consumption class of said adapter. According to an embodiment of the present invention, the terminal adapter further assumes a second set of pins accessible by the microprocessor device and allowing communication between the microprocessor device and elements of the terminal adapter.

According to an embodiment of the present invention, the terminal adapter comprises a single integrated circuit.

These and other objects, features, and advantages of the present invention will be set forth in detail in the following description of particular embodiments given in a non-limiting manner with reference to the accompanying drawings, in which Figure 1, previously described, schematically represents a terminal adapter in its environment; Figure 2, previously described, schematically illustrates the data transfer format according to ISDN USB standards; Figure 3, previously described, shows a terminal adapter according to the prior art; and Figure 4 shows a terminal adapter according to the present invention.

 As discussed in connection with FIG. 3, ISDN processing is now performed locally at the terminal adapter 20, with the consequent presence of several large components such as a microcontroller and his associated memories.

In contrast, the terminal adapter according to the present invention behaves as an almost passive component that does not process the ISDN protocol, but leaves this function to the microprocessor of the downstream connected device 16. In fact, according to the invention, all the "intelligence", that is to say all the interpretation of the information conveyed on the bus is left to the downstream microprocessor and the terminal adapter of the present invention can be called invention a "modem without controller" or "soft modem". It is then possible for the modem according to the invention to be bulky and it may be an example as a simple bulge in a cable. In fact, only an autonomous function is left to the terminating adapter of the invention: that of "waking up" the microprocessor 16, that is to say from a state of wakeful state activated when the network seeks to establish a communication while the microprocessor 16 is in the standby state.

 The downstream microprocessor therefore only sees raw data (level 1 according to the ISO standard), which it interprets. It is downstream microprocessor that also manages the access to the communication network.

Leaving the downstream microprocessor in charge of all the information conveyed on the communication network goes against a prejudgment of the technique which until now considered a system in which all "intelligence" would be transferred out of the terminal adapter was not feasible. Indeed, many problems, considered insurmountable, must be solved.

Thus, a first concern of the person skilled in the art concerned the beginning of the communication. We know that when a communication is established, we have to go very quickly. Indeed, a user is chosen, it is necessary that the various devices of the user analyze the call and, if the call concerns them, they must indicate quickly that they take 'call, on pain of which the network of conrnmnication may consider that the user is absent or the device is in use. Also, another user device can occupy the channel for another use. As a personal computer waking state requires several seconds to "wake up", it was feared that this transition time from the sleep state to the active state, added to the various times of startup drivers ("drivers") USB would cause the line to be cut off before the computer took hold of the line.

 Another problem concerned the interpretation of the information contained in the D-channel. Indeed, this information, referred to as signaling, makes it possible to process the data of the channels B1 and B2, and it is necessary to keep the hand on the D-channel under penalty of lose the line. Since several terminals are connected to the channel D, it is also necessary to check that the channel D is available and, if necessary, to wait to acquire it, for an additional delay generally of indefinite duration, dissuading the person skilled in the art from making an adapter. terminal without controller.

Another problem to be solved was the problem of storing the information between two accesses of the microprocessor 16. In fact, it has been seen that, according to the USB standard, the microprocessor 16 makes an access every millisecond, whereas the information arrives at the bus S in a continuous flow. As mentioned, the prior art terminal adapter solves this problem with an oversized memory 28 and provided with its own management system (the DMA controller 29).

In addition, it is necessary to adapt the data rates, the latter arriving at the frame rate of the network (192 kbit / s, currently) and leaving the terminal adapter at the rate of the USB standard (12). Mbits / s, currently). The synchronization of the clocks made in the circuit 20 of the prior art (FIG. 3) using the memory 28, the DMA controller 29 and the USB controller under the control of the microcontroller 26, was not a priori easily achievable simply without these elements.

In addition, a modem without "intelligence" and transferring its management to an external microprocessor would require many interruptions and it was feared that it saturates the USB bus, because many devices can be connected and each require a time minimal access, jeopardizing the operation of the entire system.

In short, there were a number of prejudices in the art as to the feasibility of a controllerless terminal adapter providing the interface between an ISDN bus and a USB bus. The Applicant examined these prejudices and found that they were unfounded. It proposes a terminal adapter in which the data management is executed outside the terminal adapter, by an external microprocessor connected downstream of the terminal adapter and located for example inside a personal microcomputer. The proposed terminal adapter does not have a controller, it is simple and inexpensive, and optimally provides the interface functions between ISDN and USB standards.

Such an adapter is illustrated in FIG.

In FIG. 4, a dotted line 40 delimits an integrated circuit constituting the single integrated circuit of the terminal adapter according to the present invention. The components external to this integrated circuit are a quartz Q, illustrated in FIG. 4, as well as various line transformers and protection circuits or other passive components not shown. Incidentally, the terminal adapter of the present invention is supplemented by two plugs (not shown), one for the USB bus and another for the ISDN bus. The terminal adapter according to the present invention thus occupies an area of a few square meters and can, as mentioned, be located in a cable bulge.

In FIG. 4, the circuit 40 first comprises an ISDN interface 42 connected to the bus S. This interface 42 receives the information from the bus S and performs functions relating to the ITU standard 1430.

The interface 42 thus supplies the data of the channels B1, B2 and D to a block 43 (DATA MULTIPLEX INTERFACE) which demultiplexes them and supplies them respectively to first-in, first-out (FIFO) memories 44, 45 and 46, respectively storing the data of the channels B1, B2 and D. The interface 42 also feeds a block 50, called IT ("InTerruption"), responsible for producing and storing interrupt signals while waiting to provide them to the external microprocessor . The interface 42 also supplies a block 48, named DCA ("D Channel Access"), connected to the block 50. The block 48 detects an activity of the D channel and, through an interruption produced by the block 50 , switches the downstream microprocessor from a sleep state to the activated state if necessary. The block 50, as well as the FIFOs 44, 45 and 46, are connected to a USB interface block 52. The USB interface is connected to a USB bus 18, allowing the link with the outside of the circuit 40. In a classic way, the USB bus has four drivers, two for data and two for power.

The USB interface 52 is also connected, for communication with the communication network, to a block 54 called CS ("Control Status"), connected to the ISDN interface 42. The interface 52 is also connected to FIFO memories 44 ', 45' and 46 'respectively receiving the data of the channels B1, B2 and D to be transmitted on the network. The USB interface 52 is furthermore connected to a ROM block 60 whose role will be described below, the ROM block comprising a ROM-type storage element and external pins 61. Furthermore, each of the FIFOs 44 to 46 is connected to block 50, for, as will be seen below, the production of particular interrupts.

In addition, a register 62, called the GPIO register, is connected to the blocks 50 and 54, as shown in FIG. 4. The register 62 comprises several pins 63, eight for example, called GPIO pins (General Purpose Input Output). These pins are accesses allowing the communication of the external microprocessor, via the USB interface 52, with elements of the external adapter to the circuit 40. Thus, the external microprocessor can, for example, drive a light-emitting diode when a communication is established or to indicate the rate of a communication (64 or 128 kbit / s, for example). Conversely, these GPIO pins are a means for transmitting, via the block 50 and the USB interface, interrupts to the external microprocessor, such as an indication of overheating from a sensor in the terminal adapter. Moreover, a clock circuit 56, driven by external quartz Q, provides clock signals to the interfaces 42 and 52, and a block 58, called "REGUL", receives the power supplied by the USB bus and produces various stabilized and / or reference voltages. For example, the block 58 converts the 5 volts supplied by the USB bus to 3.3 volts to supply the interfaces 42 and 52. The block 58 also has, in the example shown, output terminals 58A, 58B allowing use, if desired, an external power supply instead of the power supply provided by the USB bus. Also, a test block 59 connected various elements of the circuit 40 is provided for industrial testing the circuit at the stage of its manufacture.

The architecture of circuit 40 above is only one example, and other architectures can be realized without departing from the scope of the invention. For example, the storage elements 44, 44 ', 45, 45', 46 and 46 'may be other storage elements than FIFOs and are not necessarily separate elements. Also, an interface adapter may be provided between the blocks 50, 54 and the ISDN interface 42, in the case where the interface 42 produced would not be compatible with the signals coming from said blocks 50 and 54.

The operation of circuit 40 will now be described.

According to the ISDN standard, any activation of an apparatus begins with the presence of a particular activity on the D-channel. Block 48 of the circuit 40 has the function of detecting such activity and provides a line selection detection signal ( LSD) to the external microprocessor (not shown) via block 50, interface 52, and USB bus 18. Upon reception of this signal, the external microprocessor, if it was in standby, goes into activation mode, and from now on, supports all the management of the terminal adapter and exchanges with the network. Thus, it then sends to the USB interface 52 activation signals which, via the block CS 54, control the ISDN interface 42 for which it synchronizes on the data arriving by the bus S and that it sends then a signal via the bus S indicating to the digital terminal of the network 4 which is synchronized. For the time being, the operations performed do not involve any processing of the D-channel information, and they can be performed quickly enough to respond to the network in the allotted time. When the network receives the response from the terminal adapter, it transmits a frame of a particular type (named INFO 4) that contains information about the destination of the data. This frame is received by the ISDN interface 42, and the signaling data D that it contains is written in the memory 46 and then transmitted to the external microprocessor via the USB interface 52. The external microprocessor processes these data D , and determines if it is affected by the current communication. If this is the case, the external microprocessor sends request data which is written into the memory 46 'via the USB interface 52. This data is intended to be sent on the D-channel of the S bus to indicate that communication can take place. Since the channel D transported by the bus S is a resource shared by all the devices connected to this bus, it is necessary for the ISDN interface 42 of the terminal adapter to take over the bus S. For this, the microprocessor external interface in the CS block 54, via the interface 52, a signal which commands the interface 42 to provide a sequence of predetermined data on the channel D of the bus S, and to verify that this sequence of data is accepted by the network, which is done by an "echo" of the predetermined data sent, that is to say that we find on the bus S the series of data transmitted. When this occurs, the interface 42 can write on the D-channel of the S bus the data read in the memory 461, and the communication is established between the network and the external microprocessor.

A communication is established. We know that, according to USB, a device ("device") has a configuration with access points ("end point"). In the described configuration which, it will be remembered, is an example only, the choice of eight access points has been made, respectively denoted EPO, EP1,..., EP7, and which correspond to blocks 54, 50, and memories 44, 44 ', 45, 45', 46 and 46 '. These access points represent the blocks in which the external microprocessor writes or reads data or control signals via the USB interface 52. Depending on the configuration chosen, the eight access points can be grouped in four possible ways. The basic configuration uses the EPO and EP1 access points to see if there is an on-line signal. Then, during the communication, it is also possible to use for example three other possible configurations, involving B1 + D, or B2 + D, or B1 + B2 + D, these configuration variants making it possible to limit the required bandwidth the USB bus using only the strictly necessary channels.

After the choice of the configuration used, the external microprocessor goes, every millisecond as described, access access points EP2 to EP7 according to the config ration used, to search or enter information. This information is taken, respectively provided) at the (current) rate of 12 Mbit / s. They must therefore undergo a format change. This is achieved by the FIFOs 44 to 46 '. The memories 44, 45 and 46, receiving data from the network, are registered at the rate of the ISDN standard and read at the rate of the USB standard, and the moire 44 ', 45' and 46 ', receiving data from the microprocessor external, are registered at the pace of the USB standard and read at the pace of the ISDN standard. To do this, the external quartz Q, whose oscillation frequency has been chosen equal to 15.36 MHz, which is a multiple of 192 kHz, drives a clock circuit 56 which includes an analog phase-locked loop ( PLL) supplying 48 Ihz to the USB interface 52. In the non-limiting example present, the ISDN interface 42 directly receives the frequency of 15.36 Mhz provided by the quartz and divides it by two, thus obtaining 7.68 Mhz. The interfaces 42 and 52 internally comprise digital phase-locked loops (not shown) respectively receiving said 48 ihz and <B> 7.68 </ B> Ihz, as well as the clocks of the USB ISDN buses. The output signals of these internal digital PLLs are signals of frequency equal to 192 kHz respectively, synchronized to the clock of the ISDN network, and 12 MHz, synchronized to the clock of the external microprocessor. They are used for writing and reading memoirs 44 to 46 '.

The FIFOs 44 to 46 'are sufficiently sized not to lose information due to the latency of the USB bus. Furthermore, we have seen that the terminal adapter according to the present invention is preferably powered by USB line. The memory consumption must therefore remain low and their size must not be too large. The latency between two accesses of the external microprocessor via the USB bus is in practice 1 millisecond, as has been indicated, even if the USB standard provides that a limited slip is possible in frequency. In the embodiment described, the FIFO memories for the B1 and B2 channels can store 32 bytes ("bytes") and the FIFOs for the D channel, 16 bytes, which corresponds to a latency of 4 milliseconds of the USB bus, and which is largely sufficient while maintaining a reasonable size of the FIFOs.

The external microprocessor, moreover, manages the FIFOs dynamically to prevent a clock slip from making a FIFO memory fill or empty and lose data or its synchronization. To do this, a low fill threshold and a high fill threshold are defined for each FIFO memory. When the filling of a FIFO memory is greater than the high threshold, the interrupt block 50 supplies the external microprocessor with an interrupt signal indicating the state of filling of the memory concerned. The external microprocessor then reacts by increasing the amount of data collected by the USB bus during subsequent accesses if it is a memory providing a transfer in the network direction - microprocessor, or by decreasing the amount of data provided if it is a memory ensuring the transfer in the microprocessor - network direction. Similarly, a filling of a FIFO memory below the low threshold is detected and reported in the same way to the external microprocessor, the reaction of the external microprocessor then being, according to the direction of the transfer of the memory in question, to reduce the amount of data taken or increase the amount of data provided during subsequent accesses.

It will be noted that the number of interrupts transmitted to the external microprocessor via the USB bus 18 is relatively high. In a terminal adapter according to the prior art, the management of the level of filling of the memories was ensured by the internal microprocessor and interrupt signals were not necessary. As discussed above, it was feared that the transmission of a large number of interrupt signals by a USB bus would cause malfunctions, with loss of interrupt signals. To avoid any such inconvenience, the terminal adapter according to the present invention provides for keeping interrupt signals in block 50 until they are actually read by the external microprocessor.

 Finally, any device connected to a USB bus contains descriptors ("descriptors"), which are codes to identify the device. Here, these descriptors are contained in the ROM block 60 connected to the USB interface 52, and contain information concerning the manufacturer of the device, the type of device, its consumption, etc.

It is possible for the terminal adapter to be supplemented by ancillary circuits, such as displays or an audio card, so that the consumption class of the terminal adapter can be modified. The class of consumption must be reported to the external microprocessor and, to do this, the present invention provides a number of pins 61 connected to the ROM block 60 to encode the consumption information of the terminal adapter. pins are for example connected to the ground or a positive voltage of the circuit and their state informs the external microprocessor of the consumption class to which the terminal adapter belongs.

Thus, the terminal adapter according to the present invention comprises only an integrated circuit. Its size is reduced its power consumption is low, so that it can be powered without difficulty by the power supply of the USB line. The terminal adapter according to the present invention provides the external microprocessor to which interrupts interrupts and raw data that the external microprocessor will interpret. The external microprocessor, once "awake" - if it was in standby - by the signal from block 48, provides all the internal management of the terminal adapter, including, as has been described, the monitoring of the filling of the terminals. FIFO memories. With regard to the interpretation of the data, for example, it makes decoding and / or error corrections and indicates to the network the faulty blocks, which were previously realized by the terminal adapter. The required processing and management time only takes up some 6 of the microprocessor capabilities, and this additional function does not limit the microprocessor, in any case for current microprocessors.

Of course, the foregoing description is only an exemplary embodiment only and the present invention is susceptible to various variations and modifications which will be apparent to the art. Thus, the circuit 40 performs a number of functions, and its architecture is subject to many variations without departing from the scope of the present invention. For example, other storage elements may be provided instead of the FIFOs. Also, the block 43 may be part of the interface 42. Similarly, the blocks 48, 54 may be included in one of the interfaces 42 or 52.

Claims (7)

A terminal adapter (14) capable of ensuring a format conversion between information circulating on an ISDN (S) bus according to the ISDN standard and information circulating on a USB bus (18) according to the USB standard, said ISDN bus connecting the terminal adapter to a communication network and said USB bus connecting the terminal adapter to a microprocessor device (16), characterized in that the management of the terminal adapter and the processing of said information are exclusive provided by the device (16), the only autonomous function of the terminal adapter being, when a communication arrives on the ISDN bus and the device (16) is in a standby state, to pass said device ( 16) from the standby state to an activated state. A terminal adapter according to claim 1, comprising an ISDN interface (42) for receiving from the network or providing the network with information according to the ISDN standard and a USB interface (52) for providing the device (16) or receiving device ( 16) information according to the USB standard. Terminal adapter according to claim 1, comprising an access point (50) accessible by the device (16) in which interrupts for the device (16) are stored so that it interrupts its activities and manages the device. the terminal adapter. Terminal adapter according to claim 1, further comprising buffers (44, 44 ', 45, 45', 46, 46 ') for storing data awaiting transmission to the ISDN bus or the USB bus . A terminal adapter according to claim 4, wherein said buffers have high and low fill thresholds, and wherein a particular interrupt is sent to the device (16) when one of said buffers has a padding greater than its own. filling threshold high, or lower than its low filling threshold. A terminal adapter according to claim, comprising a subset (48) for moving the device (16) from a sleep state to an enabled state when the network seeks to establish communication with the device (16). The terminal adapter of claim 1, wherein the power supply of the terminal adapter is from the USB bus. A terminal adapter according to claim 1, further comprising a first set of pins (61) accessible by the device (16) and selectively connected to ground or potentials present in the terminal adapter to indicate the class consumption of said adapter. The terminal adapter of claim 1, further comprising a second set of pins (63) accessible by the device (16) and allowing communication between the microprocessor device (16) and elements of the terminal adapter . <B> 10. </ B> Terminal adapter according to claim 1, characterized in that it comprises a single integrated circuit.