FR2800482B1 - Procede de traitement des instructions dans un processeur et processeur le mettant en oeuvre - Google Patents

Procede de traitement des instructions dans un processeur et processeur le mettant en oeuvre

Info

Publication number
FR2800482B1
FR2800482B1 FR0011605A FR0011605A FR2800482B1 FR 2800482 B1 FR2800482 B1 FR 2800482B1 FR 0011605 A FR0011605 A FR 0011605A FR 0011605 A FR0011605 A FR 0011605A FR 2800482 B1 FR2800482 B1 FR 2800482B1
Authority
FR
France
Prior art keywords
processor
processing instructions
implementing
processor implementing
instructions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0011605A
Other languages
English (en)
Other versions
FR2800482A1 (fr
Inventor
James Allan Kahle
Hung Qui Le
Charles Roberts Moore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2800482A1 publication Critical patent/FR2800482A1/fr
Application granted granted Critical
Publication of FR2800482B1 publication Critical patent/FR2800482B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
FR0011605A 1999-10-28 2000-09-12 Procede de traitement des instructions dans un processeur et processeur le mettant en oeuvre Expired - Fee Related FR2800482B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/428,399 US6654869B1 (en) 1999-10-28 1999-10-28 Assigning a group tag to an instruction group wherein the group tag is recorded in the completion table along with a single instruction address for the group to facilitate in exception handling

Publications (2)

Publication Number Publication Date
FR2800482A1 FR2800482A1 (fr) 2001-05-04
FR2800482B1 true FR2800482B1 (fr) 2003-06-13

Family

ID=23698735

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0011605A Expired - Fee Related FR2800482B1 (fr) 1999-10-28 2000-09-12 Procede de traitement des instructions dans un processeur et processeur le mettant en oeuvre

Country Status (2)

Country Link
US (1) US6654869B1 (fr)
FR (1) FR2800482B1 (fr)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050102494A1 (en) * 2003-11-12 2005-05-12 Grochowski Edward T. Method and apparatus for register stack implementation using micro-operations
US7278011B2 (en) * 2004-04-08 2007-10-02 International Business Machines Corporation Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table
US7269715B2 (en) * 2005-02-03 2007-09-11 International Business Machines Corporation Instruction grouping history on fetch-side dispatch group formation
US7475223B2 (en) * 2005-02-03 2009-01-06 International Business Machines Corporation Fetch-side instruction dispatch group formation
US20070198812A1 (en) * 2005-09-27 2007-08-23 Ibm Corporation Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
US7350056B2 (en) * 2005-09-27 2008-03-25 International Business Machines Corporation Method and apparatus for issuing instructions from an issue queue in an information handling system
US8219784B2 (en) * 2008-12-09 2012-07-10 International Business Machines Corporation Assigning and pre-decoding group ID and tag ID prior to dispatching instructions in out-of-order processor
US9104399B2 (en) * 2009-12-23 2015-08-11 International Business Machines Corporation Dual issuing of complex instruction set instructions
US8082467B2 (en) * 2009-12-23 2011-12-20 International Business Machines Corporation Triggering workaround capabilities based on events active in a processor pipeline
US9135005B2 (en) * 2010-01-28 2015-09-15 International Business Machines Corporation History and alignment based cracking for store multiple instructions for optimizing operand store compare penalties
US8495341B2 (en) * 2010-02-17 2013-07-23 International Business Machines Corporation Instruction length based cracking for instruction of variable length storage operands
US8938605B2 (en) * 2010-03-05 2015-01-20 International Business Machines Corporation Instruction cracking based on machine state
US8464030B2 (en) 2010-04-09 2013-06-11 International Business Machines Corporation Instruction cracking and issue shortening based on instruction base fields, index fields, operand fields, and various other instruction text bits
US8645669B2 (en) 2010-05-05 2014-02-04 International Business Machines Corporation Cracking destructively overlapping operands in variable length instructions
CN102789377B (zh) 2011-05-18 2015-09-30 国际商业机器公司 处理指令分组信息的方法和装置
GB2514618B (en) * 2013-05-31 2020-11-11 Advanced Risc Mach Ltd Data processing systems
US9513805B2 (en) * 2014-04-15 2016-12-06 International Business Machines Corporation Page table including data fetch width indicator
US10108423B2 (en) 2015-03-25 2018-10-23 International Business Machines Corporation History buffer with single snoop tag for multiple-field registers
US9367322B1 (en) 2015-07-27 2016-06-14 International Business Machines Corporation Age based fast instruction issue
US10983797B2 (en) * 2019-05-28 2021-04-20 International Business Machines Corporation Program instruction scheduling
US11249757B1 (en) * 2020-08-14 2022-02-15 International Business Machines Corporation Handling and fusing load instructions in a processor

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075844A (en) * 1989-05-24 1991-12-24 Tandem Computers Incorporated Paired instruction processor precise exception handling mechanism
EP0450658B1 (fr) * 1990-04-06 2001-08-01 Nec Corporation Système de traitement pipeline en parallèle pour des mots d'instruction de très grande largeur
EP0454985B1 (fr) * 1990-05-04 1996-12-18 International Business Machines Corporation Architecture de machine pour un jeu échelonnable d'instructions combinées
US5826055A (en) 1991-07-08 1998-10-20 Seiko Epson Corporation System and method for retiring instructions in a superscalar microprocessor
US5404557A (en) 1991-11-22 1995-04-04 Matsushita Electric Industrial Co., Ltd. Data processor with plural instruction execution parts for synchronized parallel processing and exception handling
US5896519A (en) * 1996-06-10 1999-04-20 Lsi Logic Corporation Apparatus for detecting instructions from a variable-length compressed instruction set having extended and non-extended instructions
WO1998006042A1 (fr) 1996-08-07 1998-02-12 Sun Microsystems, Inc. Procede et appareil permettant de decondenser des instructions longues
US5925124A (en) * 1997-02-27 1999-07-20 International Business Machines Corporation Dynamic conversion between different instruction codes by recombination of instruction elements
US5930491A (en) 1997-06-18 1999-07-27 International Business Machines Corporation Identification of related instructions resulting from external to internal translation by use of common ID field for each group
US6108768A (en) * 1998-04-22 2000-08-22 Sun Microsystems, Inc. Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system
US6324640B1 (en) * 1998-06-30 2001-11-27 International Business Machines Corporation System and method for dispatching groups of instructions using pipelined register renaming

Also Published As

Publication number Publication date
US6654869B1 (en) 2003-11-25
FR2800482A1 (fr) 2001-05-04

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Legal Events

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ST Notification of lapse

Effective date: 20060531

D3 Ip right revived
ST Notification of lapse

Effective date: 20140530