FR2800169B1 - METHOD AND DEVICE FOR ANALYZING DEFECTS IN DIGITAL LOGIC CIRCUITS - Google Patents

METHOD AND DEVICE FOR ANALYZING DEFECTS IN DIGITAL LOGIC CIRCUITS

Info

Publication number
FR2800169B1
FR2800169B1 FR0013441A FR0013441A FR2800169B1 FR 2800169 B1 FR2800169 B1 FR 2800169B1 FR 0013441 A FR0013441 A FR 0013441A FR 0013441 A FR0013441 A FR 0013441A FR 2800169 B1 FR2800169 B1 FR 2800169B1
Authority
FR
France
Prior art keywords
logic circuits
digital logic
analyzing defects
analyzing
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0013441A
Other languages
French (fr)
Other versions
FR2800169A1 (en
Inventor
Christoph Fritsch
Volker Lueck
Juergen Haufe
Peter Schwarz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of FR2800169A1 publication Critical patent/FR2800169A1/en
Application granted granted Critical
Publication of FR2800169B1 publication Critical patent/FR2800169B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
FR0013441A 1999-10-21 2000-10-20 METHOD AND DEVICE FOR ANALYZING DEFECTS IN DIGITAL LOGIC CIRCUITS Expired - Fee Related FR2800169B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE1999150838 DE19950838C2 (en) 1999-10-21 1999-10-21 Method and device for error analysis of digital logic circuits

Publications (2)

Publication Number Publication Date
FR2800169A1 FR2800169A1 (en) 2001-04-27
FR2800169B1 true FR2800169B1 (en) 2003-08-29

Family

ID=7926479

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0013441A Expired - Fee Related FR2800169B1 (en) 1999-10-21 2000-10-20 METHOD AND DEVICE FOR ANALYZING DEFECTS IN DIGITAL LOGIC CIRCUITS

Country Status (4)

Country Link
CH (1) CH694927A5 (en)
DE (1) DE19950838C2 (en)
FR (1) FR2800169B1 (en)
IT (1) IT1319009B1 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10119170A1 (en) * 2001-01-08 2005-04-07 Universität Leipzig Digital circuit failure analysis procedure emulates circuit at high clock speed with all inputs connected to shift register for examination on failure
DE10136703C1 (en) 2001-07-27 2003-04-17 Infineon Technologies Ag Logic device for testing an integrated circuit
DE102004040196B3 (en) * 2004-08-19 2006-04-06 Siemens Ag Logic circuit for simultaneous processing of functional data and test data in data group uses two identical signal state stores and data is transmitted over two separate paths
EP1980964B1 (en) 2007-04-13 2016-03-23 Yogitech Spa Method and computer program product for performing failure mode and effects analysis of an integrated circuit
CN111413584B (en) * 2020-03-19 2023-08-25 国网湖北省电力有限公司荆门供电公司 Power distribution network fault positioning linear programming method based on fault direction

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5383167A (en) * 1991-10-16 1995-01-17 Nextwave Design Automation Method and apparatus for histogram based digital circuit simulator
US5568380A (en) * 1993-08-30 1996-10-22 International Business Machines Corporation Shadow register file for instruction rollback
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
US5764079A (en) * 1996-03-11 1998-06-09 Altera Corporation Sample and load scheme for observability of internal nodes in a PLD
US5870410A (en) * 1996-04-29 1999-02-09 Altera Corporation Diagnostic interface system for programmable logic system development
US5822564A (en) * 1996-06-03 1998-10-13 Quickturn Design Systems, Inc. Checkpointing in an emulation system
US5771240A (en) * 1996-11-14 1998-06-23 Hewlett-Packard Company Test systems for obtaining a sample-on-the-fly event trace for an integrated circuit with an integrated debug trigger apparatus and an external pulse pin

Also Published As

Publication number Publication date
IT1319009B1 (en) 2003-09-19
CH694927A5 (en) 2005-09-15
DE19950838C2 (en) 2001-09-27
ITMI20002236A1 (en) 2002-04-17
DE19950838A1 (en) 2001-06-07
FR2800169A1 (en) 2001-04-27

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20130628