FR2795836A1 - Method of evaluation of timing of data processing device by executing program contained in memory while adding time of execution to form accumulated value of time during such operation - Google Patents

Abstract

The method involves defining for every instruction a time of execution of this instruction by a processor. The processor executes (46) a program contained in the memory, containing at least single instruction, while adding (43) during such operation, the time of execution to form an accumulated value of time. An Independent claim is included for: (a) a data processing device

Description

Method for counting the time in an information processing device, and associated device When two intelligent electronic devices are in dialogue with one another, a communication protocol must be set up to manage the agreement between these devices. It is the same for the communication between a microcomputer card and the reader of this card.

Several communication protocols have been designed and / or implemented such as the T = 1 protocol, called block protocol, or the most currently used which is the T = 0 protocol, or character protocol. In all these protocols, it is necessary to specify different rules guaranteeing a good communication, such as the recognition of the beginning of the emission, or the end of the emission.

In the communication architecture between the card and the reader, the card is considered as slave and the master reader. This means that it is always the reader who initiates the beginning of a dialogue. More specifically, the card is requested by the reader, by sending an order, and the card, after receiving this command, performs a certain treatment, then gives back the response to the command.

Note that the case of powering up the card is a special case in that it is by applying the appropriate voltage on the reset pin (reset) of the card component that the reader initiates the dialogue. We can therefore consider that it is a particular way of sending an outgoing order to the card. In response to this electrical excitation, the card performs the appropriate initialization processing, for example by resetting some variables to RAM, or assigning them initial values, and ends processing by transmitting the power-on response, or ATR (Answer To Reset).

We can distinguish several types of command # incoming command, with data accompanying it, or without data # outgoing command, with expected data back # or a combination of previous commands In all cases, the card must answer at least by one or two word (s) of state (s). And this answer must be returned to the reader at the latest one second after the end of receipt of the order. Practically, if one is on the side of the card, it must have a means to count down the time that elapses.

For the skilled person, the conventional means that he will use is the service of an assistant counter to the microcomputer. It will be armed at a value less than one second at the beginning of the process, and when it reaches the end of its count, it will notify the central unit of the card, by triggering an interruption. The person skilled in the art will have taken care to connect this interruption in the proper routine which will have the task of issuing a state of waiting word. But as cards, as marketed products, must meet a certain cost imposed by the market, their microcomputer is rarely equipped with a meter. In addition, the counter occupies a significant volume and therefore poses difficulties in the insertion phase of the chip in the plastic support. In current and near future art, new operating system platforms are coming. They still retain characteristics of the ancient art insofar as, as before, there is a basic operating system performing more or less generic tasks, such as the management of input I outputs, or the writing in memory nonvolatile type EEPROM, and sometimes accompanied by dedicated applications, for example an SME application (Electronic Money Carrier). But what is new is that these platforms are provided with a shell interpreter, or virtual machine, and a set of specific routines documented for use by the developers of applications in interpreted code, named APIs routines (from the English Application Program Interface), and a mechanism for downloading these applications.

These applications in interpreted code have two major characteristics that differentiate them from the process existing in the prior art.

The first is that these applications can be developed, not only by the platform provider, composed of the base operating system + interpreter + APIs, but they are more intended to be developed by a third party with the platform. form and programming specifications describing the highest layer of the platform, ie the interpreted language and APIS.

The second is that these applications are downloaded not during the debugging of the base operating system, but later, during the use phase of the card! Thus, once the application has been downloaded, all the code that is executed during a command card is the result of the mixed operation of the code of the base operating system and that of the interpreted code.

The basis of the solution according to the invention uses the fact that to execute the interpreted code, the base platform (base operating system + interpreter + APIs) must iteratively take each instruction of the downloaded application and interpret. There is therefore an iterative process during the execution of the interpreted code. The solution consists in inserting a new routine, which one will name routine of accumulation of duration, in the code managing this iterative process so that it is called at each iteration.

To this end, the invention relates to a method for counting time in an information processing device comprising processing means and storage means, characterized in that it comprises the steps of defining a table containing, for each instruction of a set of instructions to be executed by the processing means, a execution time of this instruction; -execute a program comprising at least one instruction by adding, at the time of execution of each instruction, the execution time of this instruction to a cumulative time value.

In a variant, the invention also relates to a method for counting time in an information processing device comprising processing means and storage means, characterized in that it comprises the steps of defining an array containing, for each instruction of a program to be executed by the processing means, a execution time of this instruction; -checking each instruction of the program by determining whether this instruction obeys at least one determined rule by adding, at the time of checking each instruction, the execution time of this instruction to a time accumulation value; comparing, at the time of the verification of each instruction, the cumulative time value with a time reference value; inserting into the program, at a location where the instruction being checked, an instruction defining an operation to be performed by the processing means, when the cumulative time value reaches the time reference value; and - executing the program by the processing means of the information processing device.

The invention also relates to the information processing device associated with this method.

Other details and advantages of the present invention will become apparent from the following description of a preferred but nonlimiting embodiment, with reference to the appended drawings in which FIG. 1 represents a data processing device cooperating with an object. portable; FIG. 2 is a table indicating, for each interpreted instruction of an application, its duration of execution; FIG. 3 is a table indicating, for each elementary instruction of the processing means, its duration of execution; FIG. 4 is an execution flow chart of an application incorporating a duration accumulation routine according to the invention; FIG. 5 is a reduced table indicating, for each interpreted instruction of an application, its duration of execution; FIG. 6 is an application verification flow chart incorporating a duration accumulation routine according to the invention; FIG. 1 represents a data processing device 1 cooperating with a portable object 8. The data processing device comprises, in a manner known per se, a microprocessor 2 to which a ROM 3, a RAM 4, a memory 5, 5 cooperating, with or without physical contact, with the portable object 8, and a transmission interface 7 enabling the data processing device to communicate with a data communication network. The data processing device 1 may also be equipped with storage means such as floppies or removable disks or not, input means (such as a keyboard and / or a pointing device of the mouse type) and means display, these different means not being shown in FIG.

The data processing device may be constituted by any computer device installed on a private or public site and capable of providing information management means or delivery of various goods or services, this device being installed permanently or portable. It may also be a device dedicated to telecommunications.

Moreover, the portable object 8 carries a chip including information processing means 9, a nonvolatile memory 10, a volatile working memory RAM 14, and means 13 for cooperating with the data processing device 1 This chip is arranged to define, in the memory 10, a secret zone 11 in which information once recorded, are inaccessible from outside the chip but only accessible to the processing means 9, and an accessible zone 12 which is made accessible from outside the chip by the processing means 9 for reading and / or writing information. Each zone of the non-volatile memory 10 may comprise a non-modifiable portion ROM and an modifiable portion EPROM, EEPROM, or constituted by RAM of the "flash" or FRAM type (the latter being a ferromagnetic RAM memory), that is to say ie having the characteristics of an EEPROM memory with further access times identical to those of a conventional RAM.

As a chip, it will be possible to use a self-programmable microprocessor with non-volatile memory, as described in US Pat. No. 4,382,279 in the name of the Applicant. In a variant, the microprocessor of the chip is replaced - or at least supplemented - by logic circuits. Indeed, such circuits are able to perform calculations, including authentication and signing, through the wired electronics, not microprogrammed. They may in particular be of the ASIC (Application Specific Integrated Circuit) type. Advantageously, the chip will be designed in monolithic form.

According to the invention, the portable object 8 stores, in its non-volatile memory 10, a table TAB-INS-DUREE (FIG. 2) which has two columns. A first column contains identifiers or codes I,, IZ, ......, I; , <B> ...... </ B> I, of n interpreted instructions constituting the code or program of an application written in advanced language, consisting of elements of this language and calls to API functions ( the English Application Program Interface, meaning Application Program Interface). The APIs functions are written in a set of instructions that can either be elementary or use other APIs functions: they perform a certain task. In a manner known per se, an application is intended to be interpreted by a virtual machine which is located in the non-volatile memory 10 of the portable object 8 and which is in the form of an interpreter code, hereinafter designated interpreter: the interpreter is responsible for translating each interpreted instruction into instructions belonging to a basic operating system of the processing means 9 and which are therefore directly executable by them.

A second column of the table TAB-INS-DUREE contains, for each of the interpreted instructions I, 12, ......, I; , <B> ...... </ b> h of the application, a respective duration T,, T2, ...., T; , ......, T ,, corresponding to the time that the processing means 9 make to execute the interpreted instruction considered. The way in which the durations T,, T2, ...., T are calculated; The manufacturer of the chip equipping the portable object 8 usually provides, in its documentation, a table (FIG. 3) giving, for each elementary instruction i, i2, .... ii, ..... in, as part of its base operating system, its duration t,, t2, <b> .... </ b> ti, ..... tm in number of cycles carried out by the processing means 9: knowing the frequency of execution of the elementary instructions, it is easy to translate this duration into a time expressed in seconds.In addition, each interpreted instruction is a juxtaposition of a number elementary instructions, for example, I; = (i2, i5, ii, ......, ik, <B> ..... </ B>, iP), so that its duration T; can be calculated as the sum of the respective durations of these elementary instructions, ie T; = t2 + t5 + ti + ...... + tk + ...... + tP. An operator can therefore, from the table in Figure 3, constitute the table water TAB-INS-DURATION.

In the case where an interpreted instruction can comprise several possible paths of elementary instructions, the operator will choose as duration of the interpreted instruction, the duration of the longest path. This method is acceptable because, by referring to the current encoding for a base platform (base operating system + interpreter + APIs functions), it can be seen that the execution time of the vast majority of interpretable instructions is around of 250 gs. And knowing that for the component of the 6805 family, an elementary instruction requires on average about 3 cycles, and that the normalized clock frequency is 3.57 MHz, we deduce that an elementary instruction runs on average in about 1 las, and therefore, the 250 las cited above represent about 250 elementary instructions. And so, for the few instructions to interpret having different processing sequences, the difference between one branch and another is a few tens of instructions, typically between 10 and 50 elementary instructions, or some 10 to 50 more lis to add the 250 us, which is relatively small compared to the second (= 106 las) which is the critical threshold, time in which the card, after receiving a command from the reader, must send a response to it.

FIG. 4 illustrates an example of use of the TAB-INSIDE table to allow a card to send a card to a card reader a waiting state as soon as a duration Tmax has elapsed since the beginning execution, by the card, of an order sent by the reader. The TAB-INS-DUREE array is considered to have been stored in the map. FIG. 4 represents the code, stored in a card, for executing an application comprising the n interpreted instructions I, at In <B>, </ B> in which a duration accumulation routine has been inserted allowing the card to send said wait status word. This code is contained in the interpreter (alternatively, the interpreter is not implemented in software but hardware, and the duration accumulation routine according to the invention is performed in software or hardware form). In step 41, the portable object 8 receives an order from the data processing device 1. In step 42, a time variable T is initialized to 0, and in step 43, the processing means 9 read the code I; the interpretable instruction that must be executed now and read, in the table TAB-INS-DURATION, the duration T; of this instruction they add to the time variable T. In step 44, the value of the time variable T is compared with the duration Tmax. If the time variable T is not less than the duration Tm ,,, it means that the execution of the current interpreted instruction I; will lead to exceeding the duration Tm # ,,: it is therefore necessary to send, in step 45, a waiting state word to the reader and then reset to 0 the time variable T (by return to step 42). Following step 44 in the case where the time variable T is shorter than the duration T ".x, the interpreter of the card interprets the interpreted instruction I, then executes it (step 46). step 47, the processing means 9 test whether the instruction interpreted is the drennière to execute.If the affirmative, the portable object gives the hand to the data processing device 1 (step 48). the card returns to step 43 to process the next interpreted instruction.

Thus, it is found that the duration accumulation routine that has been inserted in the execution code of the application includes steps 42 to 45.

The time counting origin can be either the first use of the interpreter, when the card is put into service (it will then be possible to know an absolute duration, in a way the age of wear of the map) ; either the beginning of each new command: then we will have a relative duration (case of Figure 4 where the time variable T is initialized at the beginning of the execution command of the considered application).

In the case where the solution is implemented with the absolute duration, it is easy to know the relative duration by simple subtraction. Indeed, at the beginning of each command, one memorizes in a buffer variable the absolute duration reached, then later, to know the relative duration, it is enough to take the value of the absolute duration at the time of the consultation and to subtract it from the value of the absolute duration previously stored in the buffer variable. Conversely, if we chose an implementation in relative duration, we can know the absolute duration by simple addition. In this case, at the end of each command, the value of the relative duration (T, FIG. 4) must be added to the value contained in a permanent cumulative variable, that is, persistent beyond the current command.

Another slightly finer way of optimizing the size of the TAB-INS-DUREE array is to group together a set of interpretable statements that have near-runtime values, and taking only the largest of the values. . For example, it is possible to take a step of 100 g, and thus to have a table of the type of that of FIG. 5, in which the interpreted instructions of an application are arranged in three groups.

This table reads as follows # the set of interpreted instructions I,, <B> 15, </ B> ..... I; the first line includes any interpreted instruction whose execution time is less than or equal to 100 gs; # the set of interpreted instructions IZ, <B> 16, </ B> ..... I; the second line includes any interpreted instruction whose execution time is between 100 gs and 200 #ts; # the set of interpreted instructions 13, 14,. <B> ...... </ B> 1k of the third line includes any interpreted instruction whose duration of execution is between 200 gs and 300 us, and it is assumed here that 300 gs is the maximum execution time for all the interpreted instructions.

It is noted that the size of this table is reduced compared to that TAB-INS-DUREE of Figure 2, since it includes only (n + 3) elements instead of (n + n) elements. The table in FIG. 5 is used by cumulating the durations of the interpreted instructions (FIG. 4): the value of the duration T; of FIG. 4 will be 100, 200 or 300 Ns depending on the case.

Regarding the storage location of the TAB-INS-DUREE table, this must be entered during the finalization of the base platform (base operating system + interpreter + API functions). This table can be placed in the non-volatile memory masked, such as the ROM, which has the advantage of not wasting user nonvolatile memory, EEPROM type, but has the disadvantage of not being able to evolve if the plate basic form is made to evolve by placing additional code, or corrective, nonvolatile user memory, type EEPROM (see the applicant's US patent application filed under the number 08981607) In this case, we can consider from the start to place the table in user nonvolatile memory, type EEPROM to be able to update it.

An alternative would be to place the initial TAB-INS-DUREE array in hidden nonvolatile memory, such as the ROM, and download later, along with the additional code for the base platform (base operating system + interpreter + functions APIs), an additional table, in user nonvolatile memory, of the EEPROM type, containing the information corresponding to the newly downloaded interpreted instructions, or correcting the duration values of some of the interpreted instructions contained in the initial table, and providing in the duration accumulation routine a gateway such as in the applicant's US patent application filed under the number 08981607, so that this routine analyzes and takes into account first the additional table, then only, if necessary, from the initial table. When the array is analyzed as described above, ie accessed by the duration accumulation routine at each iteration in the code interpreter process, this method of analysis can be named as a map method . In contrast, we can use a method called off-map method. This consists of having the table TAB-INSIDE, outside the card. For example, it is integrated into the so-called verifier tool that analyzes the integrity and authenticity of the code of the application in interpreted language to be downloaded into the card. Thus, in this verifier tool, by traversing the code and performing a duration accumulation operation using the table TAB-INS-DUREE, it is possible to modify the code of the application by inserting in it the call of the routine making it possible to transmit the waiting state word. This is illustrated in FIG. 6. In step 60, a time variable T is initialized to 0, and in step 61 the time variable T is increased by the value T; corresponding to the duration of the interpretable instruction that will be checked now, a value that is read in the TAB-INS-DUREE table. In step 62, the value of the time variable T is compared with the duration TmaX. If the time variable T is not less than the duration Tmax, it means that the future execution, by the card, of the current interpretable instruction i will lead to an exceeding of the duration Tmax: there is therefore to insert, in the code of the application, in step 63, a standby instruction for the card, to send a wait status word to the reader. Then, the verifier resets the time variable T to 0 (by returning to step 60). Following step 62 in the case where the time variable T is less than the duration Tmax, the verifier of the card verifies the interpretable instruction I; (step 64). The verifier then determines whether the interpretable instruction being processed is the last to be verified. If yes, the treatment is finished. If not, the verifier returns to step 61 to process the next interpretable instruction.

Following this operation, the code of the application is in the following form, in which one or possibly more waiting instructions are present: I,, 1z, .... I; ,.....,the H. This code will then be able to be downloaded into the map for its execution. During this execution, each time the card encounters a waiting instruction la, it will send the reader a waiting state word.

In the foregoing, the invention has been described in the context of a portable object containing a virtual machine and manipulating interpretable instructions. The invention also applies to a portable object devoid of such a virtual machine; it also applies to any other data processing device having to carry out, within a certain time, a certain operation, this operation possibly consisting in providing a response to another device with which it cooperates, or in performing an internal processing .

Claims (10)

A method for counting the time in an information processing device comprising a processor (9) and a memory (10,14), characterized in that it comprises the steps of -defining, in the memory, a table containing, for each instruction of a set of instructions to be executed by the processor, a execution time of this instruction; executing (46), by means of the processor, a program contained in the memory and comprising at least one instruction by adding (43), at the time of execution of each instruction, the execution time of this instruction to a value cumulative time. The method of claim 1, wherein the instructions are interpretable instructions written in advanced language and the program execution step includes a step of interpreting these interpretable instructions to translate them into elementary instructions written in a language specific to the processor (9) and executed by the processor. The method of claim 1, including the steps of: comparing (44) by the processor, when executing each instruction, the time accumulating value to a time reference value; triggering an operation (45) to be performed by the processor when the accumulated time value reaches the time reference value. The method according to claim 3, wherein the information processing device (8) cooperates with another information processing device (1) and the time reference value corresponds to a time in which the processing device The information processor must transmit a message to the other information processing device and, when the time accumulation value reaches the time reference value, the processor transmits (45) said message to said other information processing device. The method according to claim 1, which comprises the steps of: distributing, in the memory, said set of instructions to be executed by the processor into several groups of instructions, the instructions of each group having neighboring execution times one another ; -define, in the memory, and for each group of instructions, an average execution time, unique for all the instructions of this group of instructions. A method for counting time in an information processing device comprising a processor (9) and a memory (10,14), characterized in that it comprises the steps of, in an instruction checker tool, -define an array containing, for each instruction of a program to be executed by said processor, a execution time of this instruction; -checking (64) each instruction of the program by determining whether this instruction obeys at least one determined rule by adding (61), at the time of checking each instruction, the execution time of this instruction to a cumulative value of time; comparing (62), at the time of the verification of each instruction, the cumulative time value with a time reference value; inserting (63) in the program, at a location where the instruction being checked is present, an instruction defining an operation to be performed by the processor, when the cumulative time value reaches the time reference value; and in that it comprises the step of executing the program by the processor of the information processing device. The method of claim 6, wherein the instructions are interpretable instructions written in an advanced language and the program execution step includes a step of interpreting these interpretable instructions to translate them into elementary instructions written in a language specific to the processor and executed by the processor. The method according to claim 6, which comprises the steps of: distributing, in the memory, said set of instructions to be executed by the processor into several groups of instructions, the instructions of each group having neighboring execution times one another ; -define, in the memory and for each group of instructions, an average execution time, unique for all the instructions of this group of instructions. 9. An information processing device comprising a processor (9) and a memory (10,14), characterized in that it comprises, in the memory-means for defining, for each instruction of a set of instructions to execute by the processor, a execution time of this instruction; time calculating means for adding (43), during execution, by the processor, a program comprising at least one instruction and at the time of execution of each instruction, the execution time of this instruction to a cumulative time value. 10. Device according to claim 9, which comprises, in the memory of the comparison means for comparing (44), during the execution of each instruction, the cumulative time value at a time reference value; trigger means for triggering an operation to be performed by the processor when the cumulative time value reaches the time reference value.