FR2789193A1 - Method for modifying behavior of computer under execution of functions in binary code by replacing first branching instruction by second branching instruction at first determined address - Google Patents

Abstract

A binary code contained in the first zone memory is examined to find some addresses (A2) to find a first branching instruction on first determined function with protection of addresses (A2) in a structure of data situated at a second determined address (A8). The first branching instruction is then replaced by a second branching instruction at the first determined address (A1), while writing at the addresses (A2) the second instruction of branching. An Independent claim is included for: (a) a computer

Description

Method for modifying the behavior of a computer machine.

  The field of application to which the invention relates is that of the behavioral modifications of a computer machine during execution, that is to say without the need to stop and restart the

  machine with a new configuration.

  It is interesting to be able to modify the behavior of a computer machine in operation to ensure the maintenance of systems that cannot be stopped. In the debugging phase, you may want to correct executable code errors. You may want to get a record of some special events occurring during the operation of the machine. Other needs to modify the behavior of the machine

  exist, for example to improve performance.

  The behavior of the machine results from the execution of certain functions which concern the heart of the machine, these are for example the functions of

  control of the hardware elements and the functions of the operating system.

  To make a modification in such a function, the simplest solution consists in restarting the machine by loading a new executable code of this function. The executable code of a function is binary code directly interpretable by the processor or processors of the machine. It is often obtained by compiling a source code developed in advanced language,

  closer to human understanding.

  To avoid having to recompile the code of a function and restart the machine, we can provide that the function can be configured. Certain parameters of the function can be modified by a program or by an operator interface so that the function influences the behavior of

  the machine, differently depending on the value of the parameters.

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  However, this requires knowing in advance the desired behavior modifications of the machine. This solution does not provide satisfactory flexibility for unforeseen modifications such as

  software or hardware error corrections, performance changes.

  To overcome the aforementioned drawbacks, the object of the invention is a method for modifying the behavior of a computer machine during the execution of functions in binary code contained in a first memory area of said machine, by at least one processor of said machine. The method is characterized in that it comprises: a first step consisting in storing in a second memory area of said machine, a first specific sequence of binary code starting at a first determined address in said first memory area. This first specific sequence of binary code is the one whose execution will modify the behavior of the machine; a second step consisting in browsing the binary code contained in the first memory area until finding all the addresses at which appears a first instruction to connect to a first determined function and in saving the addresses thus found in a data structure located at a second determined address. This first function is that whose execution of the binary code corresponds to the original behavior of the machine; a third step succeeding the two preceding steps, consisting in writing to each address saved in the data structure, a

  second instruction to connect to said first determined address.

  This makes it possible to insert into the binary code, without any other alteration of its structure, a sequence of binary code whose execution modifies the behavior of the machine. Indeed, the behavior of the machine no longer results from the execution of the first function as activated in the

  binary code previously executed.

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  A branch instruction is binary coded on a finite number of bits which constitute a word. To avoid doing a job comparable to that of a compiler, an advantage of the invention is to have to replace in the sequence of the initial binary code, only the single word of the first branching instruction mentioned above. The word of the second connection instruction previously mentioned should then contain the indication of the type of instruction to be carried out by the processor and the address on which to carry out the connection. This address is therefore necessarily coded on a restricted number of bits. This requires that the specific sequence of binary code be in a second memory area - whose address can

  be coded on a limited number of bits.

  When, to modify the behavior of the machine, it is impossible to control the location of the added binary code from the point of view of its address, a second, more powerful type of connection should be used, consisting of filling in a count register with the desired address, then connect to the address contained in this register. An improvement of the method according to the invention is then characterized in that the method comprises: - A first step consisting in storing in a second memory area of the machine, a first specific sequence of binary code starting at a first determined address of the first memory area. This first specific sequence of binary code is that which makes it possible to make a connection to any address function, by using the counting register. This type of branching is more elaborate than simply replacing a word in the initial binary code; a second step consisting in browsing the binary code contained in the first memory area until finding all the addresses at which appears a first instruction to connect to a first determined function and in saving the addresses thus found in a data structure located at a second determined address. This first function

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  is the one whose execution of the binary code corresponds to the behavior

original machine.

  a third step consisting in replacing the first connection instruction by a second instruction for connection to the first determined address, by writing to the address where the first is located

  branching instruction, said second branching instruction.

  a fourth step preceding the third step, consisting in storing in a third memory area of said machine, a second sequence of binary code performing a second determined function, at a third determined address, and in that said first specific code sequence binary contains at least one instruction to connect to said third determined address. Said second determined function is that of which

  the execution of the binary code will modify the original behavior of the machine.

  According to an additional characteristic of the method which is the subject of the invention, the first specific sequence of binary code contains: - one or more instructions for saving the content of a link register and a counting register of the processor on which the first specific sequence is executed, at a fourth determined address in the second memory area; - an instruction to load the third address determined in the counting register; - a connection instruction using the counting register; - one or more instructions for loading the content saved by means of the fourth determined address into the link register and into the counting register;

  - a return instruction based on the content of the link register.

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  Other advantages and details of embodiment of the invention will emerge from the

  description of a particular implementation with reference to the figures.

  - Figure 1 shows an example of a machine comprising at least one processor. - Figure 2 shows a binary code state before implementation of the

method according to the invention.

  - Figure 3 shows steps of the method according to the invention.

  - Figure 4 shows a binary code state after implementation of the

io process according to the invention.

  With reference to FIG. 1, a computer machine comprises at least one processor 1, 2, 3, 4, connected to a memory unit 5 by means of a system bus 6. Each processor 1, 2, 3, 4 is a central unit of known type (CPU for Central Processing Unit in English). A processor CPU includes several registers which allow it to process the content of memory unit 5. Without going into the details of the complex operation of the

  processor CPU, one retains on figure 1, registers IAR, LR, CTR.

  The IAR (Instruction Address Register in English), is intended to contain an instruction address resident in the memory unit 5, being executed by the processor CPU. Functions executable by the computer machine, consist of sequences of instructions in binary code, each resident at an address in the memory unit 5. Reading an instruction in binary code by means of the IAR register allows its direct interpretation by the processor that processes it. An instruction is coded by a set of bits which constitute a word. The word includes among other things, a field for coding the type of instruction and one or more fields for accessing one or more operands of the instruction. Some examples of instruction type are load, store, add, plug in, etc. Depending on the type of instruction, a field to access an operand contains the value of

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  the operand, the absolute address or the relative address of the operand in memory, the number of a register containing the value of the operand or containing

  the address of the operand in memory.

  The LR Register (Link Register in English) can be used by certain connection instructions to establish a link to the return connection

  performed by the instruction using the LR register.

  The CTR register (CounT Register in English) can be used by certain connection instructions to contain an address of

memory connection.

  The use of the registers IAR, LR and CTR will be better understood with reference to the example in FIG. 2. A first memory area 7 of the memory unit 5 contains binary code of functions executable by the machine. This binary code contains for example a series of any instructions Instr.10,

  Instr.11, Instr.12 located at successive addresses in memory area 7.

  When the IAR register, for example of processor 1, contains the address of the instruction Instr.10, the processor executes this instruction. Then, the IAR register is physically incremented by the processor 1 to contain the address of the instruction Instr. 11 he executes and so on for the next instruction

Instr. 12.

  In the example of FIG. 2, at a address A2 following the address of the instruction Instr.12, there is a particular instruction blAim, then at the following addresses, any other instructions whatever Instr.14, Instr.15, etc. The binary word which codes the instruction blAim contains as type, that of a branching bl, and as operand value, a relative address Aim (for immediate address). When the IAR register, for example of the processor 1, contains the address A2 as the current address, the decoding of the type bl by the processor 1, essentially causes two actions of the hardware circuits of the

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  processor 1. A first action consists in adding the operand value Aim to the current address A2 to obtain an absolute address which is stored in the register IAR. A second action consists in putting in the register LR,

  the following address of address A2 where the instruction Instr. 14 is located.

  The first action has the effect of breaking the sequential execution of the instructions at successive addresses in the memory area 7. In fact, the instruction which is executed following that located at the address A2 is not the instruction Instr. 14 but an instruction Instr. 20 located at address A3. At the following addresses of address A3, instructions Instr.21, Instr.22, Instr.23, Instr.24 constitute with instruction Instr.20 the binary code of a first

  machine-executable function.

  The second action has the effect of re-establishing the sequential execution of the instructions Instr.14, Instr.15 upon return of the function coded by the instructions Instr.20 to Instr.24. For this, the last instruction Instr.24 of the first function is followed by a instruction blr. The decoding of the instruction blr by the processor causes the transfer of the content of the register LR to the register IAR. The instructions Instr.10 to Instr.15 are part of the binary code of another function which calls the first function. Generally the first function and the other function are first written in an advanced language more understandable by a human being than binary code. Writing advanced language functions in a program is what is usually called source code. A compiler is then responsible for translating the source code into binary code. Preferably using relative addressing, the compiler generates a binary code of functions whose location in memory is optimized. The relative addressing which makes it possible to code in a single word the type of instruction and the address of connection of the execution, is well

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  suitable for functions including addresses of instruction series

  connected are close in memory to the connection instructions.

  The memory area 7 being reserved for the execution of the operating system, the sequences of instructions which reside there are those of functions which govern the behavior of the machine. The memory area 7 is part of a Kernel address space (Kernel in English) of the memory unit 5, not directly accessible by the applications processed by the machine. A method for modifying the behavior of the machine is described with reference to the figure

o 3 and in figure 4.

  With reference to FIG. 4, a distinction is made in the Kernel address space: - the first memory area 7 which contains code and data loaded during booting of the operating system (boot in English) when booting up the machine; a second memory area 8, close in terms of addresses of the memory area 7, for containing code and data loaded during or after the booting of the operating system; a third memory area 9 for containing code and data accessible to certain applications. The memory area 9 constitutes a shared address space, generally more distant in terms of addresses from the

  memory area 7 than memory area 8.

  With reference to FIG. 3, the notion of first, second or fourth step does not translate an order of sequentiality but simply an order of

  description or interest. The representation of steps El, E2, E4 on

  parallel branches, indicates that the sequence of these steps is unimportant. When a sequence order of steps El, E3, is

important, this is clarified.

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  With reference to FIGS. 3 and 4, in a first step E1, several addresses A1, A5, A6, A7, are reserved in the memory area 8. A specific sequence of instructions Instr.30, ..., Instr.36, bir is written in binary code, to successive addresses in memory area 8, the start address of which is address A1 o the instruction Instr.30 is written. In a second step E2, a first function is determined to be that from which calls are diverted so as to modify the behavior of the machine in comparison with that initially planned when this io first function is normally called. The address A3 at which the first instruction Instr.20 of the binary code of the first function resides is stored. An operating system generally includes a table, not shown here, which lists the functions, indicating for each the address of residence of its first instruction. This table is for example used by a compiler to transcribe in binary code a source code which calls upon functions which are listed there. A reading of this table

  provides the address A3 when the function is determined by its name.

  The binary code contained in the memory area 7 is scanned so that each time a branching instruction is detected on the first function, the value of the address A2 at which this branching instruction is detected is saved in a structure data residing at a specified address A8. To detect the instruction to connect to the first function, each time a bl_Aim instruction to connect to a relative address Aim is recognized, the relative address value Aim is added to the current address value for which the instruction bl_Aim has been recognized. If the result is equal to the address value A3, this indicates a connection to the first function. The current address then constitutes an address of type A2. Each time a blAim instruction for connection to the first function is detected, by memorizing the instruction bl Aim next to the address value A2 in the data structure residing at

  address A8, it is possible to make the process reversible.

  1o 2789193 A third step E3 follows steps E1 and E2. In step E3, an instruction blaA1 is written to each address A2 whose value is stored in the data structure residing at address A8. Each first instruction bl_Aim detected for connection to the first function is thus replaced by the second instruction bla_A1. In the example presented where the second instruction is an instruction for absolute connection to the address A1, it is not necessary to make a calculation linked to the location of the address A2 where the replacement is carried out. This accelerates the operations of

  io replacement of each first instruction by the second instruction.

  When the processors 1, 2, 3, 4 are equipped with cache memories, a step E5 can follow the step E3. In step E5, the modified cache lines are purged so as to ensure that the modifications are taken into account

by processors.

  The specific sequence stored in the memory area 8 by step E1, begins with an operation of saving the contents of registers of the processor CPU, and ends with an operation of restoring in these registers, the contents saved. The return operation itself ends with

an instruction of type blr.

  The backup operation includes instructions Instr.30, Instr.31.

  The instruction Instr.30 triggers a writing of the content of the register LR to the address A5. The instruction Instr.31 triggers a writing of the content of the register CTR at the address A6. The return operation includes instructions Instr.35, Instr.36. The instruction Instr.35 triggers a writing of the value contained at address A5 in the register LR. The instruction Instr.36 triggers a writing of the value contained at address A6 in the register

CTR.

  il 2789193 Between the backup operation and the restore operation, a sequence of instructions Instr.33, ... constitutes a sequence of instructions intended to modify the behavior of the machine by replacing the sequence

  Instructions Instr. 20, ..., Instr. 24.

  It is interesting to note that the specific sequence of instructions starting at address A1 is a priori independent of address A3, that is to say of the choice of the first function. For a user who does not have direct access rights to memory areas 7 and 8, it is possible to implement the behavior modification method when the machine comprises a sequence of the type of the specific sequence of binary code previously.

  described and a user interface 13.

  The user interface 13 comprises an input 14 provided for receiving a function name and an input 16 provided for receiving an activation / deactivation order. To allow a choice between several specific sequences, the interface may further comprise an entry 15 intended to receive a specific sequence name. The function name to be routed, received at input 14, is used to execute step E2. The specific sequence name, received at input 15, is used to execute step El. When it receives at inputs 14, 16, a function name and an activation order, the interface triggers steps El, E2 of the behavior modification process. The interface 13 has control means which, for example validate entry 16 provided that a name is presented at entry 14, or for example use a sequence name

  specific by default if no name is presented as input 15.

  A step E6 can follow the step E3 or E5, when desired. Step E6 performs the reverse operation of step E3. The data structure residing at address A8 is traversed. For each address value A2 read, the instruction bl_Aim stored next to this address value A2, is written to the address A2 of the memory area 7. This makes it possible to make the method for modifying

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  reversible behavior. Indeed, the rewriting of all the original bl_Aim connection instructions on the first function, gives back to the machine

its initial behavior.

  It is possible to trigger step E6 after step E3 or step E5 by means of the operator interface 13, by presenting, at input 16, a deactivation order. When the processors 1, 2, 3, 4 are equipped with cache memories, a step E7 o can follow the step E6. In step E7, the modified cache lines are purged so as to ensure that the modifications are taken into account

by processors.

  A step E4 improves the process in the following way. Step E4 is activated before step E3. In step E4, a sequence of instructions Instr.40, ..., Instr.46, blr, is copied to successive addresses of a memory area 9, starting at an address A4. When step E4 is activated, the specific sequence of instructions loaded into memory area 8 by step E1 is a specific specific sequence comprising saving the contents of the registers LR and CTR, loading the address A4 into the register counting of the processor, the instruction bctrl_A4 of connection to the address contained in the counting register, then the restitution, in the registers

  LR and CTR, saved content. The instruction sequence Instr.40,

  .... DTD: Instr.46, blr, constitutes the binary code of a substitution function, ie of a second function which one wishes to execute in place of the first function. This does not prevent the second function from calling the first

  function if the execution of the first function is necessary.

  The copy in zone 9 of the binary code of the second function has several advantages. The binary code of the second function can reside in any pages 11, 12 of the memory 5. It is from these pages that

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  the copy is made. Thus, for example, pages 11, 12 can be at addresses far from memory areas 7 to 9. For example again, it is possible to write the second function in an advanced language to constitute a source code. Tedious programming of binary code or assembly code is avoided. Then, it is possible to compile the source code of the second function to obtain the binary code of the second function, using a compiler. The compiler stores the binary code in the memory location that suits it. The binary code generated by the

  compiler overlaps two pages 11 and 12.

  If desired, it is possible to program the second function in advanced language, so as to call on the first function. The compiler is responsible for generating Instr.42, ..., Instr.44 instructions to binary code this call. The compiler is responsible for example of generating a l5 instruction bctrlA3 on the address A3 of the first function as seen in FIG. 4. This is advantageous when the first function remains necessary for the

machine operation.

  If the instruction sequences residing in memory area 7 are executed in virtual addressing mode, the diversion of the first function benefits from this addressing mode. However, it is possible that the sequences of instructions residing in memory area 7 are executed in physical addressing mode. Preferably, the address A4 is a physical beginning of page address 10 residing in memory area 9. By ensuring that the binary code of the second function fits on a physical page, the copying in memory area 9 makes the code hold binary of the second function on the single page 10. The problems of page connectivity which may arise in physical addressing mode are solved because the successiveness of the addresses in the absence of connection is preserved. If the binary code does not fit on a single physical page, the copy should be made on physical pages

one after the other.

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  It is possible to activate step E4 by means of the interface 13 by presenting on an input 17 of the interface 13, a name of substitution function whose code resides in the memory 5 of the machine. The interface 13 includes means for verifying that the name presented on the input 14 is that of the sequence

specific specific.

  In the case where step E4 is activated, step E1 loads into the memory area 8, the specific specific sequence which contains an instruction bctrlA4 to make a connection to the address A4. The bctrl instruction has the effect of loading into the IAR register of a processor which is executing it, the content of the CTR register of this processor and into the LR register of this processor, the value of the address which follows that at which resides the instruction bctrl. The advantage of using the bctrl instruction is that of being able to connect to

  any address whose value is contained in the CTRL register.

  The bctrl instruction of the specific sequence of instructions is then preceded by an Instruction 33 instruction whose effect is to store in the CTRL register, the

address value A4.

  After implementation of the method, the machine operates as explained with reference to FIG. 4. Suppose for example that the processor 2 executes the instructions Instr.10 to Instr.15 resident in the memory area 7. When the IAR register of the processor 2 contains address A2, processor 2 decodes the instruction bla_A1. By decoding the instruction bla _A1, the processor 2 stores in its register LR, the address according to the address A2 and stores in its register IAR the address A1 in absolute value. In the following cycles, the processor 2 then decodes the series of backup instructions Instr.30, Instr.31 which begins at address A1 in the memory area 8. By decoding the series of instructions Instr.30, Instr.31, processor 2 writes the value contained in its register LR and the value contained in its register CTR, at addresses A5, A6. Then, processor 2 decodes the series of insertion instructions which begins to

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  instruction Instr. 32. Next, the processor 2 decodes the series of restitution instructions Instr.35, Instr.36 which stores the values written at the addresses A5, A6, in the registers LR and CTR. Thus, the registers LR and CTR of processor 2, again contain the values which they contained immediately after the register IAR contains the address A2. In particular, the register LR contains the address of the instruction Instr.14 which follows the address blaA1 in the memory area 7. Following the last instruction Instr.36 of the series of restitution instructions, the processor 2 decodes the instruction blr. By decoding the instruction blr, the processor 2 stores in its register IAR, the content of its register LR. Thus, in the following cycles, the processor 2 executes the instructions Instr.14, lnstr.15 residing in the memory area 7. The saving before, then the restitution after execution of the series of insertion instructions allows the series of insertion instructions to modify the content of the registers LR and CTR if necessary, and allows to return to any instruction Instr.14 which follows any instruction blaA1 because the code of instructions Instr.30 to

  Instr. 36 is independent of address A2.

  The series of insertion instructions mentioned above may contain simple instructions which it is desired to insert between the instructions Instr.12 and Instr.14 in the memory area 7. According to the implementation of the invention presented in FIG. 4, when the processor 2 decodes the series of instructions Instr.32, Instr.33, the processor 2 loads the value residing at the address A7 and stores it in its register CTR. Since the value residing at address A7 is the address A4 of the instruction Instr.40, the register CTR then contains the address A4. Next, the processor 2 executes the instruction bctrl which precedes the instruction Instr. 35. By executing the instruction bctrl, the processor 2 stores in its register LR, the address where the instruction Instr. 35 resides and stores in its register

  IAR, the content of the CTR register, i.e. the address A4.

  When the IAR register of the processor 2 contains the address A4, the processor 2 decodes the instruction Instr.40 residing in the memory area 9, then, by

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  successive increments of the IAR register, the continuation of the instructions Instr.41 to Instr.46 until arriving at the bir instruction which follows the instruction Instr.46. By decoding the instruction bir, the processor 2 stores the content of its register LR in its register IAR, that is to say the address of the instruction Instr. 35. The processor 2 thus links the following instructions Instr.35, Instr.36 residing in the memory area 8 then the instructions Instr.14, Instr.15 residing

in memory area 7.

  The foregoing explanations for processor 2 remain valid for any processor 1, 3, 4 of the machine. It is interesting to note that the replacement of the first instruction bl_Aim by the second instruction bla_A1 does not create any disturbance in the operation of the machine, even if a processor executes one of the instructions Instr.12 to Instr.14 during the replacement . Indeed: - if the processor executes the instruction Instr.14, the behavior of the machine previously provoked by the connection to address A2 on the first function has simply not been modified by the replacement, it will be so on the following connection; - if the processor executes the instruction Instr.12, the processor then executes the instruction residing at address A2 which is the instruction blaA1 to subsequently execute the instruction Instr.14 because its register LR contains the following address of address A2 at the time of connection, which then modifies the behavior of the machine; - if the processor executes the instruction residing at address A2, whatever the

  type of connection, the LR register contains the address of the instruction Instr.14.

  If the connection is effective at address A3, the sequence of instructions starting at address A1 is not executed and the return to instruction Instr.14 is ensured by execution of the instruction blr which follows the instruction Instr. 24. If the connection is effective at address A1, the sequence of instructions starting at address A1 is executed and the return to instruction Instruction 14 is ensured by

  execution of the instruction blr which follows the instruction Instr. 36.

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  Note in the instruction sequence Instr.40, ..., Instr.46, bir, residing in memory area 9 that:

  - in the absence of a bctrl_A3 instruction, the instruction sequence Instr.40,

  .... DTD: Instr.46, bir, simply replaces the sequence of instructions Instr.20, ..., Instr.24, blr; - in the presence of an instruction bctrl_A3 at the end of the instruction sequence Instr.40, ..., Instr.46, a sequence of the instruction sequence Instr.40, Instr. 46, is inserted before the sequence of instructions Instr. 20, ..., Instr. 24, bir; - in the presence of an instruction bctrl_A3 at the start of the instruction sequence Instr.40, ..., Instr.46, a sequence of the sequence of instructions Instr.40, lnstr.46, is inserted after the sequence instructions Instr.20, ..., lnstr.24, bir;

  - in the presence of a bctrl_A3 instruction among the Instr.40 instructions,

  .... DTD: Instr.46, a sequence of instructions Instr.40, ..., Instr.46,

  is inserted before and after the sequence of instructions Instr.20, ..., Instr.24, bir.

  Thus, the method according to the invention makes it possible to insert the sequence of any number of instructions Instr.40, ..., Instr.46, before and or after, or instead

  the sequence of any sequence of instructions Instr.20, ....

  Instr. 24, without having to change the addresses of the instructions that reside in

  memory area 7. In addition, the sequence of instructions Instr.40, ....

  Instr. 46, can result from a function developed by standard software means without having to worry about the fact that the instructions residing in

  memory 7 are executed in virtual or physical addressing mode.

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Claims (7)

  1. Method for modifying the behavior of a computer machine during the execution of functions in binary code contained in a first memory area (7) of said machine, by at least one processor (1, 2) of said machine, characterized in that it comprises: - a first step (El) consisting in storing in a second memory area (8) of said machine, a first specific sequence of binary code (Instr. 30, ..., Instr. 36, bir ) starting at a first determined address io (A1) of said second memory area (8); a second step (E2) consisting in browsing the binary code contained in the first memory area (7) to find addresses (A2) to which a first connection instruction (blAim) appears on a first determined function and to save the addresses ( A2) thus found in a data structure located at a second determined address (A8); a third step (E3) succeeding the two preceding steps (E1) and (E2), consisting in replacing the first connection instruction (blAim) with a second connection instruction (bla A1) on said first determined address (A1), by writing to the addresses (A2) said second connection instruction.   2. Method according to claim 1, characterized in that it comprises: a fourth step (E4) preceding the third step (E3), consisting in storing in a third memory area (9) of said machine, a second sequence of code binary (Instr.40, ..., Instr.46, blr) performing a second determined function, at a third determined address (A4); and in that the first specific binary code sequence contains at least one branch instruction (bctrlA4) on said second determined function. 19 2789193   3. Method according to claim 2, characterized in that the first specific sequence of binary code contains: - one or more instructions for saving the content of a link register (LR) and a counting register (CTR) of the processor on which the first specific sequence is executed, by means of a fourth determined address (A5); - an instruction to load the third determined address (A4) into the counting register (CTR); - a connection instruction using the counting register (CTR); - one or more instructions to load in the link register (LR) and in the counting register (CTR) the content saved by means of the fourth determined address (A5);   - a return instruction based on the content of the link register (LR).   I, 4. Method according to claim 2, characterized in that the second sequence of binary code is contained in a single physical page of the   machine, or failing that, in contiguous physical pages of the machine.   5. Method according to claim 2, characterized in that the second binary code sequence contains an instruction (bctrlA3) whose execution has the effect of connecting to the address of the first instruction (Instr.20) of   binary code of the first function.   6. Computer machine whose behavior results from the execution of binary code of functions, said binary code residing in a first memory area (7) of a memory unit (5), characterized in that it comprises outside the first memory area (7): - a specific sequence of binary code (Instr.30, ..., Instr.36, blr) whose execution modifies the behavior of the machine; - an operator interface (13) comprising an input (14) for receiving a first function name whose binary code resides in the first zone 2789193   memory (7), provided for storing in a second memory area (8) said specific sequence of binary code from a first determined address (A1) and for replacing in the first memory area (7), each instruction for connection to said first function by an instruction to connect to said first address (A1). 7. Computer machine according to claim 5, characterized in that it comprises, outside the first memory area (7), a second sequence of binary code performing a second determined function, in that the operator interface (13) comprises an input (17) for receiving a second function name, provided for storing a second sequence of binary code performing the second function in a third memory area (9), and in that said specific sequence of binary code comprises an instruction for   connection to the second binary code sequence in the memory area (9).