FR2782424A1 - Error correction coding procedure for data transmission includes combined transmission of source and processed data following several stages of processing - Google Patents

Abstract

The system provides coding which may be readily fitted into VSLI circuits. The procedure for error correction coding uses a data source series associated with a coded data block to be transmitted to at least one receiver. The procedure includes at least two coding stages (21i), each comprising at least two basic coding modules (22i,j). Each of the coding stages receives a series of data to be processed which is distributed between the basic coding modules, and delivers a series of processed data. There is also at least one branching stage (23i) inserted between two successive coding stages, distributing the processed data derived from each basic coding module of the first coding stage between at least two basic coding modules of the second stage. The resulting coded data block for transmission comprises at least a quantity of the source data, and a quantity of the processed data emerging from the last coding stage.

Description

Method and device for error correction coding and

  method and corresponding decoding device.

  The field of the invention is that of coding digital data.

  More specifically, the invention relates to error correcting codes.

  The invention applies particularly, but not exclusively, to source data encodings organized in data blocks, independent of each other, and therefore to be coded, and decoded, individually, as well as to the coding of data streams.

data (convolutional encodings).

  Numerous coding techniques allowing the correction of errors of

  transmission are already known. In particular, reference can be made to F.J.

  McWilliams and N.J.A. Sloane [1], SBWicker [2], and V.Pless et al [3] (all references cited in this application have been grouped together for ease of reading in an appendix. transmission errors inherent in any communication channel, so they are widely used in telecommunications, broadcasting and storage

  information, for example in laser disks and magnetic disks ...

  These errors are caused, for example, by the thermal noise of the electronic components of the receiver, electromagnetic interference (intentional or not), echoes or multiple propagations in the case of radio propagation (for example in the context of radiotelephone systems such as GSM, digital broadcasting such as DAB or digital television such as DVB) or in an electrical energy network (for example to

  telecommunications on the electricity grid) ...

  The first studies of error-correcting codes date back to the 1940s. In his 1948 papers, Claude Shannon [4] founded the information theory that is still being designed (and forever?)

  digital communications systems.

  One of the results of Shannon is his theorem concerning the limit of the capacity of a communication channel whose famous formula is: C = BLog (l +) o the capacity C of the channel is a flow of information expressed in bit / s, B the bandwidth of the channel in Hz, and S / N the ratio of the power of the signal and the

noise in the bandwidth.

  This theorem can be stated in the following way: "Any channel is associated with a transmission capacity C (in bit / s) .There are error correcting codes such that the information can be transmitted through a channel to a channel. rate less than its capacity C with an arbitrarily small bit error rate by taking a code

  error corrector of sufficiently large length ".

  Shannon's theorem is unfortunately only a proof of existence. Its publication kicked off the search for "good" codes that has been going on for 50 years now. The main codes that caught the attention of the telecommunications community were first the bulk codes for transmitting bit packets: the Hamming codes, the codes of

  Golay, Reed-Muller codes, BCH codes, ReedSolomon codes, ...

  The principle of bulk error correcting codes was invented by R. W.

  Hamnming in 1950: from k bits of useful information, one computes (nk) redundancy bits by means of modulo 2 additions of the k information bits. the total length of each block, also called codeword, is therefore n bits. On reception, if errors are present in the word of n received bits, the presence of (n-k) redundancy bits beside the k bits of useful information will make it possible to correct

some of the errors present.

  If the ratio of the signal / noise powers is greater than a certain value, then the cost of the information rate occupied by the coding redundancy bits is more than compensated by the reduction, or even the virtual cancellation, of the bit error rate. (TEB) after decoding. This gain in performance is called coding gain, for a fixed BER, and is given in decibels (dB). A coding gain of 3dB means that the power of the signal transmitted with coding can be divided by 2

  to obtain the same BER as without coding (3 dB - 10.Log10 (2)).

  Another larger family of encodings, more recent, is that of the convolutional codes introduced by P. Elias [5] in 1955. These encodings transform an infinite series of information symbols into several other infinite sequences of information symbols. These codes have been invented to transmit continuous flows of information. A.J.Viterbi [6] (in 1967) and G.D.Forney [7] (in 1973) demonstrated the possibilities of decoding "small" convolutional codes efficiently with the so-called Viterbi algorithm (an algorithm derived from the theory of

  dynamic programming of Cf; Bellmann [8] (1957).

  Bulk error codes and convolutional codes can be

  be treated with the same theoretical tools and the same methods of decoding.

  Block codes and convolutional codes can be represented by rather special graphs called "lattices" from which we can calculate their

  weight distributions and decoding according to the Viterbi algorithm (cf.

Fomey [7] and McEliece [9]).

  Each code word is represented by a different path in the trellis and decoding according to the Viterbi algorithm makes it possible to find the best path that is to say the code word closest to the received word. But, for a block code as for a convolutional code, the decoding complexity "explodes" exponentially in 2 (n-k) for a block code, and in 2v for a convolutional code (v is the size of the convolutional encoder memory). The dilemma is that the longer and more powerful a code is, the more errors it corrects, but the more expensive or time consuming it is.

in hardware to decode.

  Recently, in 1993, C. Berrou and A. Glavieux [10] presented a new coding scheme commonly called "turbo-code". We can underline four ideas present in turbo-codes: 1) Use a recursive convolutional coding, that is to say having an infinite impulse response (and not an answer)

  impulse finished as classically).

  2) Code once the useful information bits in their initial order, then code a second time these same useful data but in a different order, that is to say permuted. One emits only one

  times the useful bits, and the encoders only emit their redundancies.

  The permutation, also called interlacing, is "magic", because the bigger the size, the more the code can correct errors. Indeed, the interleaving makes it possible to decorrelate the errors due to the channel

of transmission.

  3) Use Soft Decoding (soft-decoding) techniques introduced by Bahl et al. (BCJR algorithm) [11], G.Battail [12], or Hagenauer (SOVA algoritm ("Soft-Output

Viterbi Algorithm ")) [13] ...

  4) Set by definition that the output Ai (of each soft decision decoder i, receiving "information" A. () at iteration i) is the sum of the initial "information" A0 received and

  extracted or extrinsic information Wi such that: Ai = A0O + Wi.

  At the next iteration (i + 1), only a part of the extrinsic information such as: A + l (0) = A0 + ai + lWi is reinjected, with the coefficients oi varying from 0 to the first iteration and up to 1.0 for the last one. These coefficients (xi) are optimized to minimize the BER from a certain signal-to-noise ratio and, strictly speaking, the quantities A are logarithms of

  likelihood and not amounts of information.

  The first turbo-codes of Berrou and Glavieux were convolutional codes based on a large permutation matrix (256 x 256 = 65536) giving performances near the Shannon limit, for low signal-to-noise ratios. But some of the newer telecommunication and broadcast systems require the transmission of small packets of information (eg, back-air broadcast, mobile phone, wireless ATM, Internet, etc.). In addition, the disadvantage of a large permutation is an incompressible processing delay which can be very troublesome, in a real-time service, such as for example in a telephone conversation. This is why research has been conducted to find good "turbo codes" en bloc. In particular, R. Pyndiah et al. [14] adapted the concept of iterative decoding to Elias product codes [5] for small block codes (n <1024). And recently, in 1997, Berrou et al. [17] adapted their turbo-codes (by closing the lattices) to the construction of efficient block codes of this size order (n <2048),

  called FOTC (in English: "Frame Oriented Turbo Codes").

  The bulk codes presented by Berrou and Pyndiah are among the best known codes in their size and yield categories (0.5 <r <1) and this for a decoding complexity allowing a material realization of an excellent

quality / price ratio.

  For a given block length n and for a correction capacity: t = L (d - 1) / 2] given (d is the minimum Hamming distance between two words in the code), there are upper bounds (more or less severe) performance that can be expected. The best known upper bound is McEliece et al. [1,2], shown (11) in solid lines in Figure 1. We made

  also appear, in dotted lines, Gilbert-Varshamov marker 12.

  For a fixed relative distance d / n, one can not find a code having a yield k / n higher than the limit of McEliece. Moreover, we say that a family of code is good if: lim (d / n): 0 n -.o For example, for a yield of k / n = 0.5, the McEliece bound on the minimal distance relative is d / n <0.18. If n = 1024 bits, then we can at most

hope to correct 91 errors.

  Currently, the "turbo-codes" are the most effective correction codes, for a BER of the order of 10-4. When this BER is very low, for example of the order of 10-10, the gain compared to other techniques is less important. Moreover, the yields obtained (typically 1/2) do not seem optimal. The aim of the invention is in particular to overcome these different

disadvantages of the state of the art.

  More precisely, an object of the invention is to provide an error correction coding method offering better performances than known codes. In particular, an object of the invention is to provide such a method,

  allowing to get closer to McEliece's terminal.

  Another object of the invention is to provide such a coding method, which allows a very large gain, especially when the error rates are very high.

weak, of the order of 10-10.

  Another object of the invention is to provide such a method, which allows a gain in efficiency, compared with known coding techniques (for example

  example, a passage of a yield of 1/2 to 1/4 or 1/8).

  Another object of the invention is to provide such a coding method, which is suitable for coding data blocks of average length n, for example

between 128 and 2048 bits.

  Yet another object of the invention is to provide such a method of

  coding, which can be easily implemented in VLSI.

  The invention also aims to provide a corresponding decoding method, which is of reasonable complexity, and in particular which offers a ratio or performance / complexity competitive with the best known codes. These objectives as well as others which will appear later are achieved according to the invention by means of an error correction coding device, of the type associating with a series of source data a block of coded data, intended to be transmitted to at least one receiver, comprising: - at least two coding stages each comprising at least two basic coding modules, each of said coding stages receiving a series of data to be processed, distributed between said basic coding modules, and providing a series of processed data from said basic coding modules; and at least one brewing stage, said brewing stage being inserted between two successive coding stages, a first coding stage and a second coding stage, and distributing the processed data from each base coding module of said first stage coding between at least two basic coding modules

said second floor.

  Such a coding device makes it possible to obtain, for a given yield, a minimum important distance. Such a code (192, 96) of output 1/2, built on the basis of the example described later, thus presents a distance

  The minimum distribution is close to 30. In addition, the weight distribution is close to optimal.

  As will become apparent later, this method can easily be implanted

  in the form of a pipe-line machine, especially in a VLSI.

  Advantageously, the code implemented is systematic, or pseudo-

  systematic. Thus, said coded data block to be transmitted advantageously comprises at least some of said source data and at least some of the processed data from the last coding stage, and preferentially

  all of said source data.

  According to an advantageous embodiment of the invention, said coded data block comprises processed data from at least two coding stages. In other words, one can take into account the data calculated by the last floor, as well as the last stages. We will choose the appropriate compromise, depending on the needs, between the quality of the decoding (taking into account the more

  large amount of information possible) and performance.

  In a particular embodiment, at least one of said brewing stages comprises at least one permutation matrix. It can also be provided that at least one of said brewing stages distributes processed data to at least two distinct coding stages. Both aspects can of course

  to be united in the same device.

  Likewise, at least one of said source data and / or at least one of said processed data can be duplicated at least once, so as to form

at least two data to be processed.

  It can also be expected that at least one of said source data feeds

  directly another coding stage than the first coding stage.

  These different aspects are of course cumulative, and preferentially chosen so as to obtain the best coding, with a decoding remaining

simple enough and effective.

  According to a particular embodiment of the invention, the coding device comprises at least two coding units each comprising at least two of said coding stages and at least one mixing stage inserted between two successive coding stages, said source data feeding each of said

  coding units, in different feed orders.

  It may in particular comprise at least one brewing unit, ensuring a modification of the feed order of said source data in one

said coding units.

  This gives two (or more) separate sets of redundancy data.

  According to an advantageous embodiment, the coding device comprises punching means, implemented on at least some of said

  data to be processed and / or on at least some of said processed.

  Advantageously, said coding modules implement a code of

  redundancy of length n-k less than or equal to 12.

  As already mentioned, the invention applies in particular to the coding of

  relatively small data blocks.

  According to a first embodiment, particularly easy to implement, all said coding modules are identical. Said modules of

  coding can for example implement a Reed-Mtiller code.

  According to a second embodiment, at least two of said modules of

coding are different.

  Advantageously, said device comprises means for controlling and / or adjusting at least one of the following elements: type and / or characteristic of the coding implemented by at least one of the basic coding modules; - Brewing implemented by at least one of said brewing stages; - Punching implemented on at least some of said data to be processed and / or at least some of said processed data;

- number of coding stages.

  Said control and / or said adjustment can act systematically, over a given period, and / or according to at least one piece of information representative of at least one of the aspects belonging to the group comprising: at least one characteristic of the transmission channel; at least one characteristic of the receiver;

  at least one characteristic of the source signal.

  The invention also relates to the error correction coding method implemented by the device described above. According to this method, a series of source data is associated with a block of coded data, intended to be transmitted to at least one receiver, from: at least two coding steps each implementing at least two basic codings, each of said coding steps receiving a series of data to be processed, distributed between said basic codings, and delivering a series of processed data, corresponding to said basic coding; and at least one stirring step, said stirring stage being inserted between two successive coding steps, a first coding step and a second coding step, and distributing the processed data corresponding to each basic coding of said first step of coding. encoding between at least two basic encodings of

said second step.

  The invention also relates to methods and decoding devices

  corresponding. Advantageously, such a decoding method is iterative.

  Preferably, said decoding method implements at least one of the techniques belonging to the group comprising: decoding using a structure symmetrical to that implemented during coding; exhaustive decoding, according to which all the possible code words are considered and the best is selected according to a predetermined selection criterion;

  Viterbi-type decoding, implementing a decoding trellis.

  The invention also relates of course to a device for decoding a

  block of data, implementing this decoding method.

  Advantageously, such a decoding device implements at least two decoding stages, comprising at least two decoding modules, and at least one permutation stage inserted between two consecutive decoding stages, said stages being symmetrical to those of the corresponding coding, each of said decoding modules comprising twice as many inputs and outputs as the corresponding coding module, so as to ensure the propagation of likelihood values on the one hand from the upstream to the downstream of said device, and of other hand

  downstream upstream of said device.

  This gives a gradual convergence of the decoded data

in both directions of decoding.

  Preferably, in at least one of said decoding stages, a normalization step is implemented so as to maintain constant the

likelihood or energy.

  This normalization step can for example keep constant the sum of the absolute values of said likelihood values or the square root

  the sum of squares of said likelihood values.

  According to another advantageous characteristic of the invention, at least one of said permutation stages is implemented with a mixing step associating, with a pair (x, y), likelihood values coming respectively from the upstream and the downstream of said device, a pair (x ', y') of likelihood values such that: x '= a (x + (1- cL) yy' = (1 a) x + (ay

  a being a real between 1 and 1/2.

  It is thus possible to accelerate convergence.

  Preferably, ax varies progressively from 1 to 1/2, as and when

said iterations.

  According to another mode of implementation, simpler, a can be worth systematically 1/2 (which amounts to imposing equality between the value of

  upstream likelihood and downstream likelihood value).

  In another embodiment of a decoding device according to the invention, the latter implements at least one iteration of the following operations: complete propagation in the upstream direction of said device of said likelihood values, delivering a first set of values estimated; complete propagation in the downstream direction of said device of said likelihood values, delivering a second set of estimated values. It can then advantageously summing the estimated values of each of said sets of estimated values, the next iteration being performed on the results of said summation. According to another embodiment, the decoding device associates with each output of one of said decoding modules a Boolean function involving at least two inputs of said corresponding coding module, a decoding constraint imposing a downstream output of a given decoding stage

  equal to the corresponding upstream output of the next decoding stage.

  A partial posterior likelihood value is then calculated for each input, as a function of the posterior likelihoods assigned to the downstream and upstream outputs associated with the same internal Boolean variable of the corresponding coding module, and as a function of the posterior likelihood of the Entrance

corresponding.

  Other characteristics will appear more clearly on reading the

  following description of a preferred embodiment, given as a simple

  illustrative and nonlimiting example, and appended drawings, among which: - Figure 1 illustrates the boundaries of McEliece and Gilbert -Varshamov; FIG. 2 illustrates the general principle of a coding device according to the invention; FIG. 3 is a particular example of a coding device according to FIG. 2; FIG. 4 illustrates other aspects that can be implemented in

  a coding device according to the invention.

  The technique of the invention thus allows the construction of quasi-identical codes.

  optimal (referred to as "cortex codes"), to which a method of

  Specific decoding with soft decision is advantageously associated.

  The results obtained are of better quality than those of "turbocodes".

  Indeed, the minimum distance d of current turbo-codes is relatively small. Indeed, for example a Pyndiah block turbo-code which is a product code (32,26,4) x (32,26,4) = (1024,676,16), is therefore a length code n = 1024 for k = 676 useful bits and a minimum distance d = 16. With this code en bloc, you can not

  therefore correct at most t = [(d - 1) / 2 = 7 errors in hard decision.

  As another example, a 192-bit Berrou block turbo-code (see Jung et al., [19]) with a 1/3 efficiency, has an estimated minimum distance of 8 with an optimized interleaver. On the other hand, a "cortex" code (192,96) of yield 1/2 has a minimal distance close to 30. The distribution of the weights of the "cortex" codes also seems to tend towards the binomial distribution which is that of the coding

  optimal randomness (see G. Battail [16]).

  The general principle of the invention lies in the implementation of

  several coding modules, organized according to the block diagram of FIG.

  These coding modules are grouped into at least two stages 211 to 21n.

  Each coding stage 21 i comprises at least two coding modules 22j, j

operating independently.

  Between each coding stage 21 i and 21j + 1 is inserted a stirring stage 231 to 23n. 1. The data coming out of each coding module of stage 22i are

  thus distributed between several coding modules of the stage 22i + 1.

  This distribution is preferably carried out so as to distribute the best

  bits received from the same coding module.

  In the embodiment described, the code implemented is a systematic block code. The transmitted bit packet therefore comprises the useful bits 24, or source bits, and the redundancy bits 25 coming from the coder. Of course, a

  punching can be implemented.

  According to a particular embodiment of the invention, illustrated by FIG. 3, the coding modules 22ij are all identical, and implement a code

  from Reed-Mler (8, 4, 4). This gives a "cortex" code (48, 24).

  The matrix generating the Reed-Miller code used is as follows: (I O O 001 1 l1

0 1 0 0 1 0 1 1

G = 0 0 1 0 1 1 0 1

O 0 0 1 1 1 10

  If the four incoming useful bits are (x0, x1, x2, x3), the four redundancy bits are (x4, x5, x6, x7) such that {X4 = Xi + X + X3 X-x4 -X0 + 24x3 X4 = Xo + X2 + X3

X4 = XO + XI + X3

X4 = X- + X1 + X2

  Each coding stage 211, 212 and 213 comprises six basic coding modules (8, 4, 4) 22 1, at 223.6. The redundancy bits of the first coding stage 211 are subjected to a permutation rI1 (231). This permutation can be considered as a "jungle of son" which makes it possible to obtain a good correction capacity, if it is appropriately chosen (for example by successive tests

and simulation).

  The second coding stage 212 performs a new calculation of 24 new intermediate redundancy bits, which are again switched by the brewing stage n 2 (232). The process can implement this way

several stages of coding.

  It is of course possible to transmit all the bits calculated with the useful bits.

  However, the code obtained then has a low yield. It may be preferred to transmit only the start useful bits 24 and the redundancy bits 25 of the last stage. These codes have been found to have very good minimum distances, and

  weight distributions having "binomial distribution tails", i.e.

  say a very small number of neighbors after this minimum distance. Many variations and adaptations of this principle can be envisaged. Figure 4 illustrates schematically and fictitiously (i.e., simplified for illustrative purposes) some of them. They may well

  sure to be implemented independently, or in any suitable combination.

  FIG. 4 shows a first coding stage 41 comprising a plurality of identical coders C1411. These coders are fed by the source data 42. They can also take into account intermediate data 43 "reinjected" from any location in the processing chain. The data coded by these coding modules 411 feed a permutation matrix 44, which distributes the data between a plurality of coders of a second coding stage 45. Unlike the first coding stage 41, this second coding stage 45 Several different encoders C2, C3, C4 452 to 454 are used. These different codes can be of any suitable type. For example, they will be chosen because of their coding efficiency and / or the ease of

corresponding decoding.

  The next permutation stage consists of several patching modules 461, 462, in which the distribution of the intermediate data received from the coding stage 45 is distributed in a variable manner to the different coding modules 471 of the coding stage. next 47. This brewing 461, 462

  may be regular, random or controlled based on information 481.

  The transmission chain may further comprise one or more C6 encodings 49 (providing coding and / or encryption, for example), which acts on

  all the data it receives from previous coding modules.

  Punching 410 can be performed at different points of the chain and on different data. In the example illustrated, the punching 410 is performed on a set of data comprising: the source data 42; data from the last coding stage 491;

  at least some of the intermediate data 4101.

  More generally, the data, whether it is the source data 42 or the intermediate data 4101, can be distributed in a very different way to

  inside the processing chain.

  By way of example, the following cases have been illustrated: an intermediate data item 51 is directed to two distinct coding stages 45 and 47 simultaneously; a source data item 52 undergoes the same "decoupling" between an encoding module of the first coding stage 41 and the coding stage; a data item 53 simultaneously supplies two (or more) coding modules 453 and 454 of the same coding stage 45; a data item 54 from the permutation stage 44 directly supplies the coding stage 47 (and not the nearest stage 45); data 55 is selectively directed to a first coding module 452 or a second coding module 453; a data item 56 received by a coding module 454 corresponds selectively to two (or more) intermediate data; source data 57 are introduced into a coding stage 45

  other than the first coding stage 41 of the chain.

  Provision may also be made for all or part of the source data to supply, on the one hand, a first coding unit, consisting of at least two coding stages and at least one intercalated stirring stage, and on the other hand after stirring (for example a permutation), a second coding unit, also formed of at least two coding stages and at least one intercalated stirring stage. This gives two sets of redundancy data (on

  which punching is of course possible).

  These are of course only examples that can be adapted and generalized. Moreover, many aspects of the processing can be variable or controlled according to various information such as, for example: information on the transmission channel (noise level, types of noise, etc.); - information on the decoder (processing capacity, storage capacity, ...); information on the type of data transmitted (structure and / or characteristics of the data blocks, type of information (images, sounds, data, etc.), coding quality required, etc.); an instruction given by a user; 15 ... Thus the control module 48 can control: the permutations or mixing done (481); the encodings used (type of codes and / or characteristics of the code) (482);

punching (483).

  The choice of codes implemented in the coding modules takes into account in particular the efficiency and the ease of decoding. Classically, we will choose a base code such that the value n - k is small. The choice of permutations (or shuffling) is preferably carried out so as to ensure a great diversity between the Boolean functions of each output. More specifically, it is ensured that, finally, the Boolean function of each redundancy output bit is composed of a most different set of information bits.

  possible from those of other redundancy output bits.

  We can for example look for matrices and basic codes allowing

  to recreate a known code such as for example the Golay code (24, 12, 8).

  The invention also relates to the method and device for decoding the data produced by the coding method described above. this decoding is relatively simple and inexpensive to implement. It is advantageous

  iterative, which makes it easily implementable and adaptable.

  Most conventional decoding techniques can be implemented. Thus, it is possible to implement exhaustive decoding, according to which all the possible codewords are considered and the best is selected according to a predetermined selection criterion. It is also possible to use a Viterbi type decoding, implementing a decoding trellis (for example according to

SOVA or BJCR algorithms).

  Advantageously, a decoding is implemented whose structure is modeled on the structure of the encoder described above. In other words, the decoder comprises several decoding stages each comprising several

  decoding modules, and separated by permutation stages.

  This structure is easily implemented in the form of a pipeline machine,

in VLSI.

  FIG. 5B illustrates a decoding module, corresponding to the coding module illustrated in FIG. 1A (implementing a ReedMuller coding

(8,4,4).

  This decoding module is a weighted-input and weighted-output decoder, made for example from known techniques, such as the SOVA method. It implements additions and subtractions. In addition, according to

  the invention, it implements normalization multiplications outputs.

  This normalization can consist in particular of keeping constant the sum of the absolute values of the likelihoods, or the square root of the sum of the squares of the likelihoods. In other words, we work, according to the invention,

  likelihood or constant energy.

  Each wire (input or output) of the coding module of FIG. 5A, corresponding to one bit of the coder, is split into two wires in the decoding module of FIG. 5B. These wires make it possible to communicate or propagate the likelihood values from upstream to downstream of the decoder, or from downstream to upstream. The calculations in the decoder are carried out according to a particular sequencing in order to minimize these. We first introduce the received values on the data likelihood input wires and the redundancy bits. The likelihood value is equal to the ratio log (probability (bit = 0) / probability (bit = 1)), which is, in the case of a Gaussian channel, proportional to the value received, in the case of a modulation 2-state, (0, 1)

associating (+1, -1).

  Values that are not defined when the network is initialized are by default set to

  a predetermined value, advantageously zero.

  Referring to the structure of the encoder of FIG. 2, which is similar to that of the decoder, the decoding is carried out as follows: the received likelihood values to be processed are introduced into the end decoding stages ( first and last floors); the new calculated likelihood values feed the neighboring stages, and so on up to the central stage (if the number of decoding stages is odd) or the central stages (if the number of decoding stages is even ); - Then, the process follows the reverse path, from central stages to

  the end stages, up to the first and last floors.

  These steps correspond to an iteration of the processing. They are repeated either up to a given number of iterations, or with a stop of the iterations according to a criterion of minimization of the sum of the absolute values or the square root of the squares of the differences of the incoming and outgoing likelihoods

  for each wire, for at least one floor.

  In fact, it is verified that, as iterations are progressing towards an equality between the two likelihood signals entering and leaving the same bit,

in a decoding module.

  Advantageously, the permutation stages implement a mixing step, associating with a pair of incoming data (x, y) a pair of outgoing data (x ', y') such that: x '= x + (the ) y Y '= (1-a) x + ay It is thus possible, between two decoding stages, to accelerate the convergence. Preferably, the mixing coefficient a varies gradually, as iterations, from 1 to 1/2, in order to

  start with a weak mix and finish with a strong mix, even total.

  According to a simplified embodiment, one can set the value of at to 1/2.

  This forces the equality between the upstream and downstream likelihoods (x '= y').

  Another embodiment of the decoding, still based on a structure similar to that of the encoder of FIG. 2, consists in having the data carry out a complete propagation in the upstream direction of the coder (from the beginning to the

  end, floor after floor), then in the downstream direction, according to a principle of the "forward-

  backward "(" forward-backward "), the estimated values obtained in each upstream and downstream direction are then added, and then the same operations are repeated on these

sums of estimated values.

  In another implementation variant, based on the same principle of forward-backward travel of the decoder, the Boolean equation associated with each wire (each output of a decoding module) is taken into account. The value carried by this wire is assigned a posterior likelihood in proportion to the likelihood received and / or in proportion to the similarity of the upstream and downstream posterior likelihoods. In other words, if the bit considered is present in the Boolean equation, it is associated with a likelihood taking into account the likelihood

  associated with the other bits of this equation.

ANNEX

  [1] F.J. MacWilliams, N.J.A. Sloane, "The Theory of Error-Correcting Codes,"

North-Holland, 3rd edition, 1981.

  [2] S.B. Wicker, "Error Control Systems for Digital Communication and

Storage ", Prentice Hall, 1995.

  [3] V. Pless et al. "The Handbook of Coding Theory", Elsevier, 1998.

  [4] C. E. Shannon, "A Mathematical Theory of Communication," Bell System

  Technical Journal, pp. 379423 and 623-656, No. 27, 1948.

  [5] P. Elias, "Coding for Noisy Channels", IRE Conv. Record, Part 4, pp.

37-47, 1955.

  [6] A.J. Viterbi, "Error bounds for convolutional codes and an asymtotically

  optimum decoding algorithm ", IEEE, IT13, pp. 260-269, 1967.

  [7] G.D. Fomrney Jr., "The Viterbi algorithm", Proceedings of the IEEE, Vol.61,

pp. 268-276, Marchl969.

  [8] R. E. Bellman, "Dynamic programming", Princeton University Press, 1965.

  [9] R.J. McEliece, "On the BCJR Trellis for linear block codes", IEEE, IT

* Vol.42, pp. 1072-1092, July 1996.

  [10] C. Berrou, A. Glavieux, P.Thitimajshima, "Near Shannon Limit Error-Correcting Coding and Decoding: Turbo-Codes", Proceedings of the

  ICC '93, Geneva, Switzerland, May 1993, pp.1064-1070.

  [11] L. R. Bahl, J. Cocke, F. Jelinek, J. Raviv: "Optimal decoding of linear codes for minimizing symbol error rate", IEEE, Vol. IT20, pp.284287, March 1974. [12] G. Battail, "Weighting of symbols decoded by the Viterbi algorithm", Annals of Telecommunications, Vol. 31, No. 1-2, pp. 31-38, January-February 1987. [13] J. Hagenauer, P. Robertson, L. Papke, "Iterative turbo decoding of systematic convolutional codes with the MAP and the SOVA algorithms", in

Proc.ITG'94, 1994.

  [14] R. Pyndiah, A. Glavieux, A. Picart, S. Jacq, "Near optimum decoding of products codes", Proc. GLOBECOM 94, San Francisco, CA, Dec. 94, pp.

339-343.

  [15] C. Berrou, A. Glavieux, "Near Optimum Error Correcting Coding and Decoding: Turbo Codes," IEEE, Vol. IT44, no. 10, October 1996, pp.

1261-1271.

  [16] G. Battail, "A conceptual framework for understanding turbo-codes", International Symposium on turbo-codes, ENST-Brest, September 1997, pp. -62. [17] C. Berrou, M. Jézéquel, "Frame-oriented convolutional turbo-codes",

  Electronics letters, 18th July 1996, Vol.32, no. 15, pp. 1362-1364.

  [18] Adde P., R. Pyndiah, C. Berrou, "Performance of Hybrid Turbo Codes,"

  Electronics letters, 21th November 1996, Vol.32, no. 24, pp. 2209-2210.

  [19] P. Jung, M. NaBan "Performance evaluation of turbo codes for short frame transmission systems", Electronics Letters, 20th January 1994, Vol.30, No. 2, pp.

111-113.

Claims (27)

  An error correction coding device, of the type associating a block of coded data with a series of source data, intended to be transmitted to at least one receiver, characterized in that it comprises: at least two coding stages each comprising at least two basic coding modules, each of said coding stages receiving a series of data to be processed, distributed between said basic coding modules, and delivering a series of processed data, originating from said basic coding modules; and at least one brewing stage, said brewing stage being inserted between two successive coding stages, a first coding stage and a second coding stage, and distributing the processed data from each base coding module of said first stage of coding. coding between at least two basic coding modules of said second floor.   2. Encoding device according to claim 1, characterized in that said coded data block to be transmitted comprises at least some of said source data and at least some of the processed data from the last stage. coding.   3. Encoding device according to claim 2, characterized in that said block of coded data to be transmitted comprises all of said source data.   4. Encoding device according to any one of claims 1 to 3,   characterized in that said coded data block comprises processed data   from at least two coding stages.   Coding device according to one of Claims 1 to 4,   characterized in that at least one of said brewing stages comprises at least a permutation matrix.   Coding device according to one of Claims 1 to 5,   characterized in that at least one of said brewing stages distributes data   processed to at least two distinct coding stages.   Coding device according to one of Claims 1 to 6,   characterized in that at least one of said source data and / or at least one of said processed data is duplicated at least once, so as to form at least one minus two data to process.   Coding device according to one of Claims 1 to 7,   characterized in that at least one of said source data feeds directly a   other coding stage than the first stage coding.   Coding device according to one of Claims 1 to 8,   characterized in that it comprises at least two coding units each comprising at least two of said coding stages and at least one mixing stage inserted between two successive coding stages, and in that said source data feed each of said coding units ,   in different feeding orders.   10. Encoding device according to claim 9, characterized in that it comprises at least one mixing unit, ensuring a modification of the order   supplying said source data in one of said coding units.   Coding device according to one of Claims 1 to 10,   characterized in that it comprises punching means, implemented on at least some of said data to be processed and / or on at least some of said processed.   Coding device according to one of Claims 1 to 11,   characterized in that said coding modules implement a code of   redundancy of length n-k less than or equal to 12.   Coding device according to any one of claims 1 to 12,   characterized in that all said coding modules are identical.   Coding device according to claim 13, characterized in that said   Coding modules implement a Reed-Muller code.   Coding device according to one of Claims 1 to 12,   characterized in that at least two of said coding modules are different.   Coding device according to any one of claims 1 to 15,   characterized in that it comprises means for controlling and / or adjusting at least one of the following elements: - type and / or characteristic of the coding implemented by at least one of the basic coding modules; brewing implemented by at least one of said brewing stages; punching implemented on at least some of said data to be processed and / or at least some of said processed data; - number of coding stages.   Coding device according to claim 16, characterized in that said control and / or said setting systematically acts, over a given period, and / or according to at least one piece of information representative of at least one of the aspects belonging to the group comprising: - at least one characteristic of the transmission channel; at least one characteristic of the receiver;   at least one characteristic of the source signal.   18. A method for error correction coding, of the type associating a block of coded data with a series of source data, intended to be transmitted to at least one receiver, characterized in that it comprises: at least two coding steps each implementing at least two basic encodings, each of said coding steps receiving a series of data to be processed, distributed between said basic encodings, and delivering a series of processed data, corresponding to said basic coding; and at least one stirring step, said stirring stage being inserted between two successive coding steps, a first coding step and a second coding step, and distributing the processed data corresponding to each basic coding of said first step of coding. encoding between at least two basic encodings of said second step.   19. A method of decoding a coded data block by a device   coding according to any one of claims 1 to 17.   20. Decoding method according to claim 19, characterized in that it is iterative.   21. Decoding method according to any one of claims 19 and 20,   characterized in that it implements at least one of the techniques belonging to the group comprising: decoding using a structure symmetrical to that implemented during coding; exhaustive decoding, according to which all the possible codewords are considered and the best is selected according to a predetermined selection criterion;   Viterbi-type decoding, implementing a decoding trellis.   2. Device for decoding a data block, implementing the method   decoding device according to any one of claims 19 to 21.   23. Decoding device according to claim 22, characterized in that it implements at least two decoding stages, comprising at least two decoding modules, and at least one permutation stage inserted between two consecutive decoding stages, said stages being symmetrical to those of the corresponding coding, and in that each of said decoding modules comprises twice as many inputs and outputs as the corresponding coding module, so as to ensure the propagation of likelihood values on the one hand the upstream downstream of the said   device, and secondly from the downstream upstream of said device.   24. The decoding device as claimed in claim 23, characterized in that, in at least one of said decoding stages, a step of   normalization, so as to keep the likelihood or the energy constant.   25. Decoding device according to claim 24, characterized in that said normalization step keeps constant the sum of the absolute values of said likelihood values or the square root of the sum of the squares. said likelihood values.   26. Decoding device according to any one of claims 23 to 25,   characterized in that, in at least one of said permutation stages, a mixing step is implemented, associating a pair (x, y) of likelihood values, coming respectively from the upstream and the downstream of said device. , a pair (x ', y') of likelihood values such that: x '= ctx + (1- co) y {' = (1 - a) x + ay   ac being a real between 1 and 1/2.   27. Decoding device according to claim 26, characterized in that   varies gradually from 1 to 1/2, as said iterations.   The decoding device according to claim 26, characterized in that worth 1/2.   The decoding device according to any one of claims 23 to 28,   characterized in that it implements at least one iteration of the following operations: complete propagation in the upstream direction of said device of said likelihood values, delivering a first set of estimated values; complete propagation in the downstream direction of said device of said likelihood values, delivering a second set of estimated values. 30. Decoding device according to claim 29, characterized in that it performs the summation of the estimated values of each of said sets of values.   estimated, the next iteration being performed on the results of said summation.   31. The decoding device as claimed in claim 29, characterized in that it takes into account, for each output of one of said decoding modules, a Boolean function involving at least two inputs of said corresponding coding module, and in that a decoding constraint imposes that a downstream output of a given decoding stage is equal to the corresponding upstream output of the next decoding stage.