FR2781923A1 - Capacitor, especially for a DRAM, is produced by self-aligned formation of a capacitor ring structure on a semiconductor substrate having a MOS transistor - Google Patents

Abstract

A capacitor production process, in which a capacitor of ring structure is formed in a self-aligned manner on a semiconductor substrate (30) having a MOS transistor (32, 33, 34a, 34b). A capacitor is produced on a semiconductor substrate (30), having a MOS transistor (32, 33, 34a, 34b), by (a) forming and then patterning a first insulation layer (36) to form a hole exposing the transistor source/drain region (34a, b); (b) applying a first conductive layer (38b), which fills the via hole, and then a second insulation layer; (c) applying and patterning a photosensitive resin layer to define a cylindrical structure of the second insulation layer and the first conductive layer, including the via hole filling; (d) removing part of the photosensitive resin layer to expose an edge of the upper surface and a side wall of the first conductive layer; (e) forming a silicon oxide layer on the exposed first conductive layer and removing the second insulation layer to expose the first conductive layer portion which is not covered by the silicon oxide layer; (f) removing the exposed first conductive layer, using the silicon oxide layer as mask, so that a ring structure (38b) is formed; (g) removing the silicon oxide layer; and (h) successively forming a dielectric layer (43) and a second conductive layer (44) on the first conductive layer (38b).

Description

METHOD FOR MANUFACTURING A CAPACITOR

  ON A SUBSTRATE HAVING A MOS TRANSISTOR

  The invention relates to a method for manufacturing a condensate.

  tor in an integrated circuit (Cl), and it relates more particularly to a process for manufacturing a capacitor in a dynamic random access memory.

mique (or DRAM).

  FIG. 1 shows a single memory cell comprising a transfer transistor T and a capacitor C of a DRAM memory. The source of the transfer transistor T is connected to a corresponding bit conductor BL. The drain of the transfer transistor T is connected to a storage electrode 10 of the capacitor C, and the gate of the transistor

  transfer terminal T is connected to a corresponding word conductor WL.

  An electrode 12 opposite the storage electrode 10 is connected from

  so as to receive a constant supply voltage, and a di-

  electric 14 is formed between the storage electrode 10 and the electrode

opposite 12.

  To increase the storage capacity in the capacitor, alongside the use for the dielectric layer of a material having a high dielectric constant, or the control of the quality and

  the deposit thickness for the dielectric layer, one can also obtain

  hold a high capacity by increasing the surface area of the electrode

  storage. However, as the size of the mete

  moire becomes smaller, making a storage electrode having a larger surface area on the smaller substrate becomes

a significant problem.

  In a single chip, to increase the volume of data storage, the recording density of a memory in an integrated circuit is increased. The high density of a memory provides a recording structure with a higher level of integration. Normally, the density of an IC device is increased by reducing the dimensions of the interconnection conductors, transistor gates or device isolation regions. The size reduction of devices and structures is carried out in accordance with the design rule for

semiconductor manufacturing.

  To increase the surface area of a lower electrode, i.e. a storage electrode, an uneven surface structure, e.g. a crown structure, a cylinder structure, a fin structure, a tree structure, or cavity structure, is adapted to provide a larger surface area. We train in

  in addition to the surface of the above structures a semi-grained material

  spherical, to increase the surface area. With the formation of the hemispherical grain structure, the capacity gain rises up to

1.8.

  In the conventional technique of manufacturing an inferior electrode

  having a crown structure, as shown in FIG. 2, a pattern is defined in a polycrystalline silicon layer 25, by photolithography, to form a lower electrode on a semiconductor substrate 20. The substrate 20 further comprises a conductor

  word 21 of a metal-oxide-semiconductor (MOS) structure, a conduc-

  bit counter 22, source / drain region 23 and an insulating layer

  24. Due to the restriction imposed by photo-resolution and by the

  gle of design, during the exposure, the width u of the upper branch of the crown structure can not be reduced indefinitely, and therefore the possibility of increasing the surface area

is limited.

  An object of the invention is therefore to provide a method of manufacturing

  cation of a capacitor having a crown structure, by a pro-

  self aligned alignment. The restriction on the design rule and the

  photo-resolution is eliminated, and the misalignment during the ex-

position is reduced.

  To achieve these aims and advantages, and in accordance with its object, the invention, as it is implemented and described here generally, relates to a process for manufacturing a capacitor. On a semiconductor substrate having a metal-oxide-semiconductor transistor, comprising a source / drain region connected to a bit conductor, a first insulation layer is formed so as to cover the transistor and the substrate. A pattern is defined in the first layer of insulation to form a through hole which penetrates through the first layer of insulation, so as to expose a source / drain region of the transistor. A layer of polycrystalline silicon is formed

  on the first layer of insulation and this layer fills the pass-through hole

  wise. A layer of silicon nitride is formed on the layer of silicon.

  polycrystalline cium. A layer of silicon nitride is formed on

  layer of photosensitive resin, and a pattern is formed therein

  niere, to define the silicon nitride layer and the silicon layer

  polycrystalline cium, so as to form a cylinder structure which

  takes the layer of silicon nitride and the layer of polycrystalline silicon

  flax, including polycrystalline silicon which is inside the through hole. Part of the photosensitive resin layer is removed to define the silicon nitride layer so that an edge of an upper surface and a side wall of the polycrystalline silicon layer are exposed. A layer of silicon oxide is formed on the bare polycrystalline silicon layer. By removing the layer of silicon nitride, the layer of polycrystalline silicon which is not covered by the oxide of

  silicon is exposed. The bare polycrystalline silicon layer is removed

  vee using the silicon oxide layer as a mask, until a crown structure is formed. The layer of silicon oxide is removed. A polycrystalline silicon layer is formed

  layer of silicon with hemispherical grains. We form a di-

  electric on the silicon layer with hemispherical grains, and we form

  a second conductive layer on the dielectric layer.

  Other characteristics and advantages of the invention will be

  better understood on reading the description which follows in a

  embodiment, given by way of nonlimiting example. The rest of the description

  tion refers to the accompanying drawings in which:

  Figure 1 is a circuit diagram of a standard DRAM memory.

if that;

  Figure 2 is a section through a lower electrode of a con-

  classic DRAM memory densifier; and

  Figures 3A to 31 are cross-sections of the manufacturing process.

  tion of a capacitor in a DRAM memory, in an embodiment

  preferred station according to the invention.

  In FIG. 3A, a device insulation structure 31 is formed on a silicon substrate 30, for example a field oxide layer with a thickness of approximately 300 nm formed by local oxidation

  (or LOCOS), or a shallow trench. Using a treat-

  thermal oxidation layer, a gate oxide layer 32 is formed on the substrate 30. A doped polycrystalline silicon layer is formed, for example by chemical vapor deposition (or CVD), and a pattern is defined in that here to form a grid (33) (or a word conductor) on the grid oxide layer 32. A source / drain region 34a, 34b is formed in the substrate 30. By a conventional technique, a polycrystalline silicon layer and there is defined therein a pattern corresponding to a bit conductor 35, for connection to one of the source / drain regions 34a, 34b. The word conductor 33 and

  the bit conductor 35 are separated by an insulation layer.

  Referring to FIG. 3B, it is noted that a flat insulation layer 36 is formed, for example by CVD, to cover the word conductor 33 and the bit conductor 35. The flat insulation layer 36 is by example a borophosphosilicate glass (or BPSG) formed by CVD at atmospheric pressure (or APCVD), or by CVD reinforced by plasma (or PECVD). After deposition, the insulating layer is flattened by remelting or chemo-mechanical polishing (or CMP). The planing process

  is advantageous for the following deposition and photolithography processes

  touts. For example, a more accurate pattern of the through hole or others

  structures is obtained during the exhibition. By proceeding by photoli-

  thography, we form a through hole 37 which penetrates through the

  insulation 36, so that the source / drain region 34a is set to

  naked inside the through hole 37.

  Referring to FIG. 3C, it is noted that a first polycrystalline silicon layer 38 is formed on the insulation layer 36 and that it

  fills through hole 37. The first layer of polycrystalline silicon

  lin 38 is doped and has a thickness of about 100 nm to 1000 nm. We

  forms a large layer on the first layer of polycrystalline silicon 38

  of silicon nitride 39 having a thickness of about 5 nm to 100

  nm. A layer of silicon is formed on the layer of silicon nitride 39.

  photosensitive sine 40 in which a pattern is defined. Using ti-

  be mask the photosensitive resin layer 40, we define the pattern

  of the silicon nitride layer 39 and of the first silicon layer

  polycrystalline cium 40, for example by dry etching, for

  sea cylinder structure comprising a layer of silicon nitride

  cium 39a and a first layer of polycrystalline silicon 38a, as shown in FIG. 3D. The cylinder structure also comprises the first layer of polycrystalline silicon which fills the through hole 37. Part of the photosensitive resin layer 40 is removed,

  for example by an isotropic plasma process in an environment

  oxygen, to transform part of the photosensitive resin layer 40 into ash. The remaining photosensitive resin layer 40a has a shape which is illustrated in FIG. 3E. The remaining photosensitive resin layer 40a is used as a mask to define the silicon nitride layer 39a. We remove, for example by attack

  dry, part of the silicon nitride layer 39a, that is

  ie the part which is not covered by the photo-resin layer

  sensitive 40a. Therefore, an edge on the upper surface and a side wall of the first layer of polycrystalline silicon 38 are exposed, as shown in Figure 3F. On the other hand, only the central upper surface of the first layer of polycrystalline silicon 38a

  is covered by the remaining silicon nitride layer 39b. We-

  then lifts the photoresist layer 40a.

  Referring to Figure 3G, we note that by oxidation,

  thermal tion of the surface of the first layer of polycrystalline silicon

  tallin 38a bare, a layer of silicon oxide 41 with a thickness

from about 10 nm to 300 nm.

  The remaining silicon nitride layer 39b is removed by wet attack using hot phosphoric acid as

  attack agent. Therefore, the first layer of poly-

  lens 38a which is discovered by the layer of silicon oxide 41 is exposed. Referring to FIG. 3H, it is noted that by using a dry attack, the first layer of polycrystalline silicon 38a is exposed naked. By controlling the attack duration, a layer of

  polycrystalline silicon 38b having a crown structure.

  In the above process, we use a self-

  aligned to make a crown structure 38b, so that the lar-

  geur v of the hollow column of the crown structure 38b is not restricted by the photo-resolution during the photolithography. Thus, the width v can be reduced as required. With the reduction of the width v, a larger surface of the bottom electrode is obtained, and

  therefore the capacity is increased.

  Referring to Figure 31, we note that the layer is removed

  of oxide 41. A layer of silicon with heterogeneous grains is selectively formed

  spherical 42 on the crown structure 38b. We dope with a do-

  pant the hemispherical grain silicon layer 42. A lower electrode is formed by the assembly of the hemispherical grain silicon layer 42 and the crown structure 38b. A dielectric layer 43 is formed on the silicon layer with hemispherical grains 42, for example an oxide / nitride / oxide (ONO) layer. We form a

  upper electrode 44 on the dielectric layer e43.

  In the embodiment, a lower electrode having a

  crown structure is formed by a self-aligned process. The res-

  friction relating to the design rule for manufacturing, and reduction

  tion of limited size devices due to photo-resolution, are eliminated. With the deposition of hemispherical grain silicon on the

  crown structure, the surface area is further increased

  floor. The capacity is further increased.

  It goes without saying that many modifications can be made.

  brought to the device described and shown, without departing from the scope of the invention

tion.

Claims (24)

  1. Method of manufacturing a capacitor, in which   provides a semiconductor substrate (30) having a metal-oxide transistor   semiconductor (32, 33, 34a, 34b), characterized in that it comprises the following steps: a first insulation layer (36) is formed so as to cover the transistor and the substrate (30); a pattern is defined in the first insulation layer (36) to form a through hole (37) which penetrates through the first insulation layer (36), so as to expose a source / drain region ( 34a, 34b) of the transistor; a first conductive layer (38) is formed on the first insulation layer (36), so that it fills the through hole (37); forming a second insulation layer (39) on the first conductive layer; forming on the second insulation layer (39) a layer of photosensitive resin (40) in which a pattern is formed, to define the configuration of the second insulation layer (39) and of the first conductive layer (38) , so as to form a cylinder structure comprising the second   insulation layer (39a) and the first conductive layer (38a), including   taken the first conductive layer inside the through hole (37);   part of the photosensitive resin layer (40) is removed to   finish the second layer of insulation (39a), so that one edge of a   upper face and a side wall of the first conductive layer (38a) are exposed; forming a layer of silicon oxide (41) on the first conductive layer (38a) exposed; removing the second insulation layer (39b), so as to expose the first conductive layer (38a) which is not covered by the silicon oxide layer (41); removing the first conductive layer (38a) exposed, using the silicon oxide layer (41) as a mask, until a crown structure (38b) is formed; we remove the silicon oxide layer   (41); a dielectric layer (43) is formed on the first layer   ducting (38a); and a second conductive layer (44) is formed on the dielectric layer (43).   2. Method according to claim 1, characterized in that there is also a bit conductor (35) connected to another region of   source / drain (34a, 34b) of the transistor.   3. Method according to claim 1, characterized in that the   first conductive layer (38) comprises a layer of poly- doped lens.   4. Method according to claim 1, characterized in that the first conductive layer (38) has a thickness of about 100 nm to 1000 nm. 5. Method according to claim 1, characterized in that the   second insulation layer (39) is a layer of silicon nitride.   6. Method according to claim 5, characterized in that the   second layer of insulation (39) is removed by wet attack.   7. Method according to claim 6, characterized in that the at-   wet tackling is carried out using phosphoric acid.   8. Method according to claim 1, characterized in that the second insulation layer (39) has a thickness of about 5 nm to 100 nm. 9. Method according to claim 1, characterized in that the aforementioned part of the photoresist layer (40) is removed by   plasma treatment in an oxygen environment.   10. Method according to claim 1, characterized in that the   silicon oxide layer (41) is formed by thermal oxidation.   11. Method according to claim 1, characterized in that the silicon oxide layer (41) has a thickness of approximately 10 nm to 300 nm. 12. Method according to claim 1, characterized in that   that before the dielectric layer (43) is formed, a layer is formed   che with hemispherical grains (42) on the first conductive layer (38a). 13. Method according to claim 1, characterized in that the   second conductive layer (44) includes a layer of poly- doped lens.   14. Method for manufacturing a capacitor, in which   provides a semiconductor substrate (30) having a metal-oxide transistor   semiconductor (32, 33, 34a, 34b), characterized in that it comprises the   following steps: a first layer of insulation (36) is formed   lesson in covering the transistor and the substrate (30); a pattern is defined in the first insulation layer (36) to form a through hole (37) which penetrates through the first insulation layer (36), so as to expose a source / drain region ( 34a, 34b) of the transistor; forming a layer of polycrystalline silicon (38) on the first insulating layer (36) and so that it fills the through hole (37); forming a layer of silicon nitride (39) on the layer of polycrystalline silicon (38); forming a layer of photosensitive resin (40) on the silicon nitride layer (39) and forming a pattern therein, to define the configuration of the silicon nitride layer (39) and the silicon layer polycrystalline (38), so as to form a cylinder structure comprising the layer of silicon nitride (39a) and the layer of polycrystalline silicon (38a), including polycrystalline silicon inside the hole   passage (37); part of the photoresist layer is removed   a screen (40) for defining the silicon nitride layer (39a) so that an edge of an upper surface and a side wall of the polycrystalline silicon layer (38a) are exposed; forming a layer of silicon oxide (41) on the bare polycrystalline silicon layer (38a); removing the layer of silicon nitride (39b), so as to expose the layer of polycrystalline silicon (38a) which is not covered by the layer of silicon oxide (41); the layer of polycrystalline silicon (38a) is removed bare, using the silicon oxide layer as a mask   (41), until a crown structure (38b) is formed; we-   lifts the silicon oxide layer (41); forming a layer of hemispherical grain silicon (42) on the layer of polycrystalline silicon (38a); forming a dielectric layer (43) on the silicon layer with hemispherical grains (42); and we form a second conductive layer   (44) on the dielectric layer (43).   15. The method of claim 14, characterized in that there is also a bit conductor (35) connected to another region of   source / drain (34a, 34b) of the transistor.   16. Method according to claim 14, characterized in that the   polycrystalline silicon layer (38) is doped with a dopant.   17. The method of claim 14, characterized in that the polycrystalline silicon layer (38) has a thickness of about 100 nm at 1000 nm.   18. The method of claim 14, characterized in that the   layer of silicon nitride (39) is removed by etching   mide. 19. Method according to claim 18, characterized in that   the wet attack is carried out using phosphori-   than. 20. Method according to claim 14, characterized in that the   silicon nitride layer has a thickness of about 5 nm to 100 nm.   21. The method of claim 14, characterized in that the aforementioned part of the photosensitive resin layer (38) is removed by   plasma treatment in an oxygen environment.   22. Method according to claim 14, characterized in that the   silicon oxide layer (41) is formed by thermal oxidation.   23. The method of claim 14, characterized in that the silicon oxide layer (41) has a thickness of about 10 nm to 300 nm. 24. Method according to claim 14, characterized in that the   second conductive layer (44) includes a layer of poly- doped lens.