FR2778761A1 - Control of execution of programs in computer using internal events in the processor running real-time preemptive multitasking - Google Patents

Abstract

The control procedure pre-loads (302) one or more counters with a first value, and decrements the counter (303) with each occurrence of a predetermined event internal to the processor. The value of each count is compared (304) with a second predetermined value, and when one of the counters attains this second value the program execution is modified (305).

Description

The present invention relates to a device and a method for

  management of computer program execution conditions.

  It applies, in particular, to real-time multitasking programs. Currently, real-time operating systems (called "operating systems" or "OS"), basic programs allowing several applications to coexist on the same machine and to facilitate their communication with the various peripherals, provide a mechanism preemptive scheduling to define a unit or quantum of processor time (also called "Central Processing Unit" or "CPU" in English) for each process or task (called "thread", "task" or

  "process" in English) active in the system.

  By quantum of time is meant the duration during which a process is executed by the processor. A quantum can be associated with each process, the duration of which depends on the scheduling of the operating system and the execution parameters of the process (scheduling is a function of real-time priorities, privilege levels, contexts of execution...). In periodic mode, the processor therefore devotes a time

  equal to this quantum for a given process.

  This mechanism makes it possible to guarantee a distribution of the resource of the processor to the various processes, without monopolization by one of them. The usual implementation (or "implementation") of this partition of time in quanta of time is based on the use of a time base available on the machine, such as a counter, or divider, of clock frequency (called "timer" in English) of the computer system which

  perform only the division or the counting of elementary time units.

  This division is programmable and the clock and the divider are external to the processor. The frequency at the output of this divider defines the minimum quantum of time or "grain" of the quantum of time, each quantum therefore being

an integer multiple of this grain.

  When the counter / divider reaches the zero value, an interruption of the processor is triggered, and the operating system becomes aware of the expiration of the programmed period. The occurrence of the interrupt allows the operating system to suspend the process by

  course and move on to running another process.

  A problem arises when we want to assign different quanta of time to different processes, and when we want to go up to a

  relatively high scheduling frequency.

  A first solution consists in definitively fixing the period of the clock frequency divider such that it defines a very small grain of quantum. Then, a process can be allocated a quantum of time made up of ten periods of exit from the divisor, while another process will be allocated fifteen. In fact, the scheduler can change the process only after ten interruptions for the first process and after fifteen

interruptions for the second.

  A problem of additional cost then appears: when the quantum of time is composed of several basic periods of the clock frequency divider, that is to say of several grains, only the last interruption effectively activates the scheduling. All previous interrupts occupy the processor only to count the total number of grains accumulated. Even if the processing time of the interruption remains low in front of the grain, this time is in any case a waste which affects the efficiency of the

computer system.

  Two other exclusive problems then appear. If the exit period of the divider is too high, a process may be assigned a much too large quantum with respect to the period to which the system must respond to external events, but if the period is too low, the cost of interrupt time (called "interrupt overhead" in English) is no longer negligible

  before the exit period of the divider.

  A second solution consists in modifying the exit period of the divider each time a process is scheduled. This method makes it possible to have a grain as fine as what the base period of the divider allows. In addition, a process is no longer interrupted unnecessarily. It is not until the expiration of the divider and the problem of the cost of downtime no longer exists. But, given the limited number of clock frequency dividers on a motherboard, the one used for process scheduling

  is used together to update an "absolute clock".

  The latter is referenced to each service of the operating system relating to time, such as a delay request ... The modification of the output frequency of this divider at each change of process, without disturbing the entire system makes this solution very complex,

even impractical.

  Document US Pat. No. 5,657,253 is known (Intel Corp.) which presents performance counters integrated into a processor. These counters are intended to be used by programmers to analyze the operation of a software being developed, so that the programmer can modify the source code of the software according to the observation authorized by these counters. The use of these counters is therefore not envisaged outside of the software development phase. Methods are known which ensure continuous adaptation

  of a program taking into account performance measures.

  In a first approach, an "adaptive" system consists of two distinct entities: (1) the program to be adapted and (2) an "adapter", monitoring and modifying the program in order to improve its performance. For example, in profile-driven optimization the role of the adapter is played by a compiler which takes as input not only the program to be compiled, but also traces of its executions previous. This type of compiler has already been proposed: - by DEC (registered trademark of Digital Equipment Corporation, in the United States of America) in the document "continuous profiling: where as ail the cycles gone?" de Anderson et al., DEC Systems Research Center and Western Research Lab, Proceedings of the 17th ACM Symposium on Operating Systems Principles, December 1997, pages 1 to 14, and - by article by Jeremy Brown, Andre DeHon, lan Eslick, Michelle Goldberg, Ahmed Shah, and Massimiliano Poletto "The C / ever Compiler: Proposai for a First-Cut Smart Compile / ', Transit Note 101, MIT Artificial

  Intelligence Laboratory, January 1994.

  In the DEC document, traces of past executions may contain including information from performance counters as in the current proposal. On the other hand, a principle limitation of this approach is that the flow of information passes in a single

  direction, from application to adapter.

  Thus, based on the trace information, the compiler makes the decision to rewrite the code of the application, without the latter being aware of it. The advantage is transparency compared to the application; on the other hand, an essential limitation is that the adapter can only have a limited understanding of the application and its intentions, therefore of the

  way to improve his behavior.

  In a second approach, an "adaptive" application plays both the role of the program to be adapted and of its own adapter. The adaptation cycle of such an application consists of three stages: introspection, decision-making and action. In the introspection stage, the adaptive application collects information on its own execution context or on its effectiveness. In the decision-making stage, this information is analyzed to determine a possible change in behavior, allowing it to be better adapted to the new context. The action step consists in applying the behavior change through an "action" on the application. Actions can involve changing the application settings, changing the resource management policy, or even modifying the application code itself. Among the many existing works, let us quote the adaptive file management system described by S.B. Lim, in "Adaptive caching in a distributed file system" Technical Report 1936, Department of Computer Sciences, University of Illinois at Urbana, Champaign, Urbana,

Illinois, 1995.

  However, to our knowledge there are no applications

  adaptive that use information internal to the processor.

  The application is therefore not aware of the use of resources at the lowest level of the target machine. The design of applications adapted to the most

  close to a particular material is therefore not described there.

  The invention intends to improve these various limitations of the prior art. To this end, the present invention aims, according to a first aspect, a method, characterized in that it comprises: - an operation of preloading at least one counter, by a first predetermined value, - a counting operation, by each said counter, of occurrences of a predetermined event internal to said processor, - an operation of comparing the value of each said counter with a second predetermined value associated with said counter, and, when one of said counters reaches said second predetermined value associated with it, an immediate modification operation

program execution.

  It is observed here that the operation for modifying the execution of a computer program concerns as well: a change in the context of the execution of the program, a change in the program (or process) executed, and

  - a modification of the code of this program.

  Thanks to these provisions, the execution of the program can immediately adapt to the number and nature of internal events counted. Not only among the events are, on the one hand, the processor cycle but also, on the other hand, other events internal to the processor. According to particular characteristics, during the operation of comparing the value of each said counter with a second predetermined value associated with said counter, the second predetermined value is equal to "0". As the return to zero of the counter is generally the subject of a particular signal from a counter integrated in an integrated circuit, the transition from said counter to said second predetermined value is easy to detect. According to particular characteristics, during the operation for counting occurrences of predetermined events, one of said counters counts clock pulses. Thanks to these provisions, a period before a change in program execution can be predetermined. According to other particular characteristics, during the counting operation of occurrences of predetermined events, counting events likely to delay the execution of a program, then, depending on the result of one or more operations counting, we carry out, in a deferred manner, a modification of the internal or external context of said program. Thanks to these provisions, the occurrence

  such events can be monitored and can be corrected.

  According to other particular characteristics, during the operation of preloading a counter, a said counter is a counter

  internal processor performance.

  Thanks to these provisions, counters already integrated in known type processors are used and are therefore of implementation

simple and inexpensive.

  According to other particular characteristics, during the preloading operation, the first predetermined value depends on the process, in a predetermined manner. Thanks to these provisions, each process can obtain a different number of event occurrences, for example a different execution time, which makes it possible to take account of the

  need resource of said process.

  According to other particular characteristics, during the preloading operation, the first predetermined value depends on a value given during the execution of said program. Thanks to these provisions, each process can obtain a number of event occurrences, for example a different execution time, which takes account of its immediate needs, which makes it possible to take account, practically in

  in real time, of the evolution of the resource requirement of said process.

  According to other particular characteristics - during the preloading operation of at least one counter, with a first predetermined value, at least two counters are preloaded with first predetermined values, and - during the counting operation , each counter counts the occurrences of a predetermined internal audit event

  processor, event associated with said counter.

  Thanks to these provisions, several numbers of occurrences of events can be simultaneously monitored to modify the execution.

of programs.

  According to other particular characteristics, said method comprises, preliminary to the preloading, counting, comparison and modification operations, an event selection operation during which an event internal to said processor is associated with each said counter. Thanks to these provisions, each type of event whose number of occurrences is monitored can be predefined depending on the application.

Implementation.

  According to particular characteristics, at least one counter counts the number of occurrences of clock pulses simultaneous with another event internal to said processor. Thanks to these provisions, the duration of said event is monitored to trigger a change in program execution. According to a second aspect, the present invention relates to a device for managing conditions of execution of a computer program, characterized in that it comprises: - at least one occurrence counter of at least one internal event, adapted to be preloaded by said processor, to a first predetermined value, - at least one means for detecting that a said counter reaches a second predetermined value, and - a processor adapted to immediately modify the execution of the program which it performs, when said detection means detects that said counter reaches the second predetermined value. The invention also relates to a computer, a camera, a fax machine, a camera, a television set, a printer, a scanner and an audio / video player, characterized in that they comprise a device such as

succinctly set out above.

  The invention also relates to: - a means of storing information readable by a computer or a microprocessor retaining instructions of a computer program characterized in that it allows the implementation of the method of the invention as briefly described above, and - a removable information storage means, partially or totally, and readable by a computer or a microprocessor keeping instructions of a computer program characterized in that it allows the setting

  implementing the process of the invention as succinctly set out below

  above. The preferential or particular characteristics, and the advantages of this device, this computer, this camera, this fax machine, this photographic device, this television set, this printer, this scanner, this audio / video player and these information storage means being identical to those of the method such as

  succinctly explained above, these advantages are not recalled here.

  The invention will be better understood on reading the description which

  will follow, made with reference to the appended drawings in which: - Figure 1 shows schematically a device according to the present invention, Figure 2 shows schematically a part of the internal structure of a processor incorporated in the device illustrated in Figure 1, and - Figure 3 shows a schematic flowchart of operation of the device illustrated in Figures 1 and 2. In Figure 1, a device according to the present invention is illustrated as a block diagram and shown under general reference 10. It comprises, interconnected by an address and data bus 102: - an Intel Pentium P6 processor (registered trademarks) 106; - a clock frequency divider 109 - a random access memory RAM 104; - ROM 105; an input / output port 103 used to transmit and receive signals to or from, respectively, a network 107; - a display screen 108; a keyboard 101 providing bytes representative of the keyboard keys successively used; and a mass memory 110, for example consisting of a disk

hard.

  Each of the elements illustrated in Figure 1 is well known to those skilled in the art of transmission systems and, more generally, information processing systems. These elements are therefore not described here.

  We observe here that the words "memory segment" used above

  below designate, in each of the memories, both a low-capacity memory zone (keeping only a few binary data) and a large-capacity memory zone (used to store a

whole program).

  The random access memory 104 stores data, variables and intermediate processing results, in memory segments carrying,

  in the following description, the same names as the data they

  keep the values. The random access memory 104 comprises in particular: - a memory segment "stack A" in which a context for executing a task referenced "A" is kept, - a memory segment "stack B" in which a context d execution of a task referenced "B", - a segment of memory "code" in which the

  code of the program implemented by the processor 106.

  The RAM 104 constitutes a means of storing information readable by a computer or a microprocessor. It retains instructions from a computer program that allows the implementation of the

  coding method object of the invention.

  According to a variant, the random access memory 104 is removable, partially or totally, and comprises, for example a magnetic strip,

  a rewritable floppy or compact disc.

  The read-only memory 105 retains software allowing the

device started correctly.

  FIG. 2 represents a part of the internal structure of a processor 106 known at the date of the present invention, the Intel processor

Pentium P6 (registered trademarks).

  BRIEF DESCRIPTION OF THE EMBODIMENT

  In this processor 106, there are two counters 201 and 202 which can store the number of occurrences of certain events. Among these, there are, for example: - an event relating to machine cycles. Unlike all other events, this one is a variable directly proportional to time since the associated counter is incremented at each clock cycle; an event corresponding to the number of instructions executed, which is not proportional to the time elapsed, since the processor 106 can execute several instructions in a clock cycle as it can take several clock cycles to execute a single instruction, depending on the complexity of this instruction; - an event corresponding to a conditional jump prediction which failed ("miss predicted branches" in English); and - an event corresponding to access to missing data

of the cache ("cache miss" in English).

  In addition, it is possible to control the incrementation of each counter as a function of the execution context of the processor 106. Indeed, each counter can be configured in such a way that it is only incremented during, on the one hand, The execution of the user code, and, on the other hand, the execution of the code relating to the user code. This technique makes it possible not to count, on the quantum of time of a process, the time

  execution of independent interrupts of this process.

  Then, a counter can generate an interrupt when it returns to zero (zero crossing known to those skilled in the art under the English name of "overflow", which means "overflow"). This interruption is taken into account by an internal programmable interrupt controller 203 (called "APIC" for "Advanced Programmable Interrupt Controler",

  in English) which causes an interruption of the processor 106.

  Initially intended to facilitate communication between the various processors in a multiprocessor architecture, the internal controller APIC 203 integrates, in addition, an external interrupt controller and some functionalities vis-à-vis internal events (interruptions

  communication errors with another APIC, ...).

  As each counter, 201 or 202, can be initialized with a first predetermined value, it is possible to define the number of occurrences of the event before the generation of the interrupt, this number being the complement of the first predetermined value to a second

  predetermined value, here equal to 232.

  In the embodiment described and shown, the invention consists in using this type of internal counter as a clock cycle counter and an internal interrupt generation when the counter 201 is reset to zero, to obtain a system : * with variable quantum: it is enough to write different values in the counter before scheduling to define different quanta attributed to the scheduled processes, * without overload of interruptions: a single interruption is generated to trigger the scheduling, with a cost minimum scheduling interruption: the interruption remains internal to processor 106, * without disturbing the rest of the system: the output period of the motherboard clock frequency divider is not altered. Thanks to the various events managed by the Pentium processor, this preemptive scheduling technique, commonly based

  over a period of time, can be extended to other pre-emption criteria.

  For example, the operating system can use the second counter to count the number of cycles during which interrupts are inhibited and an interrupt is pending. Thus, the process will not necessarily be preempted because of the end of the temporal quantum, but because it has abused the time for blocking interruptions while a device was waiting

to be served.

  DETAILED DESCRIPTION OF THE EMBODIMENT

  The Intel Pentium P6 processor (registered trademarks) contains two counters 201 and 202 respectively called "PerfCtrO" "PerfCtrl" and two registers 204 and 205 for controlling these counters, registers called "EvntSeIO" and "EvntSeil", residing in the specific registers machine (called "MSRs" for "Machine Specific Registers", in English). Specific to Intel architecture, these registers are defined for a particular version of a

Pentium processor.

  The addresses of these registers are given in the following table: Address Register 201 EvntSe0l 0x186 202: EvntSeil 0x187 204: PerfCtr0 0xC1 205: PerfCtrl 0xC2 To measure the execution time with the counter 201 "EvntSelO", the processor therefore writes the number "0x79" in register 204 "PerfCtrO", since the event used to measure the execution time is the number "0x79", defined in the Intel documentation as the number of

  cycles during which the processor is not stopped.

  However, the processor 106 is in the "stopped" state when an "HLT" instruction is executed. When processor 106 encounters this instruction, it stops until an external interrupt (if they are not masked), a non maskable interrupt ("NMI" for "No Maskable Interrupt" in English) or a reset to zero ("RESET" in English) appears. In addition, this "HLT" instruction is part of the privileged instructions, that is to say that only the operating system can execute it without generating a general protection exception. In conclusion, this "HLT" instruction cannot be found in user code and therefore this code cannot stop the processor. We can therefore consider that the event "0x79" therefore corresponds exactly to the number of

  cycles consumed by the user code.

  The current privilege level ("CPL" for "Current Privilege Level") is a concept specific to the Intel architecture, it fixes the level of protection in which code is executed. Although there are four levels, from 0 (level in which the code has the most privilege, therefore has the right to do the most things) to 3 (least privileged level), level 0 is generally called supervisor level or core, and levels 1 to 3 the user levels. This architecture allows to run the system kernel

  operating level 0, and the various applications at user level.

  The control registers 204 and 205 make it possible in particular to specify: the event to be measured by each counter, if this event must be taken into account during the execution of the non-supervisor code ("CPL" between 1 and 3), if this event must be taken into account when executing the supervisor code ("CPL" equal to 0), if an interrupt must be generated when the counter

goes back to zero.

  In the case of an operating system in which: - the service routines for the user are at privilege level 1 or 2, and - the routines asynchronous to the execution of the user code ("user" in English) (including the scheduler) at level 0, it is possible to count even more easily the duration of execution of a process: it suffices to specify that the incrementation of the counter only takes place

  when the code executed is not at level 0.

  Component 207 "LOGIC" includes well-known combinational logic components, such as logic gates, which select for

  each counter the CPL values to consider.

  The multiplexer component 208 selects, for each counter, the event to be considered. The processor 106 is programmed to implement the flow diagram illustrated in FIG. 3. First, the processor 106 performs an initialization operation 301, which comprises: the establishment of the operating system, in a known manner, -the start of the software, in a well known manner, and - the selection of the internal event which will be counted by the

  counter 201, as indicated above.

  This event is, in the example described and represented, the

  occurrence of a processor cycle.

  Then, the processor 106 performs an operation 302 of preloading the counter 201 with a value such that the complement of this number to 232 is equal to the number of occurrences of the internal event considered, which one wishes to count before changing process or process context.

  Then, during an operation 303, a process is executed and the counter 201 counts the number of occurrences of the event which has been associated with it, that is to say at each occurrence of this associated event , it increments its value by 1. Then, during an operation 304, an interruption is triggered by the APIC 203, as soon as the counter 201 returns to the value "0". As soon as the interrupt is received, the processor changes the running process or changes the context of the running process,

during an operation 305.

  Then, operation 302 is repeated.

  It is observed here that a counted event may as well be one of the events presented in the documentation of the processor considered, as a logical combination of these events (with logical functions such as "and", ...). Thus, each clock cycle occurring during an event internal to the processor constitutes a new event internal to the processor. It is also observed that the presence of two counters makes it possible to assign to each counter a particular event, during initialization 301, each counter then being preloaded individually with a first particular predetermined value during the operation.

  302 and the first counter going back to zero triggering the interruption 304.

  According to a variant not shown, each process is associated with a first predetermined value which is specific to it. In this variant, during operation 302, the processor preloads the counter 201 to a first predetermined value which depends on the process which will be executed during operation 303. More generally, all the scheduling modes known previously to the present invention and which dynamically modify the quanta allocated to each process, benefit from the present invention, since it is no longer necessary thanks to it to multiply the interruptions corresponding to the grain of these quanta to measure

their duration.

  According to another variant not shown, each process is associated with a first predetermined value which is specific to it, according to the needs expressed by the process. For example, a process which knows that it will need a large part of the processor resource indicates, at a predetermined address of the random access memory 104, a first predetermined value called "required" which corresponds to its need. During the operation 302, the processor 106 then performs a preloading of the counter 201 with this first required predetermined value, or with a first value which depends on it, according to the needs of the other processes,

  and the qualities of service attributed to them.

  According to another variant not shown: - during the initialization operation 301, the events counted by the counter 201 are other events than clock pulses and - the operation 305 comprises other steps than the change of process or change of context. Thus, for example, if the event considered relates to a predetermined operation which is costly in processing time, such as systematic access to an address whose data is not in the cache memory, the operation for immediate modification of program execution may include an operation to correct this defect, for example by preloading memory areas intended to be used by said operation. Alternatively, a person skilled in the art uses the access to internal events that the invention allows him to improve, in a manner known per se, the

  adaptive programming described above.

  More generally, the operation 305 comprises an immediate modification of program execution, and comprises, for example comprises: - at least one change of context for the execution of the program, - at least one change of process executed and / or

  - at least one modification of the code for this program.

  According to a variant, the second predetermined value which triggers the immediate modification of program execution is initialized during the preloading operation 302, in a comparator which continuously performs the comparison of the value of the counter with the second predetermined value and triggers the immediate modification of program execution as soon as these values are equal, during

operation 304.

Claims (34)

  1. Method, characterized in that it comprises: - a preloading operation (302) of at least one counter (201, 202), by a first predetermined value, - a counting operation (303), by each said counter, of occurrences of a predetermined event internal to said processor, - a comparison operation (304) of the value of each said counter with a second predetermined value associated with said counter, and, when one of said counters reaches said second value associated with it, an immediate modification operation program execution (305).   2. Method according to claim 1, characterized in that said immediate modification operation of program execution comprises at   minus a change in context for program execution.   3. Method according to any one of claims 1 or 2,   characterized in that said immediate modification operation of execution of   program includes at least one process change executed.   4. Method according to any one of claims 1 to 3,   characterized in that said immediate modification operation of execution of   program includes at least one modification to the code for that program.   5. Method according to any one of claims 1 to 4,   characterized in that, during the comparison operation (304) of the value of each said counter with a second predetermined value   associated with said counter, the second predetermined value is equal to "0".   6. Method according to any one of claims 1 to 5,   characterized in that, during the counting operation of occurrences of predetermined events (303), one of said counters counts down clock pulses.   7. Method according to any one of claims 1 to 6,   characterized in that, during the counting operation of occurrences of predetermined events (303), counting events likely to delay the execution of a program, then, depending on the result of one or more counting operations, a deferred   modification of the internal or external context of said program.   8. Method according to any one of claims 1 to 7,   characterized in that, during the operation of preloading a counter (302), a said counter is a performance counter internal to a processor.   9. Method according to any one of claims 1 to 8,   characterized in that, during the preloading operation (302), the first predetermined value depends on the process, in a predetermined manner.   10. Method according to any one of claims 1 to 9,   characterized in that, during the preloading operation (302), the first predetermined value depends on a value given during the execution of said program.   11. Method according to any one of claims 1 to 10,   characterized in that: - during the preloading operation of at least one counter (302), with a first predetermined value, at least two counters (201, 202) are preloaded with first predetermined values, and - at during the counting operation (303), each counter counts the occurrences of a predetermined internal audit event   processor, event associated with said counter.   12. Method according to any one of claims 1 to 11,   characterized in that it comprises, preliminary to the preloading (302), counting (303), comparison (304) and modification (305) operations, an event selection operation (301) during which associates with each said counter an event internal to said processor.   13. Method according to any one of claims 1 to 12,   characterized in that at least one counter (201) counts the number of occurrences of clock pulses simultaneous with another internal event audit processor.   14. Device, characterized in that it comprises: - a processor (106) adapted to preload at least one counter (201, 202), by a first predetermined value, - to count down, by each said counter an internal predetermined event to said processor, - to compare the value of each said counter with a second predetermined value associated with said counter, and, when one of said counters reaches said second predetermined value associated with it, to immediately modify the execution of the program. 15. Device according to claim 14, characterized in that said processor (106) is adapted to immediately modify the execution of the program by changing, at least, the context of the execution of the program,   16. Device according to any one of claims 14 or 15,   characterized in that said processor (106) is adapted to immediately modify program execution by changing, at least, the process executed.   17. Device according to any one of claims 14 to 16,   characterized in that said processor (106) is adapted to immediately modify the program execution by modifying, at least, code of This program.   18. Device according to any one of claims 14 to 17,   characterized in that said processor (106) is adapted so that the second   predetermined value is equal to "0".   19. Device according to any one of claims 14 to 18,   characterized in that said processor (106) is adapted to count down, to   one of said counters (201,202), clock pulses.   20. Device according to any one of claims 14 to 19,   characterized in that said processor (106) is adapted to count down, at one of said counters (201, 202), events liable to delay the execution of a program, then, according to the result of one or more several counting operations, to modify the internal or external context of said program.   21. Device according to any one of claims 14 to 20,   characterized in that at least one said counter (201, 202) is a counter for performance of said processor (106).   22. Device according to any one of claims 14 to 21,   characterized in that the processor (106) is adapted to preload a said counter (201, 202) to a first predetermined value depending on the   process, in a predetermined way.   23. Device according to any one of claims 14 to 22,   characterized in that the processor (106) is adapted to preload a said counter (201, 202) to a first predetermined value depending on a   value given during the execution of said program.   24. Device according to any one of claims 14 to 23,   characterized in that: - the processor (106) is adapted to preload at least two counters (201, 202) with first predetermined values, and - each counter is adapted to count occurrences of a predetermined event internal to said processor, event audit associate counter.   25. Device according to any one of claims 14 to 24,   characterized in that the processor (106) is adapted, before preloading each counter (201, 202) and modifying the execution, in selecting at least one event internal to said processor, event whose occurrences are counted by said counter.   26. Device according to any one of claims 14 to 25,   characterized in that the processor (106) is adapted so that at least one said counter counts the number of occurrences of clock pulses   simultaneous with another internal event of said processor.   27. Computer, characterized in that it comprises a device according to   any one of claims 14 to 26.   28. Camera, characterized in that it comprises a device for   management according to any one of claims 14 to 26.   29. Fax machine, characterized in that it includes a device for   management according to any one of claims 14 to 26.   30. Photographic camera, characterized in that it comprises a   management device according to any one of claims 14 to 26.   31. Television, characterized in that it includes a device for   management according to any one of claims 14 to 26.   32. Printer, characterized in that it includes a device for   management according to any one of claims 14 to 26.   33. Scanner, characterized in that it includes a device for   management according to any one of claims 14 to 26.   34. Audio / video player, characterized in that it includes a   management device according to any one of claims 14 to 26.