FR2777990A1 - COHERENT READING DEVICE OF AN ABSOLUTE ENCODER OR A MEASURING DEVICE WITH PARALLEL OUTPUTS - Google Patents

Abstract

The present invention relates to a device for coherent reading of an absolute encoder or of a measurement device delivering, on a plurality of parallel outputs (S0, S1, ... Sn) of transistor type (Tn) or other, as many binary signals (D0, D1, Dn) shaped by an interface (2), characterized in that it comprises a plurality of filters (F0 to Fn) each receiving an output bit from the interface (2) and delivering signals to a memory circuit (32) whose outputs (Q0 to Qn) form a binary word representative of the position and the means (O0 to On, 31) to validate the memory circuit (32), if each bit is identical filter inlet and outlet.

Description

The present invention relates to a device for reading signals

  binaries from, via a formatting interface circuit, an absolute encoder or device

  measuring devices having a plurality of parallel outputs.

  An absolute encoder consists of an encoder disc on which are arranged concentric tracks (angular encoder) scanned optically. An optical reading device simultaneously scans all the tracks of the encoder disc. Depending on whether a transparent or opaque area is on the light flux of the reading device, the encoder delivers a logic signal "1" or "0". On any radius, the succession of opaque and transparent areas constitutes the binary representation of the angle made by the disc with a known origin. Thus for each position, the coder delivers a binary coded word consisting of a certain number of bits. The n bits of the code correspond to the n tracks and are directly accessible on the parallel outputs. The number of parallel outputs or channels is therefore equal to the number of tracks. The code of the word thus generated can be binary code, binary bcd code ("binary coded decimal"), reflected binary code or code "Gray">,

etc ...

  When changing from one value to another consecutive value, several bits change state simultaneously. The encoder can deliver, for a very short time, an incorrect word and therefore detect an incorrect position. In general, the encoder provides an inhibition signal which warns whether the position value is stable or not at the output of the encoder. But if coders with transistor outputs and open collectors are used, new dispersions between the bit state changes between conduction and blocking of the transistors appear, and become more pronounced, as soon as the distance between the coder and

the word reading organ grows.

  The object of the present invention is to provide a coherent reading of the binary word originating from the parallel outputs of an absolute encoder, not requiring the use of the inhibition signal and overcoming the dispersions between the changes of bit states,

  regardless of the distance between the outputs and the reading device.

  The device according to the invention is essentially characterized in that it comprises a plurality of filters each receiving an output bit from the interface and delivering signals to a memory circuit whose outputs form a binary word representative of the position and means for validating the memory circuit, if each bit is identical at the input

and at the filter outlet.

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  According to one characteristic, the input and output of each filtering circuit are sent to an exclusive OR circuit, the outputs of the exclusive OR being injected via an OR circuit on an input for enabling the memory circuit so as to authorize the reading of the word on the outputs of the memory circuit when the acquisition authorizations of all the bits are given. According to another characteristic, the encoder interface comprises, for each output, a comparator-type circuit performing the comparison of the voltage delivered by the output

  of the encoder with a reference value and delivering a bit on its "data" output.

  The device is particularly applicable to an encoder or measuring device with parallel outputs having an unreflected code o two or more bits change state simultaneously. The invention will now be described in more detail with reference to an embodiment given by way of example and illustrated by the appended drawings in which: - Figure 1 is an overall view showing the absolute encoder and the associated coherent reading device according to the invention; - Figure 2 is a detail view showing a transistor output of the encoder and the associated interface;

  FIG. 3 illustrates the operation of the filtering circuits.

  The absolute encoder, marked 1 in Figures 1 and 2, consists of a disc

  encoder on which are concentric tracks scanned optically.

  The optical reading device simultaneously scans all the tracks on the encoder disc. Depending on whether a transparent or opaque area is on the light flux of the reading device, the encoder delivers a logic signal "1" or "0". On any radius, the succession of opaque and transparent areas constitutes the binary representation of the angle made by the disc with a known origin. The n bits of the code correspond to the n tracks and are directly accessible on the parallel outputs SO to Sn. The number of parallel outputs

  or tracks is therefore equal to the number of tracks.

  Each output of the encoder is an open collector transistor. The signals delivered on the parallel outputs SO to Sn are injected on an encoder interface 2 which formats

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  each signal from an output. For simplification, in Figure 2, a single transistor Tn is shown. The collector of the transistor, Tn for example, is sent to a load resistance Rn of the interface and to a circuit Cn of comparator type delivering a bit ("O" or "1">) on its "data" output DO to Dn depending on whether the input voltage "ve" is higher or lower than

a reference value "vref".

  The distance between each transistor such as Tn and its load resistance such as Rn varies according to the long ur and the type of wiring of the user. The dispersion between the conduction time and the blocking time of each transistor varies due to the fact that the parasitic line capacitance of the cable marked C generates a delay time which can be significant at the charge (transistor blocking) with respect to its discharge. (transistor conduction). The encoder according to the invention is associated with a coherent reading circuit 3 which authorizes the definitive reading of the word, if and only if the states of all the bits at the output of

the encoder interface 2 are stable.

  Each bit of an output DO to Dn of the encoder interface is sent to a filtering circuit F0 to Fn. Each of these filter circuits consists of a series of flip-flops sequenced by a clock. The filtering time tF (F0, Fl, ... Fn) must be set so

  that it includes all the delays between the outputs DO a Dn of the encoder interface (Fig. 3).

  The input and output of each filter circuit are sent to an Or circuit

exclusive marked O0 to On.

  Each bit of an output DO to Dn of a filtering circuit is sent to a circuit

  memory 32 whose outputs Q0 to Qn define the binary word representative of the position.

  The outputs of the exclusive OR circuits O0 to On are injected via an OR circuit 31

  on a validation input G of the memory circuit 32.

  The operation is as follows: The outputs of the various exclusive circuits Oo to On are in the same state if, on

  each of the filters, the state at the input of the filter is identical to the state at the output of the filter.

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  The final acquisition of the binary word read on the outputs of memory circuit 32 is given

  when the acquisition permissions for all bits are given.

  It is understood that it is possible, without departing from the scope of the invention, to imagine variants and improvements in detail and even to envisage the use of equivalent means.

2777990

Claims (4)

Claims   1. Consistent reading device of an absolute encoder or of a measuring device delivering, on a plurality of parallel outputs (S0, S1, ... Sn) of transistor type (Tn) or other, as many binary signals ( DO, D1, Dn) formed by an interface (2), characterized in that it comprises a plurality of filters (F0 to Fn) each receiving an output bit from the interface (2) and delivering signals to a memory circuit (32) whose outputs (Q0 to Qn) form a binary word representative of the position and of the means (O0 to On, 31) for validating the memory circuit (32), if each bit is identical at the input and out of filtered.   2. Reading device according to claim 1, characterized in that the input and output of each filtering circuit (F0 to Fn) are sent to an exclusive Or circuit (O0 to On), the outputs of the exclusive Or ( O0 to On) being injected via an OR circuit (31) on a validation input (G) of the memory circuit (32) so as to authorize the reading of the word on the outputs of the memory circuit (32) when the acquisition authorizations of all bits are given. 3. Reading device according to claim 1 or 2, characterized in that the encoder interface (2) comprises, for each output, a circuit (C0, .. Cn) of comparator type performing the comparison of the voltage (ve ) delivered by the encoder output   with a reference value (vref) and delivering a bit on its "data" output (D0, .. Dn).   4. Application of the device according to any one of the preceding claims,   characterized by the fact that the encoder or the measuring device with parallel outputs delivers a code   not reflected o two or more bits change state simultaneously.