FR2762730A1 - Rapid transfer data coder/decoder of digital data - Google Patents

Abstract

The device includes a memory (1) storing digital information and being connected to a data processing device (10) via a bus line. The memory can be accessed by a bidirectional circuit (2) with two channels: one for emission and the other for reception. A FIFO buffer memory (3) is inserted along the emission channel. The buffer memory is connected to an error correcting circuit (4) which applies the Viterbo algorithm. The reception channel is connected to a decoding circuit (7) linked to a second FIFO buffer memory (6).

Description

 The present invention relates generally to the coding and decoding of digital data, and relates more particularly to the transfer of data between a memory and a coding circuit or a data decoding circuit.

 In most cases of data transmission between a transmitting device and a receiving device, it is necessary to code the data before the transmitter transmits it, and correspondingly to decode it after the receiver has received it. The purpose of coding, for example, is to minimize transmission errors due to noise coming to corrupt the transmitted data, or for the purpose of encrypting the transmitted data.

 The type of coding envisaged here consists in increasing the total number of data to be transmitted, by adding coding data to the data initially to be transmitted, or useful data.

 A coding circuit processes the useful data by block to code them, a block comprising for example a few tens of bytes. The coding circuit needs input blocks of data to be coded separated from each other by padding blocks. The coding circuit replaces the padding blocks with coding data blocks. The coding circuit produces successive frames each comprising a useful data block formed of a certain number of useful data words, and a coding data block formed of a certain number of coding data words.

 On reception, the coding data must be separated from the useful data. The coding data are used to decode the useful data, for example by correcting possible transmission errors, or by decrypting the useful data. These can then be stored, for example.

 The decoding circuit therefore produces successive blocks of useful data.

 On the other hand, more and more devices use a direct access circuit to transfer data between two internal circuits. A direct access circuit allows faster transfers than a processor and does not monopolize the processor.

 To make the best use of a direct access circuit, that is to say to carry out rapid data transfers, it is necessary to carry out a continuous transfer of a "stream" of data. However, as specified above, the coding circuit needs at the input of data blocks to be coded separated from each other by padding blocks. There is therefore an incompatibility between the fact of transferring the data by continuous stream, and providing useful data by block, with interruption between the blocks.

 Indeed, the transmission of successive small blocks of data by means of a direct access circuit eliminates the advantage of the latter, since it would then be necessary to reprogram the direct access circuit for each block transmitted.

 To transfer data between a memory and a coding circuit as envisaged here, it is therefore not realistic to carry out successive transfers of blocks containing the number of useful data words for each of the frames to be formed.

 To carry out a continuous transfer of a large number of words of useful data between the memory and the coding circuit, it can be envisaged to include non-significant words after each block of useful data, prior to the transfer. When coding, these non-significant words will be replaced by the coding words. However, this leads to memorizing the non-significant words with the useful data words, and therefore a large memory space is required.

 Similarly, after decoding, in order to carry out a continuous transfer of a large number of data words to the memory, it may be envisaged to transmit the coding words with the useful data words. Again1 this leads to the use of a large memory space, by memorizing the coding words which then no longer have a function.

 As well for coding as for decoding, the memory is badly used, since it contains insignificant words or coding words, in addition to the useful data.

 Thus, the transfer of data between a memory and a coding or decoding circuit by means of a direct access circuit, leads to using either the direct access circuit or the memory in a non-optimal manner.

 The object of the invention is to make the use of a coding circuit or of a decoding circuit compatible with a direct access circuit, and to allow rapid transfer of data between a memory and a coding circuit or a decoding circuit, while allowing optimal use of the memory.

To this end, the invention proposes a device for coding data extracted from a main memory, the data being in the form of useful data words, comprising:
a means of direct access to the main memory for extracting the data to be coded,
a means of coding the extracted data, by the formation of groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, the additional words being determined by the coding means,
characterized in that it comprises:
a first buffer memory means connected between the direct access means and the coding means, said buffer memory means receiving the extracted data, and
a means for controlling the transfer of data between the first buffer memory means and the coding means, adapted to successively control a transfer of the first predetermined number of useful data words, and an interruption of the transfer of the data words for a duration of interruption corresponding to the duration which would be necessary to transfer the second predetermined number of additional words.

The invention also provides a data coding device, adapted to cooperate with:
a main memory containing the data to be coded, the data being in the form of useful data words,
a means of direct access to the main memory for extracting the data to be coded,
and comprising:
a means of coding the extracted data, by the formation of groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, the additional words being determined by the coding means,
characterized in that it comprises:
a first buffer memory means connected between the direct access means and the coding means, said buffer memory means receiving the extracted data, and
a means for controlling the transfer of data between the first buffer memory means and the coding means, adapted to successively control a transfer of the first predetermined number of useful data words and an interruption of the transfer of the data words for a duration d 'interruption corresponding to the duration which would be necessary to transfer the second predetermined number of additional words.

Correlatively, the invention proposes a method of coding data extracted from a main memory, the data being in the form of useful data words, comprising the step of:
coding of the extracted data, by coding means forming groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, the additional words being determined by coding,
characterized in that it comprises the steps of:
storage of the data extracted in a first buffer memory means, prior to coding, and
control of a transfer of the first predetermined number of useful data words between the first buffer memory means and the coding means, and successively of an interruption of the transfer of the data words during an interruption duration corresponding to the duration which would be required to transfer the second predetermined number of additional words.

 The coding device and method according to the invention allow rapid data transfer between the main memory and the coding circuit, by means of the direct access circuit, while storing only the useful data in the main memory.

 Thus, the main memory and the direct access circuit are both optimally used, thanks to the use of a buffer memory between the direct access means and the coding means, and to the appropriate control of the data transfers between the buffer memory and the coding means.

 According to a preferred characteristic, the control means is adapted to control the transfer of data between the main memory and the first buffer memory means, via the direct access means.

 The transfer of data between the main memory and the buffer memory is a rapid transfer of a large number of useful data, while the transfer of data between the buffer memory and the coding means is a transfer of successive blocks of data words. each containing a smaller number of useful data words.

 According to another preferred characteristic, a data transmission means is connected at the output of the coding means, and the control means is adapted to control the transfer of data between the coding means and the transmission means. Indeed, data coding applies more particularly to the transmission of data, for example by radio transmission.

The invention also relates to a device for decoding coded data in the form of groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, comprising:
a means for decoding the coded data, to supply the first predetermined number of useful data words from each of the groups of words,
a main memory for storing the useful data words supplied by the decoding means,
a means of direct access to the main memory for entering the useful data words therein,
characterized in that it comprises:
a second buffer memory means connected between the decoding means and the direct access means, and
a means for controlling the transfer of data between the decoding means and the second buffer memory means, adapted to successively control a transfer of the first predetermined number of useful data words, and an interruption of the transfer of the data words for a duration of interruption corresponding to the duration which would be necessary to transfer the second predetermined number of additional words.

The invention also relates to a device for decoding data coded in the form of groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, comprising:
a means for decoding the coded data, to supply the first predetermined number of useful data words from each of the groups of words,
and adapted to cooperate with:
a main memory for storing the useful data words supplied by the decoding means,
a means of direct access to the main memory for entering the useful data words therein,
characterized in that it comprises:
a second buffer memory means connected between the decoding means and the direct access means, and
a means for controlling the transfer of data between the decoding means and the second buffer memory means, adapted to successively control a transfer of the first predetermined number of useful data words, and an interruption of the transfer of the data words for a duration of interruption corresponding to the duration which would be necessary to transfer the second predetermined number of additional words.

Correlatively, the invention relates to a method for decoding coded data in the form of groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, comprising the steps of:
- decoding of the coded data, by a decoding means supplying the first predetermined number of useful data words from each of the groups of words,
- memorization of the useful data words supplied by the decoding means,
characterized in that it comprises the steps of:
storage of the decoded data in a second buffer memory means, and
control of a transfer of the first predetermined number of useful data words between the decoding means and the second buffer memory means, and successively of an interruption of the transfer of the data words during an interruption duration corresponding to the duration which would be required to transfer the second predetermined number of additional words.

 The advantages offered by the invention for the transfer of data between the decoding means and the main memory are similar to those explained above.

According to preferred characteristics:
- The control means is adapted to control the transfer of data between the second buffer memory means and the main memory, via the direct access circuit.

 - A data reception means is connected at the input of the decoding means, and the control means is adapted to control the transfer of data between the data reception means and the decoding means.

The characteristics and advantages of the present invention will appear more clearly on reading several embodiments illustrated by the attached drawings, in which:
FIG. 1 is a block diagram of a transmission and reception device according to the invention,
FIG. 2 represents an error correction code word formed in the device of FIG. 1,
FIGS. 3a to 3c represent sequences of bytes passing through the device of FIG. 1,
FIG. 4 represents the control signals and the status signals used in the device of FIG. 1,
FIGS. 5 to 7 represent data transfer algorithms for transmitting data, and
- Figures 8 to 10 show data transfer algorithms for receiving data.

 In the embodiment chosen and shown in FIG. 1, a data transmission and reception device comprises a main memory 1 in which data are stored. The data transmission and reception device is connected, via the memory 1, to a data processing device 10, known per se. The device 10 can be a computer, or a processing terminal, linked by a data bus to the memory 1. The data transmission and reception device can also be integrated into a data processing device, such as a computer, and the memory 1 is then connected to a data processing circuit internal to the computer.

 The main memory 1 is connected to a circuit 2 for direct access to the main memory 1, called the DMA circuit (Direct Access Memory) which allows bidirectional, direct access to the main memory 1. The circuit 2 here uses two channels so monodirectional, which form a transmission channel and a reception channel. This circuit has the advantage of allowing very rapid access to the main memory 1.

First of all in the transmission direction, the direct access circuit 2 is connected to a buffer memory 3 of FIFO (First In, First Out) type, itself connected to a data coding circuit, here a error correction 4. The error correction circuit 4 is a FEC (Forward Error Correction) circuit which codes the data to be transmitted, according to a VITERBI type algorithm, suitable when the errors are not grouped, or according to an algorithm REED type
SOLOMON, suitable for packet errors. This latter type of error correction will be more particularly considered and detailed below.

 The error correction circuit 4 is connected to a transmission circuit 5 which transmits the data on a transmission channel.

 The error correction circuit 4 receives data in the form of a series of words, for example bytes, forming a useful message and receives filling data, in the form of words, here filling bytes1.

 The error correction circuit 4 thus receives N bytes of useful data followed by K padding bytes, where N is an integer worth 26 by way of example and K is an integer worth 6 by way of example. Every N bytes received, circuit 4 replaces the K filling bytes with K redundancy bytes. The N useful bytes OC, to OCN and the K redundancy bytes OR, to ORK form a word MC of error correction code as shown in FIG. 2. The K redundancy bytes OR, to ORK are determined by the circuit error correction 4, according to a Reed-Solomon algorithm, to correct K / 2 possible errors in the error correction code word.

 On the other hand, in the receiving direction, a receiving circuit 8 receives data from the transmission channel. The reception circuit 8 is connected to a data decoding circuit, here an error correction circuit 7. The error correction circuit 7 is connected to a buffer memory 6 of FIFO type, analogous to the buffer memory 3 The buffer memory 6 is connected to the direct access circuit 2, itself connected to the main memory 1.

 The error correction circuit 7 generally performs reverse decoding operations of the coding operations of the circuit 4. The error correction circuit 7 receives error correction code words MC comprising N useful bytes OC1 to OCN and K bytes of redundancy OR to ORK.

Circuit 7 uses the K redundancy bytes to detect and correct possible errors in the words received. Decoding results in decoded words containing the N bytes of useful message, possibly corrected by means of the redundancy bytes, and K bytes of redundancy OR, in ORK no longer having a role.

 The circuit 7 transfers the decoded words to the buffer memory 6, in order to store the useful message bytes OC, to OCN in the main memory 1.

 A control automaton 9 is connected to the direct access circuit 2, to the buffer memories 3 and 6 and to the error correction circuits 4 and 7, as will be detailed below.

 The coding and decoding operations performed by the error correction circuits 4 and 7 are illustrated in FIGS. 3a to 3c.

 FIG. 3a schematically represents a series of bytes useful at the input or output of the main memory 1. FIG. 3b represents the series of bytes at the input of the error correction circuit 4. This series comprises an alternation of N bytes useful OC to OCN and K padding bytes Or to OrK. FIG. 3c represents the sequence of bytes at the output of the error correction circuit 4 or at the input, or at the output, of the error correction circuit 7. This sequence comprises an alternation of N useful bytes OC1 to OCN and of K redundancy bytes ORr to ORK. The K redundancy bytes are determined on transmission by the error correction circuit 4 which inserts them in place of the filling bytes.

 According to other embodiments, the coding circuit is a data encryption circuit. The coding circuit then inserts a key formed by a certain number of bytes following each of blocks of coded useful data. The corresponding decoding circuit uses the key to decode the block of coded useful data. Other types of codec coding can be used in the context of the invention.

 FIG. 4 represents a block diagram of the logic signals exchanged between the control automaton 9 and the direct access circuit 2, the buffer memories 3 and 6, and the error correction circuits 4 and 7. Some of these signals control the data transfers between the main memory 1 and the transmission 5 and reception 8 circuits, as well as the operation of the circuits involved in the transmission and reception of data. Others of these signals represent operating states of the various circuits, relative to data transfer.

 The control automaton 9 receives signals DEME and DEMR from circuits 5 and 8, respectively. The DEME signal is an authorization to transmit data when it goes high. The signal DEMR indicates that a reception of data is detected by the circuit 8 when it goes high.

 The control automaton 9 transmits DCE and DCR signals to the direct access circuit 2. The DCE signal is a request for a direct access channel for a data transmission, between the main memory 1 and the buffer memory 3, when 'it goes high. The DCR signal is a request for a direct access channel for receiving data, between the memory 6 and the main memory 1, when it goes high.

 The direct access circuit 2 transmits signals ACQE and ACQR to the control controller 9 in response to the signals DCE and DCR, respectively.

The ACQE signal is a direct access channel request acknowledgment for transmission. When the ACQE signal goes low, this means that the direct access circuit 2 executes the data transfer between the main memory 1 and the buffer memory 3. The ACQR signal is an acknowledgment of access channel request direct for reception. When the ACQR signal goes low, this means that the direct access circuit 2 executes the data transfer between the memory 6 and the main memory 1.

 The control automaton 9 transmits SIME and SIMR signals respectively to the buffer memories 3 and 6. The SIME signal indicates that a byte is presented at the input of the buffer memory 3 when it goes high. The signal SIMR indicates that a byte is presented at the input of memory 6 when it goes high.

The buffer memory 3 and the buffer memory 6 respectively transmit IRE and IRR signals to the control controller 9. The signal IRE indicates that the buffer memory 3 is ready to receive data. The signal
IRR indicates that buffer 6 is ready to receive data.

 The control controller 9 transmits SOME and SOMR signals respectively to the buffer memories 3 and 6. The SOME signal is an order for transmission of one byte from the buffer memory 3 to the error correction circuit 4, when it goes high. The signal SOMR is an order for transmission of a byte from memory 6 to memory 1, via direct access circuit 2, when it goes high.

 The control automaton 9 transmits SOFE and SOFR signals respectively to the error correction circuits 4 and 7. The SOFE signal is an order of transmission of a byte from the error correction circuit 4 to the transmission circuit 5. The signal SOFR is an order for transmission of a byte from the error correction circuit 7 to the buffer memory 6.

 The buffer memory 3 transmits an ORE signal to the control controller 9. The ORE signal indicates that the buffer memory 3 contains data to be transmitted when it is in the high state.

 The buffer memory 6 transmits an ORR signal to the control automaton 9. The ORR signal indicates that the memory 6 contains data in reception when it is in the high state.

 The control controller 9 transmits signals SIFE and SIFR respectively to the error correction circuits 4 and 7. The signal SIFE indicates that a byte is presented at the input of the error correction circuit 4, when it is at the high state. The signal SIFR indicates that a byte is presented at the input of the error correction circuit 7, when it is in the high state.

 The control controller 9 transmits signals STE and STR respectively to the error correction circuits 4 and 7. The signal STE indicates the start of a useful data block presented to the error correction circuit 4 when it passes high. The signal STR indicates the start of a useful data block presented to the error correction circuit 7 when it goes high.

 The error correction circuits 4 and 7 respectively transmit OUTE and OUTR signals to the control controller 9. The OUTE signal indicates that the error correction circuit 4 has useful bytes present at the output, or that these bytes useful are being transmitted to the transmission circuit 5, when it is in the high state. When the signal OUTE is in the low state, it indicates either that redundancy bytes are being transmitted to the transmission circuit 5, or that no byte is being transmitted between the circuit 4 and the circuit 5.

 Similarly, the signal OUTR indicates that the error correction circuit 7 has useful bytes present at the output, or that useful bytes are being transmitted to the memory 6 when it is in the high state. When the OUTE signal is in the low state, it indicates either that redundancy bytes are present at the output of circuit 7, or that no byte is being transmitted between circuit 7 and circuit 6.

 Data transmission and reception are independent of each other and can operate in both full-duplex and half-duplex.

 We are first interested in the transmission of data, described with reference to Figures 4, 5 6 and 7. The transmission of data involves data transfers between the main memory 1, the direct access circuit 2 , the buffer memory 3, the error correction circuit 4 and the transmission circuit 5. These transfers are controlled by the automaton 9 and are described in the form of algorithms.

 The data transfers necessary for transmitting data and described with reference to FIGS. 5, 6 and 7 can be carried out simultaneously, while being asynchronous.

 FIG. 5 represents an algorithm for transferring data between the main memory 1 and the buffer memory 3, via the direct access circuit 2. This algorithm comprises steps E1 to E5 and is implemented by the control automaton. Steps E1 to E5 are cyclically traversed, and the control automaton 9 passes from one step to the next on each switching of an internal clock.

Step E1 is the initialization of the data transfer, at which the signal
DCE for direct access channel request is low, i.e. the control controller 9 does not request a direct access channel to direct access circuit 2. The SIME signal is also in the low state, which means that no byte is presented at the input of the buffer memory 3 by the direct access circuit 2.

The next step E2 is a logic test on the values of the signals
DEME and IRE to check if they are both high. The signal DEME in the high state indicates that the circuit 5 authorizes a transmission of data, and the signal IRE in the high state indicates that the buffer memory 3 is not full and can receive data. As long as these signals are not both in the high state, step E2 is repeated.

When the DEME and IRE signals both go high,
The control automaton 9 transmits the high DCE signal to the direct access circuit 2, in step E3, to request a direct access channel.

 The next step E4 is a test of the logic value of the signal ACQE to determine whether the direct access circuit 2 is carrying out the requested transfer. As long as the signal ACQE is in the high state, Step E4 is looped back on itself; when the ACQE signal goes low, this means that the direct access circuit 2 transfers the data between the main memory 1 and the buffer memory 3. In the latter case, step E4 is followed by l 'step E5.

 In step E5, the control automaton cancels its request for a direct access channel by transmitting the low DCE signal to the direct access circuit 2. The control automaton 9 transmits the SIME signal to the 'high state to buffer 3 to indicate that data is presented to it as input. Consequently, the data transmitted by the direct access circuit are stored in buffer memory 3.

 Step E5 is followed by step El previously described.

 FIG. 6 represents an algorithm for transferring data between the buffer memory 3 and the error correction circuit 4. This algorithm comprises steps E10 to E16 which are run through cyclically. The control automaton 9 passes from one step to the next on each switching of an internal clock, which may be different from that used for the algorithm of FIG. 5.

 The data transfer algorithm between the buffer memory 3 and the error correction circuit 4 successively commands a transfer of the first predetermined number N of useful data words, and an interruption of the transfer of the data words for a duration of interruption corresponding to the duration which would be necessary to transfer the second predetermined number K of additional words.

The stage of
- to transmit the signals SIFE and STE in the low state to the correction circuit 4, to signify that no byte is presented at the input of circuit 4.

 The next step Ell is a logical test of the DEME and ORE signals.

When these signals are both in the high state, this means that a transmission request has been transmitted to the control automaton 9, and that the buffer memory 3 contains data to be transmitted. As long as these two conditions are not satisfied, Step Ell is repeated.

 When these two conditions are verified, Step Ell is then followed by step E12 during which the counter CPTE is incremented by one unit, and the control automaton 9 transmits the signal SOME in the high state to the buffer 3 to signify an order of transmission of byte from buffer 3 to circuit 4, and transmits the signals SIFE and STE in the high state to the error correction circuit 4, to signify that a byte is presented at the input of circuit 4, and that this byte constitutes the beginning of a block of useful data.

In the next step E13, the counter CPTE is incremented by one unit and the control automaton 9 transmits the signal SOME in the high state to the buffer memory 3 to signify to it an order of transmission of byte from the buffer memory 3 to circuit 4, and transmits the signal SIFE in the high state and the signal
STE in the low state at error correction circuit 4, to signify that a byte is presented at the input of circuit 4, and that this byte does not constitute the start of a block of useful data.

The following step E14 is a test to check whether the counter CPTE of bytes transmitted to the error correction circuit 4 has reached the predetermined value N, corresponding to the number of useful bytes present in a code word for correction of mistake. As long as the value N is not reached,
Step E13 is repeated.

The steps E12 and E13 allow the transfer of the useful bytes OC, to
OCN between memory 3 and error correction circuit 4.

 When N useful bytes have been transmitted to the error correction circuit 4, step E14 is followed by step E15, in which the counter CPTE is incremented by one, and the control automaton 9 transmits the signal SOME in the low state to the buffer memory 3 to indicate to it an absence of an order for transmission of byte from the buffer memory 3 to the circuit 4, and transmits the signal SIFE in the high state and the signal STE to the low state at error correction circuit 4, to signify that a byte is presented at the input of circuit 4, and that this byte does not constitute the start of a useful data block.

 The bytes transmitted to circuit 4 during step E15 are not useful bytes, and their value does not matter. These bytes are padding bytes Orr to OrK, which will be replaced later by the redundancy bytes OR1 to ORK determined by the error correction circuit 4.

The next step E16 is a test to check the value of the counter
CPTE. As long as the counter CPTE has not reached the value N + K, step E15 is repeated.

When the counter CPTE has reached the value N + K, a sufficient number of bytes have been transmitted to allow the error correction circuit 4 to form an error correction code word MC. Step E16 is then followed by step E10. Steps E10 to E16 are repeated as long as there are bytes in buffer memory 3 to be transmitted to the error correction circuit 4 (signal
ORE high).

 FIG. 7 represents a data transfer algorithm between the error correction circuit 4 and the transmission circuit 5. This algorithm includes steps E20 to E23 which are cyclically traversed by the control automaton. The control automaton 9 passes from one step to the next on each switching of an internal clock, which may be different from those used for the algorithms of FIGS. 5 and 6.

 Step E20 is an initialization in which the control circuit 9 puts the signal SOFE in the low state, to indicate to the error correction circuit 4 not to transmit data to the transmission circuit 5.

The next step E21 is a test to check the value of the signals
DEME and OUTE. As long as the DEME and OUTE signals are not both high, step E21 is repeated.

 When the signals DEME and OUTE are both in the high state, this means that a request for transmission of data has been transmitted to the control circuit 9, and that the error correction circuit 4 contains data to transmit. Step E21 is then followed by step E22 in which the control automaton 9 transmits the signal SOFE in the high state to the error correction circuit 4 to indicate to it to transmit a byte to the transmission circuit 5 .

The next step E23 is a test to check the value of the signals
DEME and OUTE. As long as the signals DEME and OUTE are not both in the low state, step E22 is repeated to transmit a byte to the transmission circuit 5.

When the signals DEME and OUTE are both in the low state, this means that there is no longer any request for transmission of data transmitted to the control circuit 9, and that the error correction circuit 4 does not contain data to be transmitted. Step E23 is then followed by the initialization step
E20.

 We are now interested in the reception of data, described with reference to FIGS. 4, 8, 9 and 10. The reception of data involves transfers of data between the reception circuit 8, the error correction circuit 7, the memory 6, direct access circuit 2 and main memory 1.

These transfers are controlled by the automaton 9 and are described in the form of algorithms.

 The data transfers described with reference to FIGS. 8, 9 and 10 can be carried out simultaneously, while being asynchronous.

 FIG. 8 represents the data transfer algorithm between the data reception circuit 8 and the error correction circuit 7. This data transfer involves exchanges of logic signals between the control controller 9 and the error correction 7. The algorithm includes steps E30 to E35 which are cyclically traversed by the control automaton. The algorithm goes from one step to the next each time an internal clock switches.

Step E30 is an initialization which aims:
- to zero a CPTR counter which counts the bytes which enter the error correction circuit 7,
to transmit the signal SIFR in the low state to the error correction circuit 7, to indicate that no byte is presented at the input of the error correction circuit 7,
to transmit the signal STR in the low state to the error correction circuit 7, to indicate that the first byte of a block is not transmitted to the error correction circuit 7.

 The next step E31 is a test to check the value of the signal DEMR.

As long as the signal DEMR remains low, no reception of data is detected and step E31 is then repeated.

 When the signal DEMR goes high, a reception of data is detected, and step E31 is followed by step E32.

 In step E32, the counter CPTR is incremented by one unit, and the control automaton 9 transmits the signals SIFR and STR in the high state to the error correction circuit 7, to indicate to it that the reception circuit transmits a byte to it, and that this byte is the start of a block of useful data.

 In the following step E33, the counter CPTR is incremented by one unit, and the control automaton 9 transmits the signals SIFR and STR in the high and low state respectively, to the error correction circuit 7, to indicate to it that the reception circuit transmits to it a byte, and that this byte is not the beginning of a block of useful data.

Step E33 is followed by step E34 which is a test to check whether the counter CPTR has reached the value N + K. Until this value is reached,
Step E33 is repeated, so as to transmit an error correction code word MC to the error correction circuit 7.

When the counter CPTR reaches the value N + K, step E34 is followed by step E35, at which the value of the signal DEMR is tested. If the signal
DEMR is high, this means that there is still data received by the reception circuit 8, and step E35 is followed by step E32 to process another error correction code word. .

 If the signal DEMR is in the low state, this means that there is no longer any data received by the reception circuit 8, and step E35 is followed by step E30.

 FIG. 9 represents an algorithm for transferring data between the error correction circuit 7 and the buffer memory 6. This algorithm comprises steps E40 to E45 which are traversed cyclically.

The algorithm goes from one step to the next with each switching of an internal clock, which can be different from that used for the algorithm of FIG. 8.

 The data transfer algorithm between the error correction circuit 7 and the buffer memory 6 successively commands a transfer of the first predetermined number N of useful data words, and an interruption of the transfer of the data words for a duration of interruption corresponding to the duration which would be necessary to transfer the second predetermined number K of additional words.

Step E40 is an initialization which aims to:
- set a counter CP2R to zero, which counts the bytes transmitted from the error correction circuit 7 to the buffer memory 6,
- transmit the SIMR signal in the low state to the buffer memory 6, to indicate to it that no byte is supplied to it as input,
- transmit the signal SOFR in the low state to the error correction circuit 7, to indicate to it not to transmit a byte to the buffer memory 6.

 The next step E41 is a test of the value of the signals OUTR, DEMR and IRR.

 As long as the signals OUTR, DEMR and IRR are not all in the high state, step E41 is repeated.

When these three signals are in the high state, it means respectively that:
- useful bytes are present at the output of the error correction circuit 7 to the buffer memory 6,
- a data reception is detected,
- the buffer memory 6 is not full, and can therefore receive data.

When these three conditions are verified, Step E41 is followed by step E42, in which the counter CP2R is incremented by one,
The control automaton 9 transmits the signal SIMR in the high state to the buffer memory 6, to indicate to it that a byte is presented to it as an input, and the control automaton 9 transmits the signal SOFR in the high state to the error correction circuit 7 for controlling the transmission of a byte between the error correction circuit 7 and the buffer memory 6.

 The next step E43 is a test to check whether the counter CP2R has reached the value N. As long as this is not the case, Step E42 is repeated.

When the counter CP2R has reached the value N, this means that the error correction circuit has transmitted the N useful bytes OC, to OCN of a word
MC of error correction code to the buffer memory 6. The step E43 is then followed by the step E44 in which the counter CP2R is incremented by one unit, the control automaton 9 transmits the signal SIMR to the low state to the buffer memory 6, to command it not to receive a byte, and the control controller 9 transmits the signal SOFR in the high state to the error correction circuit 7 to control the transmission of a byte between error correction circuit 7 and buffer memory 6.

 At step E44, the redundancy bytes ORi to ORK of the error correction code word MC which leave circuit 7 are not stored in buffer memory 6.

The next step E45 is a test on the value of the counter CP2R, to repeat step E44 for the K redundancy bytes of the error correction code word. So, as long as the counter CP2R has not reached the value
N + K, Step E44 is repeated, and when this value is reached, Step E45 is followed by step E40.

 FIG. 10 represents an algorithm for transferring data between the buffer memory 6 and the main memory 1, via the direct access circuit 2.

The algorithm comprises steps E50 to E54 which are traversed cyclically by the control automaton. The algorithm goes from one step to the next with each switching of an internal clock, which can be different from those used for the algorithms of Figures 8 and 9.

Step E50 is an initialization at which:
the DCR signal is transmitted in a low state to the direct access circuit 2, to indicate to it that there is no data to be transferred from the buffer memory 6 to the main memory 1, and
- the signal SOMR is transmitted in the low state to the buffer memory 6, to instruct it not to transmit a byte to the direct access circuit 2.

The next step E51 is a test on the values of the signals DEMR and
ORR. As long as the signals DEMR and ORR are not both high, step E51 is repeated.

 When the signals DEMR and ORR are both in the high state, this signifies that a reception of data is detected, and that the buffer memory 6 contains data to be transmitted to the main memory 1. Step E51 is then followed by step E52, in which the control automaton 9 transmits the signal DCR in the high state to the direct access circuit, to command it a direct access channel to the main memory 1.

 The next step E53 is a test on the value of the signal ACQR, to determine if the direct access circuit performs the data transfer between the buffer memory 6 and the main memory 1. As long as the response is negative, it is that is to say that the signal ACQR is in the high state, step E53 is repeated.

 When the signal ACQR goes to the low state, Step E53 is followed by step E54 in which the signal SOMR is transmitted in the high state to the buffer memory 6, to order it to transmit the bytes to the circuit direct access 2.

 When the data has been transferred from the buffer memory 6 to the main memory 1, step E54 is followed by step E50.

 Of course, the present invention is not limited to the embodiments described and shown, but encompasses, quite the contrary, any variant within the reach of ordinary skill in the art.

 In particular, the transmission and reception of data can be carried out by two separate devices, respectively comprising only the circuits necessary for each of these functions.

Claims (13)

1. Device for coding data extracted from a main memory (1), the data being in the form of useful data words, comprising:  a means of direct access (2) to the main memory for extracting the data to be coded,  a means of coding (4) the extracted data, by the formation of word groups (MC) each comprising a first predetermined number (N) of useful data words (OCn) and a second predetermined number (K) of additional words (ORk), the additional words being determined by the coding means,  characterized in that it comprises:  a first buffer memory means (3) connected between the direct access means and the coding means, said buffer memory means receiving the extracted data, and  a control means (9) for transferring data between the first buffer memory means and the coding means, adapted to successively control a transfer of the first predetermined number (N) of useful data words, and an interruption of the transfer of data words during an interruption duration corresponding to the duration that would be necessary to transfer the second predetermined number (K) of additional words. 2. Data coding device, adapted to cooperate with:  - a main memory (1) containing the data to be coded, the data being in the form of useful data words,  a means of direct access (2) to the main memory for extracting the data to be coded,  and comprising:  a means of coding (4) the extracted data, by the formation of groups of words each comprising a first predetermined number (N) of useful data words and a second predetermined number (K) of additional words, the additional words being determined by means of coding,  characterized in that it comprises:  a first buffer memory means (3) connected between the direct access means and the coding means, said buffer memory means receiving the extracted data, and  - a control means (9) for transferring data between the first buffer memory means and the coding means, adapted to successively control a transfer of the first predetermined number of useful data words and an interruption of the transfer of the data words during an interruption duration corresponding to the duration that would be necessary to transfer the second predetermined number of additional words. 3. Coding device according to claim 1 or 2, characterized in that the control means is adapted to control the transfer of data between the main memory (1) and the first buffer memory means (3), via the means d 'direct access (2). 4. Coding device according to any one of claims 1 to 3, characterized in that it comprises a data transmission means (5) connected at the output of the coding means (4), and in that the means of control is adapted to control the transfer of data between the coding means and the transmission means. 5. Device for decoding data coded in the form of groups of words (MC) each comprising a first predetermined number (N) of useful data words and a second predetermined number (K) of additional words, comprising:  a means for decoding (7) the coded data, to supply the first predetermined number of useful data words from each of the groups of words,  - a main memory (1) for storing the useful data words supplied by the decoding means,  a means of direct access (2) to the main memory for entering the useful data words therein,  characterized in that it comprises:  a second buffer memory means (6) connected between the decoding means and the direct access means, and  a control means (9) for transferring data between the decoding means and the second buffer memory means, adapted to successively control a transfer of the first predetermined number (N) of useful data words, and an interruption of the transfer of data words during an interruption duration corresponding to the duration that would be necessary to transfer the second predetermined number (K) of additional words. 6. Device for decoding coded data in the form of groups of words each comprising a first predetermined number (N) of useful data words and a second predetermined number (K) of additional words, comprising:  a means for decoding (7) the coded data, to supply the first predetermined number of useful data words from each of the groups of words,  and adapted to cooperate with:  - a main memory (1) for storing the useful data words supplied by the decoding means,  a means of direct access (2) to the main memory for entering the useful data words therein,  characterized in that it comprises:  a second buffer memory means (6) connected between the decoding means and the direct access means, and  a control means (9) for transferring data between the decoding means and the second buffer memory means, adapted to successively control a transfer of the first predetermined number of useful data words, and an interruption of the transfer of the data words during an interruption duration corresponding to the duration that would be necessary to transfer the second predetermined number of additional words. 7. Decoding device according to claim 5 or 6, characterized in that the control means is adapted to control the transfer of data between the second buffer memory means and the main memory (1), via the direct access circuit (2). 8. Decoding device according to any one of claims 5 to 7, characterized in that it comprises a data reception means (8) connected at the input of the decoding means, and in that the control means is adapted controlling the transfer of data between the data receiving means and the decoding means. 9. Method for coding data extracted from a main memory, the data being in the form of useful data words, comprising the step of:  coding of the extracted data, by coding means forming groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, the additional words being determined by coding,  characterized in that it comprises the steps of:  storage (E5) of the data extracted in a first buffer memory means, prior to coding, and  - control of a transfer (E12, E13) of the first predetermined number (N) of useful data words (OCl-OCN) between the first buffer memory means and the coding means, and successively of an interruption (E15) transferring the data words during an interruption duration corresponding to the duration that would be necessary to transfer the second predetermined number (K) of additional words. 10. Coding method according to claim 9, characterized in that it further comprises the step (E22) of controlling a data transfer to a data transmission means after the coding step. 11. Method for decoding coded data in the form of groups of words each comprising a first predetermined number of useful data words and a second predetermined number of additional words, comprising the steps of:  - decoding of the coded data, by a decoding means supplying the first predetermined number of useful data words from each of the groups of words,  - memorization of the useful data words supplied by the decoding means,  characterized in that it includes the step of:  - control of a transfer (E42) of the first predetermined number of useful data words between the decoding means and a second buffer memory means, and successively of an interruption (E44) of the transfer of the data words for a duration d 'interruption corresponding to the duration which would be necessary to transfer the second predetermined number of additional words. 12. A decoding method according to claim 11, characterized in that it comprises the step (E54) of controlling a data transfer between the second buffer memory means and a main memory (1). 13. A decoding method according to claim 11 or 12, characterized in that it comprises the step (E33) of controlling a data transfer between a data reception means connected at the input of the decoding means, and the decoding means.