FR2761494B1 - FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA - Google Patents

FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA

Info

Publication number
FR2761494B1
FR2761494B1 FR9703817A FR9703817A FR2761494B1 FR 2761494 B1 FR2761494 B1 FR 2761494B1 FR 9703817 A FR9703817 A FR 9703817A FR 9703817 A FR9703817 A FR 9703817A FR 2761494 B1 FR2761494 B1 FR 2761494B1
Authority
FR
France
Prior art keywords
recording
reading
digital data
flow regulation
regulation interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9703817A
Other languages
French (fr)
Other versions
FR2761494A1 (en
Inventor
Claude Chapel
Jean Yves Quintard
Francois Bourdon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Technicolor SA
Original Assignee
Thomson Multimedia SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Multimedia SA filed Critical Thomson Multimedia SA
Priority to FR9703817A priority Critical patent/FR2761494B1/en
Priority to US09/044,443 priority patent/US6356611B1/en
Priority to EP98400677A priority patent/EP0867801A1/en
Priority to JP10074433A priority patent/JPH10334588A/en
Publication of FR2761494A1 publication Critical patent/FR2761494A1/en
Application granted granted Critical
Publication of FR2761494B1 publication Critical patent/FR2761494B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
    • G06F2205/061—Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
FR9703817A 1997-03-28 1997-03-28 FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA Expired - Fee Related FR2761494B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR9703817A FR2761494B1 (en) 1997-03-28 1997-03-28 FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA
US09/044,443 US6356611B1 (en) 1997-03-28 1998-03-19 Bit rate control interface for the recording and/or reading of digital data
EP98400677A EP0867801A1 (en) 1997-03-28 1998-03-23 Bit rate control interface for the recording and/or reading of digital data
JP10074433A JPH10334588A (en) 1997-03-28 1998-03-23 Bit rate controlling interface for recording and/or readout of digital data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9703817A FR2761494B1 (en) 1997-03-28 1997-03-28 FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA

Publications (2)

Publication Number Publication Date
FR2761494A1 FR2761494A1 (en) 1998-10-02
FR2761494B1 true FR2761494B1 (en) 1999-12-03

Family

ID=9505279

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9703817A Expired - Fee Related FR2761494B1 (en) 1997-03-28 1997-03-28 FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA

Country Status (4)

Country Link
US (1) US6356611B1 (en)
EP (1) EP0867801A1 (en)
JP (1) JPH10334588A (en)
FR (1) FR2761494B1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2761494B1 (en) 1997-03-28 1999-12-03 Thomson Multimedia Sa FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA
WO2002013195A2 (en) * 2000-08-03 2002-02-14 Thomson Licensing S.A. Method for recording data streams with a low bit rate
KR100619020B1 (en) 2004-05-22 2006-08-31 삼성전자주식회사 Optical recording medium and recording/reproducing apparatus
EP1858227A1 (en) * 2006-05-16 2007-11-21 THOMSON Licensing Network storage device with separated control and storage data interfaces

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718074A (en) * 1986-03-25 1988-01-05 Sotas, Inc. Dejitterizer method and apparatus
US4759041A (en) * 1987-02-19 1988-07-19 Unisys Corporation Local area network control system synchronization with phase-lock loop
BE1000415A7 (en) * 1987-03-18 1988-11-22 Bell Telephone Mfg Asynchronous based on time division operating communication.
US5007070A (en) * 1989-10-31 1991-04-09 Bell Communications Research, Inc. Service clock recovery circuit
JPH0683578A (en) * 1992-03-13 1994-03-25 Internatl Business Mach Corp <Ibm> Method for controlling processing system and data throughput
JPH0730589A (en) * 1993-07-06 1995-01-31 Canon Inc Data transmitter
SE515201C2 (en) * 1993-11-26 2001-06-25 Ericsson Telefon Ab L M Method and apparatus for clock signal generation
US6115537A (en) * 1994-02-18 2000-09-05 Matsushita Electric Industrial Co., Ltd. Digital signal recording and reproducing apparatus
US5566208A (en) * 1994-03-17 1996-10-15 Philips Electronics North America Corp. Encoder buffer having an effective size which varies automatically with the channel bit-rate
JPH07296571A (en) * 1994-04-21 1995-11-10 Canon Inc Recording/reproducing device
DE69533153T2 (en) * 1994-10-07 2005-08-25 Victor Company of Japan, Ltd., Yokohama Magnetic recording and reproducing apparatus
US5754241A (en) * 1994-11-18 1998-05-19 Sanyo Electric Co., Ltd Video decoder capable of controlling encoded video data
DE19509484A1 (en) * 1995-03-16 1996-09-19 Deutsche Telekom Ag Method for receiving clock recovery for digital signals
JPH0927030A (en) * 1995-07-12 1997-01-28 Fujitsu Ltd Image processor
GB2304501B (en) 1995-08-15 1999-12-29 Motorola As Simulcast system and method of routing a block divided signal
FR2761494B1 (en) 1997-03-28 1999-12-03 Thomson Multimedia Sa FLOW REGULATION INTERFACE FOR RECORDING AND / OR READING OF DIGITAL DATA

Also Published As

Publication number Publication date
US6356611B1 (en) 2002-03-12
JPH10334588A (en) 1998-12-18
EP0867801A1 (en) 1998-09-30
FR2761494A1 (en) 1998-10-02

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Legal Events

Date Code Title Description
ST Notification of lapse