FR2752333A1 - PROCESS FOR FORMING DATA STORAGE CAPACITORS IN DYNAMIC RAM CELLS - Google Patents

Abstract

The method of the invention comprises forming a double trench structure in at least two superimposed conductive layers (48, 52) which constitute a bottom frame of a data storage capacitor. A dielectric layer (56) is then formed on the lower armature, after which another conductive layer (58) constituting an upper armature of the capacitor is formed on the dielectric layer. In this device, the double trench structure in the data storage capacitor increases the surface area of the bottom armature, which in turn increases the capacitance of the capacitor.

Description

CAPACITOR TRAINING PROCESS

  FOR STORING DATA IN CELLS

DYNAMIC LIVE MEMORY

  The present invention relates to a method of manufacturing semiconductor integrated circuits. The invention relates more particularly to

  a process for forming data storage capacitors

  born with increased capacity in dynamic random access memory (or DRAM) cells, so as to maintain a possibility of high data retention, even if the size of the DRAM chip is reduced

  to achieve a higher level of integration.

  A dynamic random access memory (or DRAM) is a volatile memory

  semiconductor tile operating in read / write which is widely used for main memory in most computers. In the information age, there is a constant need for DRAM memories with a higher level of integration, so as to satisfy the requirements of applications of successive generations, which are always more sophisticated. There is therefore an ongoing research effort in the semiconductor industry to develop DRAM memories with higher integration densities of memory cells, in a single memory chip

DRAM.

  A single DRAM memory chip includes a set of memory cells, each of which includes at least one MOS transistor and a data storage capacitor connected in series with the MOS transistor. Data storage capacitor is used

  to keep electrical charges representative of bi-

  "0" and "1". However, the value of these electrical charges diminishes

  progressively cloud due to leaks. Periodic regeneration of these electrical charges is therefore required to allow the capacitor

  data storage to keep binary data. He is habi-

  It is therefore desirable that the data storage capacitor be formed with a capacity high enough that electrical charges can be reliably retained for an extended period of time. If the capacity was too low, the data stored in the DRAM memory cells could easily be lost in one

short duration.

  Two ways are currently used to increase the density of integration of memory cells in a DRAM memory chip: (1) reducing the size of circuit elements of the DRAM memory chip, such as the length of interconnections and the width of grids of MOS transistors; and (2) reducing the spacing between individual circuit elements. In DRAM memories of the future or next generation, with ultra-high integration level (or ULSI for "Ultra Large Scale Integration"), the data storage capacitors, or more precisely the charge storage armatures (electrodes) which are used to keep the electric charges, will have a size reduced in proportion. It is known, according to fundamental principles of circuits, that the capacitance of a capacitor is proportional to the surface area of the charge storage plates. Therefore, a reduction in size of the data storage capacitors in cells

  DRAM memory will correspondingly reduce the capacity of these

  data storage capacitors, so these data storage capacitors will retain a reduced amount of electrical charge. The binary data that is stored in the DRAM memory cells could thus be lost more easily and quickly due to the leakage of electrical charges. To keep the data in the data storage capacitors, it is necessary to regenerate the DRAM memory cells more frequently. However,

  read / write operations cannot be performed while

  during the regeneration period, which effectively reduces the performance-

  these DRAM memory cells. Therefore, in manufacturing DRAM memory cells, it is always desirable to have

  high capacity data storage capacitors.

  Figure 1 is a schematic section of a single DRAM memory cell having a data storage capacitor formed by a known conventional method. The manufacturing of the DRAM memory cell is based on a silicon substrate 10, on the main surface

  outside of which a field oxide layer 12 and a layer are formed

  grid oxide che 14. A first conductive layer is formed,

  such as a layer of doped polycrystalline silicon, on the outer surface

  of the substrate, and it is then removed selectively to form a grid 16a and a metal contact 16b. Then forming respective spacers 18a and 18b on the side walls of the grid 16a and the metal contact 16b. A pair of N + source / drain regions 20a and 20b are formed in the silicon substrate 10. An insulating layer 22 is formed on the outer surface of the substrate and is removed.

  then selectively to expose the source / drain region 20b.

  To form a data storage capacitor for the DRAM cell, a conductive layer 24, a dielectric layer 26 and another conductive layer 28 are successively formed on the

  outer surface of the substrate, with the layer 24 in contact with the surface

  gion 20b. The conductive layers 24 and 28 may for example be layers of doped polycrystalline silicon which fulfill the function of

  two opposite electrodes for the data storage capacitor.

  The previous data storage capacitor has a drawback

  comes which is as follows: when the element size of the microchip

  DRAM memory is reduced to increase the integration of memory cells

  moire on a chip, the surface areas of the conductive layers 24 and 28 are also reduced proportionally, which causes a decrease in the capacity of the storage capacitors. This significantly reduces the possibility of charge retention of the capacitor.

data storage.

  An object of the present invention is therefore to provide a process

  training dice for data storage capacitors with a

  increased capacity in DRAM memory cells, so as to increase

  the possibility of data retention from DRAM memory cells.

  In accordance with the foregoing object as well as others, the present invention provides a new and improved method for forming a data storage capacitor in a memory cell.

  DRAM. In the process of the invention, the first step consists in pre-

  covering or providing a semiconductor substrate having at least one tran

  MOS sistor formed on this substrate, and a first insulating layer forming

  mee on the MOS transistors, and being traversed by an opening to expose one of the source / drain regions. The second step is to form a first conductive layer on the outer surface of the

  substrate, that is to say on the first insulating layer, and to fill the

  greenery. The next step consists in forming an insulating bump on the first conductive layer, above the opening, this step being preferably accomplished by forming a second insulating layer on the first conductive layer, and then selectively attacking the

  second insulating layer to remove a selected part of the se-

  insulating layer, to form the insulating bump. The next step

  consists in forming a second conductive layer covering the pre-

  conductive layer and insulating bump. We then form an element

  spacer in insulating material on the side walls of a projecting part of the second conductive layer which covers the insulating bump. The next step consists in anisotropically attacking the exposed parts of the first and second conductive layers, using the spacer element and the insulating bump as an attack mask,

  so as to selectively remove part of the first and second layers

  conductive, and to form at least a pair of trenches which extend inside the first conductive layer to a given depth, in the region surrounded by the spacer, and between the element d spacing and the insulating hump. Next, the spacer and the insulating bump are removed from the substrate, and a

  dielectric layer covering the remaining parts of the first and second

  conde conductive layers. Finally, we form a third layer

  conductive on the dielectric layer.

  In the semiconductor structure which is thus formed, the remaining part of the first and second conductive layers, the layer

  dielectric and the third conductive layer constitute in combination

  its the data storage capacitor of the DRAM memory cell. The double trench structure in the data storage capacitor particularly increases the surface area of the lower frame of the data storage capacitor, so that the

  capacity of the data storage capacitor is also increased

proportionately lied to.

  Other characteristics and advantages of the invention will be

  better understood on reading the description which follows in a

  preferred embodiment, given by way of nonlimiting example. Following the

  description refers to the accompanying drawings, in which:

  Figure 1 is a schematic section of a single DRAM memory cell having a data storage capacitor formed by a single conventional method; and FIGS. 2A to 2H represent schematic sections of a single DRAM memory cell, illustrating the process steps involved in the process according to the present invention, for

  form a data storage capacitor with an ac-

  raw, in a DRAM memory cell.

  FIGS. 2A to 2H are schematic sections represented

  both the steps involved in the process according to the present invention, to form a data storage capacitor in

a single DRAM memory cell.

  Referring first to FIG. 2A, it is noted that this

  The DRAM memory cell is formed on a semiconductor substrate such as a silicon substrate 30. A field oxide layer 32 is formed on a selected portion of the surface of the silicon substrate 30, so as to define an active area for a cell. Then, using conventional techniques, a gate oxide layer 34 is formed on the outer surface of the substrate 30, including the layer 32, and formed

  successively conductive layers, such as a silicon layer

  polycrystalline cium and a metal silicide layer, on the gate oxide layer 34 on the substrate 30, and then selectively remove the gate oxide layer 34 and the successive conductive layer, to

  form a grid 36 and a layer of metal silicide 38 covering it

  and also another metal contact 36 and a layer of silicon.

  metal ciure 138 on the remaining part of the gate oxide layer 34. Spacers 40 are formed from an insulating material, for example silicon dioxide, on respective side walls of the

  grid 36 and the metal silicide layer 38, and elements are formed

  spacers 140 on respective side walls of the metal contact 136 and the metal silicide layer 138 and the underlying portion of the gate oxide layer 34. Next, a pair of regions of source / drain N + 42, 44 in the silicon substrate

, on its upper surface.

  Referring now to FIG. 2B, it is noted that a first insulating layer 46 is formed by depositing, for example, an oxide layer over the entire outer surface of the substrate 30 and over the other layers formed on this surface. The layer 46 is then subjected to an anisotropic etching treatment so as to remove a selected part of the oxide layer 46, thereby forming in the layer 46 a self-aligned opening 100 which exposes the source region / drain 42. Turning now to FIG. 2C, it is noted that during a following process step, a conductive layer 48, such as a layer of polycrystalline silicon, is deposited by a chemical vapor deposition process (or CVD), with a thickness of 300 nm at

  800 nm, on the surface of the substrate. We dop the layer of poly-

  crystalline with impurities to increase its conductivity. An insulating bump 50 is then formed on the first conductive layer 48, in a position situated above the source / drain region N + 42, by first forming an insulating layer, for example an oxide layer, on the surface of the conductive layer 48, and by performing

  then a classic photolithography and attack treatment,

  lesson in removing by anisotropic attack a selected part of the se-

  insulating layer, to obtain the bump 50. Then, we form

  an additional conductive layer 52, such as a silicon layer

  doped polycrystalline cium, covering both the first conductive layer

trice 48 and the insulating hump 50.

  Then, as shown in Figure 2D, we form ele-

  spacers 54 made of an insulating material, for example silicon dioxide, on the side walls of the projecting part of the second

  conductive layer 52 which covers the insulating hump 50.

  Referring next to FIG. 2E, it is noted that the insulating hump 50 and the spacing elements 54 are used jointly as an attack mask for an anisotropic attack process, so as to remove the parts not masked from the conductive layers 48 and 52. The anisotropic etching treatment is controlled so as to remove all the parts of the conductive layers 48 and 52 which are found

  wind beyond the region limited by spacers 54 in-

  turning the insulating hump 50, but performing the removal to a predetermined controlled depth, not reaching the source / drain regions N + 42, in the unmasked parts of layers 48 and 52

  which lie within the region bounded by the elements of space

  cement 54, and between the spacers 54 and the boss 50, so

  lesson in forming a pair of trenches 55a, 55b which extend inside

  of the conductive layer 48, for example to a depth which corresponds

  practically corresponds to the layers 38 and 178, as shown

feel.

  Then, as shown in FIG. 2F, the insulating hump 50 and the insulating spacing elements 54 are removed, so as to expose the remaining parts or regions of the conductive layers 48 and

  52. The remaining parts of the conductive layers are used together

  these 48 and 52 for the lower armature (electrode) 53 of the capacitor

  DRAM memory cell data storage.

  Referring next to FIG. 2G, it is noted that a dielectric layer 56 is formed, such as a layer of silicon nitride /

  silicon dioxide (NO) or a layer of Ta2O5, on the outer surface

  lower of the substrate, so as to cover the lower frame 53 of the

  DRAM memory cell data storage densifier.

  Referring finally to Figure 2H, we note that we de-

  laying on the dielectric layer 56, by chemical vapor deposition (CVD), an additional conductive layer (third layer) 58, such as a layer of polycrystalline silicon, and as shown, this layer fills practically the rest of the space in trenches 55a and 55b. It is also possible to dop the polycrystalline silicon layer with

  impurities so as to increase its conductivity. The conductive layer

  trice 58 performs the function of an upper armature (electrode) of the con-

  DRAM memory cell data storage densifier.

  In summary, the lower reinforcement 53 (the two conductive layers

  48 and 52 in combination), the dielectric layer 56 and the layer

  additional conductor (third layer) 58 form in combination

  its a capacitive structure for the DRAM memory cell, filled

  sant the function of a data storage capacitor. More parti-

  especially, the double trench structure 55a, 55b in the condensa-

  data storage increases the surface area of the frame

  lower 53, which has the effect of increasing the capacitance of the

data storage.

  It goes without saying that many modifications can be made.

  brought to the device and to the process described and represented, without leaving the

part of the invention.

Claims (16)

  1. Method for forming a storage capacitor   data in a dynamic random access memory (or DRAM) cell,   characterized in that it comprises the following steps: (a) providing a semiconductor substrate (30) having at least one MOS transistor, comprising a pair of source / drain regions (42, 44), formed on this substrate, and a first insulating layer (46) formed on the MOS transistor, the first insulating layer (46) having an opening for exposing one of the source / drain regions (42, 44); (b) forming a first conductive layer (48) on the first insulating layer (46) so as to fill the opening; (c) forming an insulating bump (50) on the first conductive layer (48), above the opening; (d) forming a second conductive layer (52) on the exterior surface of the substrate (30), so as to cover the first conductive layer (48) and the insulating bump (50); (e) a spacer (54) is formed from an insulating material   on the side walls of a projecting part of the second layer   ducting (52) which covers the insulating boss (50); (f) using the spacer (54) and the insulating boss (50) as an attack mask,   an anisotropic attack is carried out on the bare parts of the first and second   conductive layers (48, 52), for selectively removing   parts of the first and second conductive layers (48, 52) on the outside   of the spacer (54), and to form at least one pair of trenches (55a, 55b) extending inside the first conductive layer (48) to a given depth, in a region which is   surrounded by the spacer (54); (g) removing the element of es   pitch (54) and the insulating hump (50); (h) a dielectric layer is formed   stick (56) on the outer surface of the substrate (30), for covering the remaining part of the first and second conductive layers (48, 52);   and (i) a third conductive layer (58) is formed on the di-   electric (56), whereby the remaining parts of the first and second   conductive layers (48, 52), the dielectric layer (56) and the   third conductive layer (58) in combination constitute a con-   data storage densifier of a DRAM memory cell.   2. A method of forming a data storage capacitor in a DRAM memory cell according to claim 1, characterized in that the step of forming an insulating bump (50) comprises: forming an insulating layer on the first conductive layer (48); and selective removal of the second insulating layer   to remove parts of it and form the insulating hump (50).   3. Method for forming a data storage capacitor in a DRAM memory cell according to claim 2, characterized in that the second insulating layer is a layer of silicon dioxide.   4. A method of forming a data storage capacitor in a DRAM memory cell according to claim 2, characterized in that the step of selective removal of the second layer   insulating is an anisotropic attack treatment.   5. Method for forming a data storage capacitor in a DRAM memory cell according to claim 1, characterized in that the spacer (54) consists of dioxide of silicon.   6. Method for forming a data storage capacitor in a DRAM memory cell according to claim 1,   characterized in that the dielectric layer (56) is a layer of ni-   silicon tride / silicon dioxide (NO).   7. A method of forming a data storage capacitor in a DRAM memory cell according to claim 1, characterized in that the dielectric layer (56) is a layer of Ta205. 8. A method of forming a data storage capacitor in a DRAM memory cell according to claim 1,   characterized in that the first conductive layer (48) is a layer   doped polycrystalline silicon.   9. A method of forming a data storage capacitor in a DRAM memory cell according to claim 1, characterized in that the second conductive layer (52) is a layer of doped polycrystalline silicon.   10. A method of forming a data storage capacitor in a DRAM memory cell according to claim 1,   characterized in that the third conductive layer (58) is a layer   doped polycrystalline silicon.   11. Method for forming a data storage capacitor in a DRAM memory cell, characterized in that it   includes the following steps: (a) providing a semiconductor substrate   tor (30) on which are formed at least one MOS transistor comprising a pair of source / drain regions (42, 44), and a first oxide layer (46) on the MOS transistor, the first oxide layer having an opening for exposing one of the source / drain regions (42, 44); (b) forming a first conductive layer of polycrystalline silicon (48) on the first oxide layer (46) so as to fill the opening; (c) forming a second oxide layer on the first conductive layer of polycrystalline silicon (48); (d) selectively attacking the surface of the   substrate (30) for removing selected portions of the second layer   oxide oxide, to form an oxide bump (50) on the first layer   conductive of polycrystalline silicon (48); (e) forming a second layer   polycrystalline silicon conductive che (52) on the first polycrystalline silicon conductive layer (48) and on the oxide hump (50); (f) forming a spacer (54) of an insulating material on side walls of a projecting portion of the second conductive layer of polycrystalline silicon (52) which covers the oxide bump (50); (g) using the spacer element (54) and the oxide bump (50) as an attack mask, an anisotropic attack is carried out on the bare parts of the first and second conductive layers of polycrystalline silicon ( 48, 52), for selectively removing portions of the first and second conductive layers of polycrystalline silicon (48, 52) outside of   the spacer (54), and to form at least one pair of tran-   chées (55a, 55b) extending inside the first conductive layer   polycrystalline silicon (48) in a region which is surrounded by the spacer (54) and between the spacer (54) and the oxide bump (50); (h) the spacer (54) is removed and the   oxide bump (50); (i) a dielectric layer (56) is formed on the over-   outer face of the substrate (30), for covering the remaining parts of the first and second conductive layers of polycrystalline silicon (48,   52); and (j) forming a third conductive layer of poly-   crystalline (58) on the dielectric layer (56), whereby the parts   of the first and second conductive layers of silicon po-   lycrystalline (48, 52), the dielectric layer (56) and the third conductive layer of polycrystalline silicon (58) constitute in combination a   data storage capacitor of a DRAM memory cell.   12. Method for forming a data storage capacitor in a DRAM memory cell according to claim 11,   characterized in that it further comprises a step of introducing im-   doping purities in the first conductive layer of poly- crystalline (48).   13. Method for forming a data storage capacitor in a DRAM memory cell according to claim 11,   characterized in that it further comprises a step of introducing im-   doping purities in the second conductive layer of poly- crystalline (52).   14. Method for forming a data storage capacitor in a DRAM memory cell according to claim 11,   characterized in that it further comprises a step of introducing im-   doping purities in the third conductive layer of poly- crystalline (58).   15. Method for forming a data storage capacitor in a DRAM memory cell according to claim 11, characterized in that the dielectric layer (56) is a nitride layer   silicon / silicon dioxide (NO).   16. A method of forming a data storage capacitor in a DRAM memory cell according to claim 11,   characterized in that the dielectric layer (56) is a layer of Ta205.