FR2748620A1 - Arbitration method for queued data awaiting transmission over digital network - Google Patents

Abstract

The method involves determining the number of data queues. Each data queue is associated with a data priority determined by a circuit in an input interface. The circuit includes a counter (41) and an eligibility table (42). This table consists of a number of registers equal to the number of node output ports of the network. A binary signal is used to indicate the eligibility of each waiting queue, with a logic 0 indicating that queue is not eligible and a logic 1 indicating that it is. A queue is determined to be eligible if it is not empty and if the destination is not congested. A random number generator is used to determine which queued data is to be transmitted when there are a number of eligible queues with the same priority.

Description

 The present invention relates to a method and device for arbitrating between queues in a digital transmission network. It applies in particular to the digital data mixing and switching equipment composing a network operating in asynchronous transmission mode called ATM, the latter term being derived from the English expression "Asynchronous Transfer Mode". More generally, the invention applies to all digital data transmission networks where it is necessary to route this data to arbitrate between queues at different points of the network.

Telecommunication systems are increasingly using the asynchronous ATM transfer mode. This transmission technique makes it possible to convey digital information of varied and irregular nature and bit rates. The information is transported through a network which can present various topologies, for example in mesh, ring or star. Each node in the network, called a switch
ATM, is connected to an adjacent node by a transmission route accepting all types of technology. Transmission can therefore take place, for example, by cable, microwave or optical fiber.

 The principle of the ATM technique is to segment the data from the various sources into blocks of fixed length, and to add a header to a block to form an ATM cell. ATM cells from various sources are then multiplexed and transmitted asynchronously over the transmission artery.

 Within ATM equipment, at a given time, several cells can compete for access to the same resource. Queuing of competing cells is then necessary and it is then necessary to choose in what order the queues will be served.

 In equipment, for example an ATM switch, having Ne input ports and N output ports, it is necessary to queue the cells received or to be transmitted. At an input port, the cells are stored in different FIFO type registers according to precise criteria, for example according to the destination, the path or the virtual channel, the output port of the following equipment or the priority . A FIFO type register is a register known to those skilled in the art where the bits exit according to their order of entry into the register, FIFO being derived from the Anglo-Saxon expression "First in, First out".

According to the prior art, each port has a priority level arbitration algorithm which makes it possible to choose the queue to be served from among all those which have the same priority. This mechanism refers to an eligibility table which contains binary information which, depending on their values, authorizes or not to serve a client or a set of clients. For example, this eligibility table prohibits serving queues whose cells are intended for congested exit ports. One of the most used arbitration algorithms is known as "Priority"
Rotating "or" Round Robin "The algorithm operates independently from one input port to another.

 Current arbitration mechanisms introduce several drawbacks, in particular they can lead to performance degradation. The performance is thus poor in that there is congestion inside the switches. This results in an increase in response times for the end user. Ultimately, the user is therefore poorly served.

 The object of the invention is to overcome the aforementioned drawbacks, in particular to allow an efficient and rapid flow of information at each node of a network, for example asynchronous, and therefore improve the final service for the user.

 To this end, the invention relates to an arbitration process between queues at a node of a digital transmission network, characterized in that each queue having a priority level assigned , it introduces a hazard into the selection of queues with the same priority.

 The invention also relates to a device for implementing the method. The main advantages of the invention are that it is simple to implement and that it is economical.

Other characteristics and advantages of the invention will become apparent from the following description given with reference to the accompanying drawings which represent:
FIG. 1, an arbitration device operating according to the prior art,
- Figures 2a, 2b, 2c illustrations of a synchronization problem highlighted by the Applicant,
- Figure 3, an example of possible embodiment for the implementation of the method according to the invention.

 Figure 1 shows, by a block diagram, an arbitration device between queues at a node of a digital network, according to the prior art. An item of equipment 1 is dedicated to receiving data (ATM cells or packets or frames, etc.) coming from Ne input ports and for retransmitting them on some of its Ns output ports. Since the output ports have a limited speed, if all the input ports present data intended for the same output port, it will be impossible to retransmit all these cells at the same time. The cells which could not be served will then be queued in the FIFO of the destination output port and retransmitted later. When these output FIFOs reach a certain threshold, it is said that there is congestion within the equipment.

In order not to go further in congestion, it must be notified to all ports of entry via a flow control between outputs and inputs and / or for the updating of a table of eligibility. Thus for each port of entry, an arbitrator is required to choose the queues to be served from those which are not likely to worsen congestion.

A choice algorithm is then necessary; this is the "Round algorithm
Robin ", also called" Rotating Priority "algorithm
Cells arrive at a node, materialized by equipment 1.

This equipment is for example an ATM switch. Its function is in particular to direct the cells arriving at its input ports 10, 11 to its output ports 12, 13. The equipment 1 comprises for example Ne input ports 10, 11. A first input interface 2 is connected to the first input port 10 of the equipment 1. An interface term 3 is connected to the n th input port 11. An interface, for example the first 2, comprises circuits 201, 20P made up of registers 14 FIFO type, a first circuit 201 containing all the priority 1 queues, the highest priority, one trap circuit 20P containing all the priority queues
P, the lowest priority, and other circuits containing the intermediate priority queues. By way of example, the operation of the interfaces 2, 3 is explained relative to the circuits 201, 301 of priority 1 of these interfaces. A priority 1 circuit will hereinafter be called priority 1. Each output port of node 1 of the network has a priority level arbitration algorithm.

A priority 1 comprises a number Ns of registers 14 of the type
FIFO, this number Ns being equal to the number of output ports of the equipment 1. Each register 14 of priority 1 contains one or more incoming cells. Row X of register 14, also called FIFO number, corresponds to the number of the output port provided for the incoming cell. The aforementioned FIFO number X in fact corresponds to the queue number of the incoming cell. For example, a cell having rank X is provided for exiting on the X th output port of node 1 of the network. In other words, a FIFO contains a cell queue, the FIFO 14 possibly being empty.

 Each priority 201, 20P, 301, 30P is associated with a choice algorithm 15 carried out for example by a processor not shown. The generally used arbitration algorithms are known as "Round Robin". The arbitration algorithm 15 associated with priority 1 selects a rank X after having selected a lower rank, and this among the FIFOs which have the right to transmit a cell towards the output of node 1. The associated cells are said to be eligible , by extension we will say that it is the ranks or FIFO numbers that are eligible. An eligibility table not shown is associated with the priorities or circuits 201, 20P. A FIFO whose rank X has been selected transmits a cell to the rank X output port of the equipment 1.

 In the next round, the algorithm selects a next rank, X + 1 if it is eligible, then rank X + 2, and so on. Each FIFO 14 is associated with an address from the eligibility table to read binary information on its eligibility state. The arbitration algorithm 15 therefore operates cyclically on all the ranks or numbers of FIFO 1, 2, ... X, Ns of the same priority, in the example of operation explained, it is in this case priority 1 registers, therefore associated queues.

 The Applicant has highlighted problems of synchronization of all the arbitration algorithms of all the input ports of a node of a network when they are subjected to heavy loads in particular when all the queues, that is, all priorities 201, 20P, 301, 308 contain cells. The same synchronization phenomenon can obviously also be found at the output ports if they are connected to another node of the network, that is to say that the same principle can be applied between different nodes of a network. In this case, the cells are stored in FIFO whose number indicates the output port of the following equipment. The flow control is this time transmitted between nodes.

 Two synchronization problems were highlighted by the Applicant.

 A convergent type synchronization appears when the algorithms of choice evolve towards a synchronization state where all the ports, input or output, serve the same queue at the same time.

 Synchronization of random type occurs when a certain periodicity in the choice of queues to serve causes, at an unpredictable time t, the synchronization of independent algorithms. At this instant t, the algorithms present different phase shifts with respect to each other, and they will keep them as long as they remain synchronized.

This means in particular that if at time t, an input interface serves the queue of rank i and another input interface serves the queue of rank j, then the phase shift difference E-it will remain constant as long as the all queues remain non-empty.

 These two synchronization problems correspond in fact to two types of algorithms based on different flow controls.

 In the case of a check by queue, the arbitration algorithm refers to an eligibility table which indicates the state of each queue. For each cell in a queue, this table indicates the authorization or prohibition to send this cell to the output ports of the node. There then appears an evolution towards converging synchronization.

 In the case of a global check, the arbitration algorithm refers to an eligibility table which indicates the global status of the queues. This table then indicates the authorization or the prohibition to emit a cell for all the queues. An evolution here tends towards a random synchronization.

 From these synchronization problems, it follows that many cells conflict when they have to reach the same resource, an output port, at the same time. They are actually congesting the resource. This type of phenomenon thus leads to a decrease in the performance of the equipment.

 FIGS. 2a, 2b and 2c illustrate a synchronization problem in the case for example where the number of inputs Ne of the node is equal to the number of outputs Ns.

 FIG. 2a illustrates a problem-free case, an arbitration process in its initial phase for example. In the first interface, the queue n "1 is selected, in the interface n" X + 1, the queue n "X + 1 is selected, finally in the last interface Ns., The queue d 'wait n "Ns. is selected, then a new cycle starts again for all the priorities 1 of the interfaces.

 FIG. 2b illustrates the start of an evolution towards a synchronization state. In the case of FIG. 2b, the output port n "1 is for example subject to a blocking. This happens in particular if the output port is congested. If two cells want to exit at the same instant on the same port, one one of them will actually be able to exit and the other will be queued for the corresponding exit port. There will be congestion only when one of the FIFOs of the exit ports has reached a maximum filling threshold. flow control is thus activated and will be sent to all input ports so that the choice algorithms integrate this information into their "eligibility table". Flow control brought back to the entry of the network node then prohibits the first interface to serve queue n "1, its arbitration algorithm then tries to serve queue n" 2. Ultimately, congestion appears when a maximum threshold is reached, for example between the two priorities 1 of the first two interfaces which try t at the same time send a cell to the second output port of node 1 of the network. The output port n "2 prohibiting its access, the first two interfaces will then synchronize on the queue n" 3 as illustrated in Figure 2c. At an instant, if several algorithms are synchronized on n "2 for example, the output FIFO of port 2 will grow and therefore risk quickly reaching its congestion threshold. The more synchronized algorithms, the higher the probability congestion increases, hence the converging trend towards synchronization. A cascade phenomenon continues until all the interfaces emit a cell on the same output port, the last port Ns for example. no physical resource like a bus which prohibits all input ports from transmitting a cell to the same output. They actually all emit a cell but only one of them will be output, the others will be queued waiting for the port of exit concerned.

 Therefore, wishing to reach the same output port at the same time, many cells therefore create congestion. This type of phenomenon thus leads to a reduction in the performance of the equipment as explained in particular above.

 According to the invention, in order to avoid any degradation in performance, the arbitration process breaks the cycles which cause synchronization while guaranteeing equity between the queues. For this, the method introduces a hazard into the selection of queues of the same priority. With each choice, according to the method according to the invention, a queue is for example drawn by lot from all the eligible queues, without being concerned for example with the preceding choices. Fairness is guaranteed on average. Thus, instead of choosing the queue of rank X + 1, if this is eligible, after the queue of rank X, the arbitration means make it possible to choose from among all the eligible queues, which whatever their rank.

 Another way to introduce a hazard according to the invention consists in drawing lots from a given number of queues, for example drawing lots from N eligible queues according to the rank of the last chosen.

So if the previous queue chosen was X, and if the total number of eligible queues is N, then the arbitration means authorize the drawing of a number R between 0 and N so that the R th queue eligible queue from the Xth queue is selected. The selected queue will therefore not necessarily be R + X modulo Ns.

 FIG. 3 shows a possible embodiment of a device for implementing the method according to the invention. This device provides the number of the queue to be served. It is associated with a circuit 201, 20P, 301, 30P of priority given in an input interface 2, 3. It therefore allows the interface to choose a queue among all those of the same priority.

 According to FIG. 3, a counter 41 counts the number of queues which can be elected. For this, the counter 41 is connected to the eligibility table 42. This table is composed for example of Ns registers, Ns being the number of output ports of the network node. The register n "X indicates for example the state of eligibility of the queue n" X by binary information, 1 meaning for example eligible and 0 meaning for example not eligible. A queue X is declared eligible if it is not empty and if the destination port is not congested. The counter 41 therefore counts for example the number of bits equal to 1 in the eligibility table 42.

The result is between 0 and Ns. A random number generation module 43 provides random numbers coded for example on 16 bits, starting for example from a polynomial of degree 32. The possibilities of choice are in this case very important. The random number provided is between 0 and 1.1 being excluded. It therefore belongs to the interval [0, 1 [.

 The output of the counter 41 indicating the result of the counting of the latter and the output of the generator 43 of random numbers are connected to the two inputs of a multiplier 44, the latter carrying out the product of these two inputs, therefore the product of the number of queues waiting list eligible by the random number provided. The number Ns of output ports is for example such that it can be coded on 5 bits. The multiplier 44 performs a rounding in order to present at its output an integer between 1 and Ns. The multiplier 44 makes it possible to carry out a fair random draw of an integer between 1 and N, with N variable between each draw. Another solution could have been to draw a very large number between 1 and 2P-1 (classical random draw since the two bounds are fixed), then express the result in full on 5 bits modulo N (N = number of eligible queues) +1. We thus obtain a number between 1 and N, but the realization of a modulo N (with N not power of 2) is not very easy.

In addition, to be sure of having a fairness random draw, p must be very large. We therefore see the advantages in terms of simplicity and fairness provided by the solution proposed in the device in FIG. 3.

The output of the multiplier 44 is connected to an input of a first multiplexer 45, the other input of this multiplexer having a constant logic state equal to 1. This multiplexer 45 is controlled by a binary signal
M1. Its output is connected to a first input N of a selection circuit 46.

 The output of a second multiplexer 47 is connected to a second input R of the selection circuit 46. A first input of the second multiplexer 47 is in logic 0 while the other input is connected to the output of a memory 48 which stores the output of the selection circuit 46.

This memory 48 in fact stores the last queue served.

The selection circuit goes through the eligibility table from the rank
R + 1, R being the number displayed at its second entry R. It traverses from this rank R + 1, N successive eligible registers, in state 1 for example, of the eligibility table. At its output, it presents the rank of the last register scanned, for example R + 1 + N if all the registers are eligible. If the counter 41 counts a zero result, it deactivates the selection circuit 46, the output of which then remains frozen. The counter 41 is connected to an activation input of the selection circuit 46. The counter indicates whether its result is zero by binary information. The latter is also combined with the output of the selection circuit 46 via a gate "and" 49. The output of this gate is at zero if the counter is at zero, in this case no queue n is to serve. The selection circuit 46 having been deactivated, the number of the last queue served is kept at the output of the circuit. It is therefore possible to loop back on the latter when queues are again to be used. If the counter displays a non-zero result, the gate "and" 49 reproduces the output of the selection circuit. Gate "and" 49 provides the output with the queue number to be served. This number is for example read by a processor which activates for example the register or the corresponding FIFO.

 The various circuits, in particular the counter 41 and the module 43 for generating random numbers, are for example synchronized by a clock signal not shown, or else by a signal controlled by a processor, each synchronization signal corresponding to a new selection. queue.

 The binary information M1, M2 which controls the two multiplexers makes it possible to configure the operation of the assembly.

 If M1M2 = 11, the first entry N of the selection circuit is forced to 1 and the second entry R reproduces the last queue number served. After the queue of row R, that of row R + 1 is thus selected, then that of row R + 2 and so on. A cyclic algorithm of the Round Robin type is then in operation. No risk is introduced, this is the case described above which can lead, in certain circumstances, to an overall reduction in the performance of the equipment.

 If M1M2 = 00, the second input R is forced to zero and the first input N of the selection circuit 46 includes the result of the counter 41. After each selection, a new queue is then chosen at random from among all those eligible.

 If M1M2 = 01, the second entry R reproduces the number of the last queue selected and the first entry N of the selection circuit 46 includes the result of the counter 41.

 If M1M2 = 10, the first entry N is set to 1 and the second entry R of the selection circuit 46 is set to 0. The first queue eligible from the first queue is then selected.

 The circuits of Figure 3 could for example be replaced by a microcontroller integrating the functions of all these circuits.

Claims (11)

 1. Arbitration method between queues (14) at a node (1) of a digital transmission network, characterized in that each queue having a priority level assigned, it introduces a hazard (43) in the selection of queues of the same priority.  2. Method according to claim 1, characterized in that a queue (14) is drawn among all the queues authorized to send a cell.  3. Method according to claim 1, characterized in that a queue (14) is drawn by lot from a given number of queues according to the rank of the last queue selected, and among the queues authorized to transmit.  4. Arbitration device between queues (14) at a node (1) of a digital transmission network, characterized in that a queue having an assigned priority level, it includes selection means (46) queues of the same priority and means (41, 42, 43, 44, 45, 47, 48) for introducing a hazard into the selection means (46).  5. Device according to claim 4, characterized in that the means for introducing a random comprise a module (43) for generating a random number, the selection means (46) operating a selection of queues as a function of this random number .  6. Device according to any one of claims 4 or 5, characterized in that it comprises means (45, 47, M1, M2) for configuring the selection of queues, with or without hazard.  7. Device according to any one of claims 4 to 6, characterized in that being connected to an eligibility table (42) queues, the selection means (46) select a queue from all eligible queues, an eligible queue being a queue authorized to send a cell.  8. Device according to any one of claims 4 to 6, characterized in that being connected to an eligibility table (42) queues, the selection means (46) select a queue from a given number of eligible queues from the last queue selected, an eligible queue being a queue authorized to send a cell.  9. Device according to any one of the preceding claims, characterized in that it comprises at least:  - a generator (43) of random number between 0 and 1  - a counter (41) counting the eligible queues in an eligibility table (42)  - a multiplier (44) performing the product of the random number by the result of the counter (44)  - a selection circuit (46) traversing a number N of successive eligible registers of the eligibility table (42), the number N being the product of the multiplier (44), the selection circuit presenting at output the rank of the last register scanned, each register of the eligibility table being associated with a queue, an eligible register indicating that its associated queue is authorized to transmit a cell, the output of the selection circuit (46) indicating the number of the selected queue.  10. Device according to claim 9, characterized in that it comprises a multiplexer (45) interposed between the multiplier (44) and the selection circuit (46), the multiplexer being controlled by a configuration bit (M1) which can force the output of the multiplexer at 1.  11. Device according to any one of claims 9 or 10, characterized in that it comprises a memory (48) connected to the output of the selection circuit (46), the output of the memory being connected to the input of a multiplexer (47), the output of which is connected to a second input (R) of the selection circuit (46), the multiplexer (47) being controlled by a configuration bit (M2) which can force its output to 0, the circuit selection (46) browsing the eligibility table (42) from the row corresponding to the number displayed on its second entry (R).