FR2746946A1 - Communications system for battery charging system components in vehicle - Google Patents

Abstract

The communications system for linking two electrical or electronic units (A,B) within a vehicle uses a single conductor (L) connected between the units which also share a common base potential such as the vehicle earth. Within each unit there is a decoding circuit (DEC,DEC') which is intended to combine a binary logic signal (E,E') for transmission with the voltage (F,F') present on the single conductor. The voltage is able to take one of three levels at a given instant - either high, low or intermediate. The decoder is able to reconstitute on the output (S,S') the signal transmitted by the remote unit, operating in real time. Each unit includes a resistance (R1,R'1) to one terminal of which the binary logic signal is applied, whilst the other is connected to the single conductor (L). These resistances may be identical. Each decoding circuit includes a threshold comparator which receives the voltage present on the conductor.

Description

 The present invention relates generally to communication between two electrical or electronic components of a motor vehicle.

 In general, when a vehicle is equipped with an electronically controlled alternator and an engine operation management computer, two separate links must be provided between these two members; the first allows a binary logic signal, typically a rectangular signal, representative of the alternator's excitation rate to be sent from the alternator to the computer; the second makes it possible to route information, also logical, from the computer to the alternator (for example coded by pulse width modulation, delta modulation, etc.) representative of the voltage on which the regulation is to be carried out , or a required variation of this voltage.

 Thus Figure 1 of the accompanying drawings shows two members A, B both connected to ground and further connected together, for this communication, by two separate conductors L1 and L2.

 Furthermore, efforts are constantly being made to simplify and reduce the cost of on-board networks for motor vehicles by reducing the number or length of the various electrical connections that constitute it.

 However, insofar as this reduction in the number of conductors leads to a significant complication of the connected equipment, it loses its economic interest.

 The present invention aims to propose a communication system allowing two organs to exchange bidirectional logic information on the same conductor simultaneously, while keeping at each organ means of transmission-reception sufficiently simple and economical.

Thus the present invention proposes, according to a first aspect, a communication system between two electric or electronic members of a motor vehicle, both connected to a common potential such as the mass of the vehicle, system intended to circulate in a bidirectional simultaneous manner between said organs binary logical information having alternately a high level and a low level, characterized in that it comprises
a single conductor between the two organs,
in each member, a decoding circuit capable of combining a binary logic signal to be transmitted to the other member with the voltage present on the single conductor, said voltage being able to take, at a given instant, one of three levels, namely a level high, a low level and an intermediate level, so as to reconstitute as an output, in real time, the signal transmitted by the other organ.

Preferred, but not limiting, aspects of this system are as follows
each member comprises a resistor on a first terminal from which the binary logic signal to be transmitted to the other member is applied, and the other terminal of which is connected to said single conductor.

 - the values of the resistances in each of the two bodies are identical.

 - The decoding circuit comprises threshold comparator means receiving the voltage present on the single conductor.

 the comparator means are comparator means with two fixed thresholds, and the decoding circuit further comprises a logic circuit.

 the comparator means comprise two comparators delivering two logic signals, varying according to the value of the voltage present on the single conductor with respect to the two thresholds, and the logic circuit comprises a first gate receiving said logic signals delivered by the two comparators and delivering a output signal.

 the logic circuit comprises a second gate receiving the output signal from the first gate and the signal to be transmitted, and reconstituting at output the signal transmitted by the other member.

 the comparator means are comparator means with a single variable threshold, directly reconstructing the signal transmitted by the other member as an output.

 the single variable threshold is established using a divider bridge comprising two resistors connected in series between a voltage source and said common potential and a third resistance connected between the logic signal to be transmitted and the common point between said two resistors .

 the first member of the vehicle constitutes a regulator circuit for the charging voltage of a battery by an alternator, the second member of the vehicle constitutes a computer for managing the operation of the engine of the vehicle, the signal to be emitted by the first member is a signal representative of the alternator excitation rate, and the signal to be emitted by the second member is a signal representative of the voltage to be regulated or of a variation of the voltage to be regulated.

 - the high and low levels of binary logic information are respectively the battery voltage and the vehicle mass.

According to a second aspect, the invention proposes an electric or electronic member of a motor vehicle, connected to a reference potential such as the mass of the vehicle and intended to exchange bidirectional binary logic information with a member remote from said vehicle, characterized in that it includes
a terminal for the connection of a single connecting conductor with the distant member,
a resistor on a first end of which is applied a binary logic signal to be transmitted to the remote member, and the other end of which is connected to said connection terminal,
a decoding circuit able to combine the voltage present on the connection terminal with the signal to be transmitted, so as to reconstruct at output a signal transmitted by the distant member.

Preferred, but not limiting, aspects of this organ are as follows
- The decoding circuit also includes first means for detecting the cut of the single conductor.

 - The first detection means comprise means for combining the output signal from the decoding circuit and the signal to be transmitted, and a timer means.

 - The decoding circuit also includes second means for detecting the short-circuiting of the single conductor on the ground.

 - The second detection means comprise means for combining a signal supplied by the double threshold comparator means with the signal to be transmitted.

 - The decoding circuit also includes third means for detecting the short-circuiting of the single conductor on a positive potential.

 - The third detection means comprise means for combining a signal supplied by the double threshold comparator means with a signal derived from the signal to be transmitted.

Other aspects, aims and advantages of the present invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of example and made with reference to the accompanying drawings, in which
FIG. 1 is a general diagram of two electrical or electronic members connected according to the prior art by two conductors, in addition to the ground,
FIG. 2 is a general diagram of two electrical or electronic members connected according to the invention by a single conductor, in addition to the ground,
FIG. 3 is a block diagram of the assembly of FIG. 2, on which are illustrated decoding circuits of the two electrical or electronic members,
FIG. 4 is a detailed diagram of the coding-decoding circuit of one of the electrical or electronic organs,
FIG. 5 is a detailed diagram of a part of the decoding circuit according to an alternative embodiment of the invention,
FIG. 6 is a diagram of the circuit incorporating in its decoding circuit this variant embodiment of the invention, and
FIG. 7 represents a variant of part of the decoding circuit of FIG. 4.

 Referring first to Figure 2, there are illustrated two bodies A and B electrical, electronic or electromechanical of a motor vehicle.

 I1 can be for example, respectively, a regulation circuit provided on an alternator or in its vicinity to regulate the charging voltage of a battery by this alternator, and a computer intended for the electronic management of the engine vehicle thermal. These two members A and B are, conventionally, connected somewhere to the ground potential of the vehicle.

 According to the invention, and by means which will be explained below, these two computers can exchange binary type information, bidirectionally simultaneously, using a single-conductor link L.

 Referring now to FIG. 3, provision is made in each computer for a resistance, respectively R1 and R'1.

 In the computer A, the latter applies to a first terminal of the resistor R1 a binary logic signal to be transmitted, denoted E, while the other terminal of R1, denoted F (as well as the corresponding signal for reasons of convenience) is directly connected to a first end of the link L.

 Similarly, in the computer B, the latter applies to a first terminal of the resistor R'1 a binary logic signal to be transmitted, denoted E ', while the other terminal of R'1, denoted F' (likewise that the corresponding signal for convenience) is directly connected to the other end of the link L.

 It is understood that the values of F and F 'are permanently identical, except for the resistance of the bond (negligible).

Each signal E and E ′ can take, for example, a value equal to either zero volts or 5 volts, the corresponding logic values being denoted in the sequence "0" and ln,
Preferably, the ohmic values of R1 and R'1 are identical, without this being imperative.

Thus the link L is at a potential which varies according to the values of the signals E and E ', being able to take one of three values, and more precisely
if the signals E and E 'are at zero volts, then the signals F and F' are at the same value;
if the signals E and E 'are at 5 volts, then the signals F and F' are at the same value;
if one of the signals E and E 'is at zero volts, while the other is at 5 volts, then the signals F and F' are at 2.5 volts (the corresponding logic signal being noted "1 / 2fi) , the resistors R1 and R'1 playing the role of a divider bridge.

This can be summarized in the following table
EE 'F F'
OO 0 O
1 1 1 1
0 1 1/2 1/2
1 0 1/2 1/2
According to one aspect of the invention, a decoder circuit, respectively DEC and DEC ', which uses the value of the transmitted signal, E or E' respectively, is used in each computer A or B to decode the signal present on the link L ( point F or F ', respectively) and reconstruct the signal, E' or E, that the other computer sent.

More precisely, if we call S and S 'the signals decoded in the respective computers A and B, and If we wish to obtain S = E' and S '= E, then we see that for the computer A
S = E '= E if F = E
S = E '= E if F = 1/2
for computer B
S '= E = E' if F '= E'
S '= E = E' if F '= 1/2
Thus it is understood that by performing an appropriate logical combination of the signals E and F in the decoder DEC of the computer A, and E 'and F' in the decoder DEC 'of the computer B, it is possible to reconstruct the logic signal in real time emitted in the remote computer.

 FIG. 4 represents an example of a decoding circuit DEC of the computer A. An identical circuit is provided in the computer B.

 The three input resistors R2, R3, R4 constitute a divider bridge connected between a direct supply voltage Ualim, for example of +5 volts, and the ground.

 This bridge defines three voltage ranges, respectively U2, U3 and U4, making it possible to detect logic levels 1, 1/2 and 0 respectively.

Two operational amplifiers A1 and A2, mounted as comparators, receive on their non-inverting and inverting input respectively the voltage present on the link
L, i.e. at point F.

 The inverting input of Al is also connected to the common point between R2 and R3, while the non-inverting input of A2 is connected to the common point between R3 and R4.

A NOR gate designated by Norl receives on its two inputs the outputs Q1 and Q2 of Al and A2. The exit
Q3 of the door Norl is applied to an entry of a door
OU-EXCLUSIVE designated by Ouexl, the other input of which receives the signal E intended to be transmitted to the remote computer B via the resistor R1, as explained above.

 This Ouexl gate outputs the signal S.

The circuit part described above works as follows
- when the potential F of the link L is located in the range U3 (value F = 1/2), the output signals Q1 and Q2 of A1 and A2 are at logic level 0, and the output Q3 of Norl is therefore at logic level 1. I1 follows that the gate Ouexl plays the role of a logic inverter of the signal E, and we therefore obtain
S = E '= E
- when the potential F of the link L is located in one of the ranges U2 (value F = 1) and U4 (value F = 0), then one of the comparators Al and A2 has its output at logic level 1, while the other has its logical exit
O. The output Q3 of Norl is therefore at level 0, and the gate Ouexl therefore reproduces at its output the signal E. We therefore obtain
S = E '= E
Thus the circuit part as described above therefore allows, by combining the value of F with the value of
E, to reconstruct on its output S the value of E 'emitted in the remote computer.

 The circuit of FIG. 4 also includes means for managing certain degraded modes of operation, these means being intended to signal to the corresponding computer an anomaly.

 Thus the circuit firstly comprises a second OU-EXCLUSIVE gate Ouex2, one input of which receives the output signal from Ouexl and the other input of which receives the signal E.

 The output of Ouex2 attacks a reset input of a timer T1 constituted in this case by a logic counter clocked by a clock signal CK. One of the bits of the counter's parallel output is taken as the output signal Dl.

This part of the circuit makes it possible to detect a break in the single-wire connection L. In fact, during such a compure, the potential at point F is permanently reduced to a value practically equal to that of the potential of E via the resistor R1. In this case, we always have the relation
S = E.

 When this situation occurs, the output of gate Ouex2 remains permanently at zero, so that the timer T1 is never reset to zero and the counting therein ends up switching output D1 to logic level 1 .

 This transition to logic level 1, after the expiration of the timer, the value of which is chosen as a function of the rate of the mandatory level changes expected on the link L, therefore makes it possible to signal the computer when the link breaks.

 I1 is also provided a NAND gate designated by Nandl, intended to detect the fact that the link L is accidentally grounded.

 Thus the Nandl gate receives on an input the signal Q2 delivered by the comparator A2, and its other input the logic signal E.

 In the absence of a fault, F is at ground potential only if E and E 'are at logic level 0. In this case, the Nandl gate receives on an input the value Q2 equal to 1, and on the other input the value of E, equal to zero. Its output is therefore at 1.

When the line L is accidentally forced to ground, the signal Q2 remains permanently at the value 1, while the value of E can be either 0 or 1. As soon as the value of E is 1, the gate Nandl switches and delivers a zero value on its D2 output, which signals the short-circuiting on the earth of the link
L.

 Means are also provided for detecting the short-circuiting of the link L on a positive potential, for example on the voltage Ualim or on the voltage of the vehicle's on-board network, for example +12 volts.

For this purpose, a NAND gate Nand2 receives on an input the signal Q1 at the output of A1, and a logic inverter I4 applies to its other input the logic value of the signal
E after inversion.

 In the absence of a fault, F is at the potential included in the range U2 if and only if the values of E and E 'are both at 1. In this situation, the gate Nand2 receives on an input a value 1 (level of Q1) and on its other input a value zero (inverse of E), and outputs a value 1.

 If the fault exists, the level of Q1 remains at 1 even if the value of E goes to zero.

 In this situation, the Nandl gate receives a value 1 on each of its inputs, and its output D3 switches to the value zero, which signals the short-circuiting of the link L on a positive potential.

 Referring now to Figure 5, there is shown an alternative embodiment of the circuit part intended to produce the signals Q1 and Q2 as a function of the value of the voltage at point F.

 In this variant, the two comparators A1 and A2 are replaced by three logic inverters constituted by respective pairs of MOS transistors, respectively Mil, M12; M21, M22 and M31, M32.

 These inverters generally switch to a threshold value equal to half the supply voltage Ualim, and to obtain the two switching levels (the first between U2 and U3, and the second between U3 and U4), these thresholds are shifted tilting using resistors R21, R31, R32 and R41.

 Thus the pair of transistors M31, M32, which will form the inverse of the signal Q1, switches for a value equal for example to 2/3 of the voltage Ualim, while the pair of transistors M21, M22, which will directly form the signal Q2 , switches for a value equal to 1/3 of the voltage Ualim.

 To obtain these values, one can choose R21 and R41 equal to approximately 50 k0, and R31, R32 equal to approximately 16 kQ.

 The object of the pair of transistors Mil, M12 is to reverse the signal delivered by M31, M32 to form the signal Q1.

 FIG. 6 illustrates a decoding and degraded mode management circuit similar to that of FIG. 4, in which the circuit of FIG. 5 has been incorporated to replace the resistors R2 to R4 and the comparators A1 and A2, being represented with a simplified symbolism.

Thus the inverters I1, I2 and I3 in this figure correspond respectively to the pairs of transistors Mli,
M12; M21, M22 and M31, M32 in Figure 5.

 It will be observed here that, in order to improve the immunity of the circuits of the present invention with respect to disturbances, it is advantageous to supply the divider bridge R2, R3, R4 fixing the various voltage ranges under a higher voltage than 5 volts, and more particularly to supply it directly under the vehicle battery voltage (of the order of 14 volts), and this both in member A and in member B.

 The three voltage ranges are thus widened, to reduce the risks of false decoding, and the problems of voltage shifts likely to appear if the supplies specific to the two organs accidentally take too different values relative to one another. to the other.

 In this case, it is of course provided that the logic levels of the signals transmitted E and E 'are 0 volts (level 0 ") or 14 volts (level" 1 ").

 We will now describe with reference to FIG. 7 an alternative embodiment of the invention which makes it possible to further improve the reliability of the decoding, in particular in the case where the signals present on the single line L are strongly disturbed by wave components or if voltage shifts due to mass shifts occur.

 According to this variant, no longer uses a divider bridge R2, R3, R4 fixing three voltage ranges, but a divider bridge which will fix two voltage ranges; in this case, the transition level between the two voltage ranges will be varied as a function of the logic value of the signal (E or E ') emitted by the respective member.

 Thus, FIG. 7 shows a divider bridge constituted by two resistors Ril and R12 connected in series between a positive supply voltage Ualim and the ground. Preferably, here again, a voltage Ualim taken directly from the battery (approximately 14 volts) is used in the two members A and B. As before, the voltage ranges at the resistors Rîl and R12 are denoted Uli and U12 respectively.

 The circuit also includes a resistor R13 connected between the terminal of the signal E transmitted and the common point of the Roll divider bridge, R12. This common point is applied to the negative input of a comparator All, the positive input of which is connected to the terminal F via a protective resistor R14 which does not influence the level of the signal.

 As in the previous embodiments, we find the resistance R1 creating any voltage changes on the line L.

The comparator All outputs the decoded signal
S.

The values of the voltage ranges Uli and U12 are governed as follows
- if the voltage E is at level 1 (14 volts), then the divider bridge is defined by Ril and R13 in parallel, which fix the range Pull, and by R12 alone, which fixes the range U12; therefore, the ohmic value of Ril being reduced by putting R13 in parallel, the range Uli is reduced in favor of the range U12;
- If on the contrary the voltage E is at level "0" (0 volts), then the divider bridge is defined by Ril alone, which fixes the range Uiî, and by R12 and R13 in parallel, which fixes the range U12; therefore, the ohmic value of R12 being reduced by placing R13 in parallel, the range U12 is reduced in favor of the range Pull.

If for example we choose Ril = R12 = 33 kQ, and R13 = 18 kQ, then it is easy to verify by calculation that
- if E = 14 volts, then
Uîl = 3.65 volts and
U12 = 10.35 volts;
- if E = 0 volts, then
Uli = 10.35 volts and
U12 = 3.65 volts.

 It will be understood from reading the above that this result is equivalent in theory to that obtained with three resistors R2, R3 R4 defining ranges of respective voltages of 3.65 volts, 6.70 volts and 3.65 volts.

 However, insofar as, in all cases, the comparison is no longer carried out with a single threshold value, namely the transition point between the ranges Uli and U12, the risks of false detection are significantly reduced in signal disturbance present on line L.

 More specifically, the selective widening of one of the ranges as a function of the value of E makes it possible to accept without error large shifts in the voltages E and E 'applied in the two members (due to mass shifts or to wave components).

 Thus, in theory, if the values of Roll, R12 and R13 are such that U12 = 3.Ull (case where E = "1") or U11 = 3.U12 (case where E = "0"), and if l 'We keep the assumption of a power supply at 14 volts, so the comparison is carried out respectively on threshold values of 10.5 volts and 3.5 volts.

 It follows that the acceptable error on the signal F in the cases where E = E '= F = "1" n or E = E' = F = 81 "is 3.5 volts; or F being equal to ( E + E ') / 2 (assuming R1 = R'1), the maximum admissible error on the difference between E and E' is therefore 7 volts.

 Similarly, the acceptable error on F = 1/2 (which is normally 7 volts) in the case where E = o n and E '= "1" or in the opposite case is also 3.5 volts. It would therefore be necessary that the difference between E and E 'accidentally drops below 7 volts to perform an erroneous decoding.

 It will be noted here that the variant of FIG. 7 can be fitted either with only one of the members, or more advantageously with the two members.

 Of course, the present invention is not limited to the embodiments described and shown, but those skilled in the art will be able to make any variant or modification in accordance with his spirit.

Claims (25)

 1. Communication system between two electrical or electronic components (A, B) of a motor vehicle, both connected to a common potential such as the mass of the vehicle, system intended to circulate bidirectional information between said components simultaneously binary logic having alternately a high level and a low level, characterized in that it comprises  a single conductor (L) between the two bodies,  in each member, a decoding circuit (DEC, DEC ') capable of combining a binary logic signal (E, E') to be transmitted to the other member with the voltage (F, F ') present on the single conductor, said voltage which can take at any given time one of three levels, namely a high level, a low level and an intermediate level, so as to reconstruct at output (S, S '), in real time, the signal transmitted by l other organ.  2. System according to claim 1, characterized in that each member (A, B) comprises a resistor (R1, R'1) on a first terminal from which the binary logic signal to be transmitted to the other member is applied, and the other terminal of which is connected to said single conductor (L).  3. System according to claim 2, characterized in that the values of the resistances (R1, R'1) in each of the two members (A, B) are identical.  4. System according to one of claims 1 to 3, characterized in that the decoding circuit (DEC, DEC ') comprises threshold comparator means (Al, A2; I1-I3; All) receiving the voltage (F) present on the single conductor.  5. System according to claim 4, characterized in that the comparator means are comparator means (A1, A2; I1-I3) with two fixed thresholds, and in that the decoding circuit further comprises a logic circuit (Norl, Ouexl).  6. System according to claim 5, characterized in that the comparator means comprise two comparators (Al, A2) delivering two logic signals (Q1, Q2), varying according to the value of the voltage (F) present on the single conductor (L ) with respect to the two thresholds, and in that the logic circuit comprises a first gate (Norl) receiving said logic signals (Q1, Q2) delivered by the two comparators and delivering an output signal (Q3).  7. System according to claim 6, characterized in that the logic circuit comprises a second gate (Ouexl) receiving the output signal (Q3) from the first gate (Norl) and the signal to be transmitted (E), and reconstructing at output (S) the signal (E ') transmitted by the other organ.  8. System according to claim 4, characterized in that the comparator means are comparator means (All) with a single variable threshold, directly reconstructing at output (S) the signal (E ') transmitted by the other member.  9. System according to claim 8, characterized in that the single variable threshold is established using a divider bridge comprising two resistors (roll, R12) connected in series between a voltage source (Ualim) and said common potential and a third resistor (R13) connected between the logic signal (E) to be transmitted and the common point between said two resistors.  10. System according to one of claims 1 to 9, characterized in that the first member (A) of the vehicle constitutes a circuit for regulating the charging voltage of a battery by an alternator, in that the second member (B ) of the vehicle constitutes a computer for managing the operation of the thermal engine of the vehicle, in that the signal (E) to be transmitted by the first member is a signal representative of the excitation rate of the alternator, and in that the signal (E ') to be transmitted by the second member is a signal representative of the voltage to be regulated or of a variation of the voltage to be regulated.  11. System according to one of claims 1 to 10, characterized in that the high and low levels of the binary logic information (E, E ') are respectively the battery voltage and the vehicle mass.  12. Electric or electronic component (A; B) of a motor vehicle, connected to a reference potential such as the mass of the vehicle and intended to exchange bidirectional binary logic information (E; E ') with a component distant from said vehicle, characterized in that it comprises  a terminal (F) for the connection of a single conductor (L) for connection with the remote member,  a resistor (R1) on a first end of which is applied a binary logic signal (E) to be transmitted to the remote member, and the other end of which is connected to said connection terminal,  a decoding circuit (DEC) for combining the voltage present on the connection terminal with the signal to be transmitted, so as to reconstruct at output a signal transmitted by the distant member.  13. Device according to claim 12, characterized in that the decoding circuit (DEC, DEC ') comprises threshold comparator means (Al, A2; I1-I3; All) receiving the voltage (F) present on the single conductor .  14. Device according to claim 13, characterized in that the comparator means are comparator means (A1, A2; I1-I3) with two fixed thresholds, and in that the decoding circuit also comprises a logic circuit (Norl, Ouexl).  15. Body according to claim 14, characterized in that the comparator means comprise two comparators (Al, A2) delivering two logic signals (Q1, Q2), varying according to the value of the voltage (F) present on the single conductor (L ) with respect to the two thresholds, and in that the logic circuit comprises a first gate (Norl) receiving said logic signals delivered by the two comparators and delivering an output signal (Q3).  16. Device according to claim 15, characterized in that the logic circuit comprises a second gate (Ouexl) receiving the output signal (Q3) from the first gate (Norl) and the signal to be transmitted (E), and reconstituting at output (S) the signal (E ') transmitted by the other organ.  17. Component according to claim 13, characterized in that the comparator means are comparator means (All) with a single variable threshold, directly reconstructing at output (S) the signal (E ') transmitted by the remote member.  18. Device according to claim 17, characterized in that the single variable threshold is established using a divider bridge comprising two resistors (roll, R12) connected in series between a voltage source (Ualim) and said common potential and a third resistor (R13) connected between the logic signal to be transmitted (E) and the common point between said two resistors.  19. Device according to one of claims 12 to 18, characterized in that the decoding circuit also comprises first detection means (Ouex2, T1) of the cut of the single conductor (L).  20. Device according to claim 19, characterized in that the first detection means comprise means (Ouex2) for combining the output signal (S) of the decoding circuit and the signal to be transmitted (E), and a timer means ( T1).  21. Body according to one of claims 12 to 20, characterized in that the decoding circuit also comprises second detection means (Nandl) of the short-circuiting of the single conductor (L) on the ground.  22. Body according to claim 21 taken in combination with one of claims 14 to 16, characterized in that the second detection means comprise means (Nandl) for combining a signal (Q2) supplied by the double threshold comparator means with the signal to be transmitted (E).  23. Body according to one of claims 12 to 22, characterized in that the decoding circuit also comprises third means of detection (Nand2) of the short-circuiting of the single conductor (L) on a positive potential.  24. Body according to claim 23 taken in combination with one of claims 14 to 16, characterized in that the third detection means comprise means (Nand2) for combining a signal (Q1) supplied by the comparator means with a signal (E) derived from the signal to be transmitted.  25. Device according to one of claims 12 to 24, characterized in that the high and low levels of the binary logic information are respectively the battery voltage and the mass of the vehicle.