FR2745101A1 - INSTALLATION FOR RESETTING A CALCULATION ELEMENT - Google Patents

Abstract

Installation forming part of a control installation capable of being started and of being stopped, comprising a circuit applying at least one reset signal to the computing element. The circuit is connected to a supply voltage which cannot be cut off when the control installation is shut down and the circuit applies to the computing element at least one reset signal at a time in an undelayed manner and in a delayed manner.

Description

State of the art: The invention relates to an installation for

put back

  in the initial state a calculation element forming part of an ins-

  control unit capable of being switched on and off, comprising a circuit applying at least one

  reset signal to the compute element.

  According to document DE-A-42 20 247, an installation for controlling the drive motor of a motor vehicle is known, comprising at least two calculation elements. For

  guarantee the operability of the

  However, the first calculation element is monitored by the second.

  In addition, the computing elements are provided with their own facilities to monitor their operation, for example

  example of "watchdog" circuits. For such com-

  electronic drive motor commands, in the event of

  failure of at least one of the calculation elements, a reset signal is generated which resets one or both of the calculation elements to the initial state and restarts them at zero. In addition, reset signals are generated in

  in case of undervoltage or when the supply voltage is connected

  tion. Similarly, it is planned to cut off, in the event of a fault, a power element from the output stage controlling the group

vehicle drive.

  According to document DE-A-37 00 986 (US-A-4 881 227), in connection with a system with two computers, it is known that computers exchange reset signals

  initial and "watchdog" signals through

  diary of a logic circuit. In addition, a reset signal is generated when the voltage is connected.

  power supply and this signal is applied to the two computers.

  The reset signal when the power supply is connected, the reset signal from each other computer, and the output signal from its "watchdog" circuit are combined in one single reset signal

  the initial state of a computer via a circuit

  cooked logical. The means which go beyond, in particular for the combination over time of these reset signals, their realization and the guarantee of their availability,

are not offered.

  The object of the present invention is to create an

  tallation to reset a calculation element, which combines efficiently, without the need for a circuit

  bearing, the reset signals from different sources

  férentes. To this end, the invention relates to an installation characterized in that the circuit is connected to a supply voltage which cannot be cut off when the control installation is stopped, and the circuit applies to the element of calculation of at least one reset signal at the

  both non-delayed and delayed.

  According to other advantageous characteristics of the invention: - the circuit consists of at least two AND logic gates, - the installation comprises at least two calculation elements, the second calculation element generating a reset signal to

  the initial state for the first calculation element and the first

  mier calculation element generating a reset signal for the second calculation element,

  - the circuit includes at least two AND gates, the first

  receiving the reset signals for the applications

  quer by its output, as an undelayed reset signal

  the initial state, to the calculation element, and this signal is also

  Lely applied with delay to the input of the second AND gate, the output of which provides a delayed reset signal for the calculation element, - the delay is made by an RC element, for an own error , the calculation element emits a reset signal which locks both the stages

  corresponding output power, and returns to the initial state

tial the second element of calculation,

  - the installation includes a voltage regulator for

  ter the control system with a stabilized voltage which generates a reset signal in the event of

  undervoltage or when switching on, this signal

  initialization being applied to the calculation element on the one hand in an undelayed manner and on the other hand in a delayed manner, - the control installation is a control installation

  to control the driving power of a vehicle

  tomobile, comprising a first calculation element and a second calculation element monitoring the first element, the power control being effected by an output stage adjustment element, - the circuit is an AND-quadruple gate in integrated circuit, in CMOS technique, - the output circuit can be locked and activated by at least one calculation element, the corresponding signal being

also applied to the circuit.

Advantages of the invention:

  The solution according to the invention constitutes an installation

  lation to reset a calculation element,

  allowing to combine in a predetermined way the different

  annuity reset signals from sources

  different, and without increasing the circuits implemented.

  Availability is improved by supplying one of the circuits processing the reset signals, by a permanent supply independent of the running and stopping of the calculation elements. This guarantees optimum operation of the control installation equipped with the

  calculation, even during connection or disconnection.

  It is particularly advantageous to use

  commercial HCMOS components which have a very high

  operating safety and consume little current

(only a few gA).

  The use of integrated components reduces before-

  carefully the number of components, the cost and the size.

  The solution of the invention is therefore particularly suitable

  for highly integrated control units.

  It is particularly advantageous to use the solution of the invention in the case of a power control unit of a drive unit, in particular of a

  internal combustion engine, comprising two elements of cal-

  ass, namely a function computer and a safety computer which monitors it. In this context, it is advantageous

  that the solution of the invention makes it possible to provide the calcula-

  function tester, two reset signals at

  from a reset signal, the first if

  general used as a warning signal to introduce

  corresponding backup programs and the other signal, re-

  delayed, triggering the actual reset operation and the new start in the function computer. Drawings:

  The present invention will be described below in detail.

  in more detail using embodiments shown

  schematically in the accompanying drawings in which: - Figure 1 is an overall diagram, by blocks, of a control unit of a drive unit corresponding to a preferred embodiment; Figure 2 shows the solution of the invention using an example circuit; and - Figures 3 to 5 show the operation of the circuit to

using chronograms.

  Description of the exemplary embodiments:

  Figure 1 shows a control unit 10 of the

  power of a motor vehicle drive unit.

  The control installation 10 includes two microcomputers

  12, 14 independent, connected by a bus 16 for reciprocal exchange

  of information and data. The input lines 18-20 which may be part of the bus system 16 supply the microcomputer 12 with the operating parameters of the drive unit and / or of the vehicle, from the measurement installations 22-24. These operating parameters represent for example the speed of rotation of the engine, a quantity for the load of the engine, the position of the accelerator pedal, the

  position of the power group setting element

  drag etc. In addition, the microcomputer 12 receives via a line 26 a stabilized supply voltage supplied by a

voltage regulator 28.

  The voltage regulator 28 is connected by the line and the ignition key 32 actuated by the driver, to the pole

  positive 34 of the vehicle on-board network. By at least one li-

  output 36 and a power stage 38, the micro-

  computer 12 controls, via the output line 40 of the installation

  control lation 10, an adjusting element 42 influencing the power of the engine; in the preferred embodiment

  tiel, this adjustment element is the throttle flap of the mo-

internal combustion engine.

  The second microcomputer 14 is also powered.

  ted by the voltage regulator 28, by a line 44, with a

  stabilized supply voltage. In addition, the micro-

  computer 14 receives through input lines 46-48 which make

  also part of the bus system 16, metering installations

  on 50-52, the operating parameters of the

  drag and / or vehicle. These operating parameters,

  and thus the measuring installations according to the example of realization

  preferential position, are partly identical to those of the micro-

  computer 12. Thus, in the preferred embodiment example-

  tiel, the microcomputer 14 receives the position of the accelerator pedal (the driver's instruction) and the position of

  the power adjusting element 42 for overtaking purposes

  vigilance. A circuit 54 is further provided for coordinating the reset operations. Circuit 54 receives a first line 56 and a second line 58 from the regulator.

  voltage 28 as well as one or more lines 60, 62 of the micro-

  computers 14 and 12. By the first line, a supply voltage

  switched (5V, from terminal 15 via line 30)

  applied, while line 58 receives the supply current

  tion of a permanent positive supply (5V, positive terminal

  30 by the second link from regulator 28 to the positive pole

  tif). The output lines of circuit 54 consist of a line 64 to the power stage 38 as well as lines

  to microcomputers 12 and 14; these lines are schemati-

  entered by the double arrows on lines 60 and 62. In a preferred embodiment, the microcomputers 12

  and 14 are also connected to permanent positive poles.

  In normal operation, the microcomputer 12

  command, according to the driver's instruction deducted from the posi-

  acceleration pedal and if necessary according to other operating parameters, the power of the power unit in the direction of the driver's instruction. Using selected operating parameters and internal quantities, the microcomputer 14 controls the operation of the microcomputer.

  computer 12 and, in the event of a recognized fault in the micro-

  computer 12, generates a reset signal for the microcomputer 12 as well as a signal for locking the output stage 38. Furthermore, the microcomputer 12 comprises at least one "watchdog" system internal which controls the internal operation of the microprocessor 12. When this circuit recognizes a fault in the microcomputer 12, it generates a reset signal which resets

  the initial state not only the microcomputer 12 but also

  the microcomputer 14, and locks the power stage 54. The microcomputer 14 correspondingly generates, when it recognizes an internal fault, reset and locking signals for the microcomputer computer 12

  and the power stage 54. In addition, when the ins

  control unit or in the event of undervoltage, provision is made for the voltage regulator 28 to generate a corresponding reset signal transmitted by line 54 to microcomputers 12 and 14 and the stage of power 54.25 FIG. 2 shows the circuit 54 corresponding to a preferred exemplary embodiment shown in more detail. We use a component 100 comprising four doors

  AND logic. By its VCC connection, component 100 is re-

  linked to the permanent supply voltage VSTBY of the installation

  ordering; by its GND connection, it is connected to ground. The first AND logic gate 100a is connected to a line 101 of the voltage regulator 28 which transmits the signal RESET of undervoltage and of resetting to the initial state when the power supply is connected; from the microprocessor 12 leaves an input line 102 used by the reset signal RSTOUTFR from the microcomputer 12 in the event of an internal error or malfunction. The output line 104 of the first

  AND logic gate 100a is connected to the RSTINSR input of the micro-

  computer 14. Line 106 connects line 101 to the first

  second door entrance AND 100b. Its second entry is re-

  linked to line 108 of microprocessor 14 which transmits the

  general reset SWRSTSR of the microcomputer 14 in the event of an internal fault or malfunction. The output of this AND gate is a line 110 connected to the NMIFR input of the microcomputer 12. A resistor R1 is connected

  between line 110 and capacitor Cl, to ground. In-

  tre resistor R1 and capacitor Ci, there is a line 112 connected to the two inputs of the third AND gate 100c. The output line 114 of this door is connected to the RSTINFR input of the

  microcomputer 12. The fourth AND logic gate 100d comprises, as input lines, line 116 coming from line 104 as well as a line 118 coming from the output ESENSR of the microcomputer.

  computer 14 conducting a locking signal for the power stage in the event of a fault. The output line of the qua-

  third gate AND 120 is connected to the ESV input of the output stage circuit 38. According to the preferred embodiment, the

  component 100 is a CMOS integrated circuit for example the

  standard HCMOS standard 74HC08.

  When the ignition is switched on, the voltage regulator

  sion 28 generates a RESET signal as in the case of an undervoltage. In the example of realization

  preferential, the signal level of the output line of the

  voltage regulator 28 thus passes from a high value to a low value (see FIG. 3a). This "reset to initial state during start-up" or this reset signal for undervoltage, triggers, via the second AND gate and line 110, a change of level at the NMIFR input of the microcomputer 12 (see also FIG. 3b). This signal is used by the microcomputer 12 to signal a reset which will occur after a predetermined time delay. The microcomputer 12 thus has the possibility

  to execute important programs. The realization of the time-

  Porization is ensured by the RC mounting which transmits to the

  generates a signal varying from high to low level. The delay of this signal variation in the RC element makes it active, via line 112, at the third junction

  AND, with delay, to have an alternation of signal level on line 114 compared to the alternation of signal level on line 110, with time delay (see figure 3c) .5 The change of signal level on line 114 triggers the mid-reset operation itself

  computer 12, that is to say the resetting of the microcomputer and a new start-up (new initialization). The "reset to initialization on start-up" 10 or the reset signal for undervoltage also leads, via line 101, to a change in level of

  signal on line 104, that is to say the output line of the first AND gate. This generates a corresponding signal variation in line 120 via line 11615 for the fourth AND gate (see FIG. 3e); which opens up

  rust on the output stage. In addition, the change in signal level on line 104 is applied directly to the RSTINSR input of the microcomputer 14 (see FIG. 3d) which is reset to

  the initial state to be restarted.

  In addition to "reset to initialization" or reset to initial state in the event of under-

  voltage, in the preferred control installation, on the basis of the monitoring which is carried out, the microcomputer 14 generates a reset signal in the event of

  implausible carrying of the microcomputer 12 or if there is a specific error. Via the SWRSTR exit and line 108, a signal

  corresponding is applied by a change in level of if-

  generally passing from high to low level (see figure 4a). This signal is applied to the second AND gate which generates the non-delayed NMIFR pre-warning signal (figure 4b) and the delayed reset signal described above RSTINFR for the microcomputer 12 (see figure 4c ). A change of

  signal level corresponding to the microphone's ESENSR output

  computer 14, ensures the unlocking of the output stage

  through the fourth AND gate and line 120 (see Figure 4d).

  Another possibility to return to the original state

  tial the control installation, is that of a fault state directly in the microcomputer 12. When the "watchdog" circuit of this microcomputer or the monitoring of

  functioning integrated in this microcomputer, notes a

  necessary, the microcomputer generates a corresponding signal of re-

  initialization. This is issued by the RSTOUTSR output to reset the function computer (see Figure 5a). The output signal is applied to the first AND gate which generates, through its output line 114, a change

  signal level at both the RSTINSR input of the microphone

  computer 14 and on line 116 for the fourth AND gate (see Figures 5b and 5c). Signal level change

  at the input RSTINSR returns the microcomputer 14 to the initial state

  tial; the change in signal level on the fourth door

  AND locks, via line 120, the output stage 38.

  The locking of the output stage at the end of the reset and initialization sequences, by a corresponding change in the signal level on the reset lines of the microcomputer or of the regulator

  of tension, is then released again.

  For all initialization operations

  components triggered, the microcomputer 12 re-

  receive a first reset signal without delay

  as a pre-warning signal and a delayed

  cond signal constituting the actual reset signal, which triggers the reset and a new start. The duration of the AT delay is set

  by the time constant of the element RC consisting of the re-

  resistance R1 and of the capacitor Cl. According to an example of realization

  preferential tion, there is a time delay of 10 gsec.

  Instead of delaying the NMIFR signal by the AND gate, according to an advantageous embodiment, we

  directly switches the NMIFR signal by an RC element or sim-

  by a buffer circuit, to apply it to the input of

reset.

R E V E N D I CATIONS

  1) Installation to reset an element of

  calculation as part of a susceptible control installation

  ble to be started and stopped, including a circuit

  cooked applying at least one reset signal to the calculating element, characterized in that the circuit is connected to a supply voltage which cannot be cut when the control installation is stopped , and the circuit applies at least one reset signal to the calculation element both in an undelayed manner and

delayed way.

  ) Installation according to claim 1, characterized in that

  the circuit consists of at least two AND logic gates.

  ) Installation according to one of the preceding claims,

  characterized in that the installation comprises at least two calculation elements, the second calculation element generating a reset signal for the first calculation element and the first calculation element generating a reset signal initial state for the

second element of calculation.

  4) Installation according to one of the preceding claims,

characterized in that

  the circuit comprises at least two AND gates, the first receiving

  to reset signals to apply them

  by its output, as an undelayed reset signal

  tial, to the compute element, and this signal is also applied

  that delayed with the input of the second AND gate whose output provides a reset signal, delayed,

for the calculation element.

   ) Installation according to claim 4, characterized in that

  timing is made by an RC element.

  6) Installation according to any one of the pre- claims

  cédentes, characterized in that for its own error, the calculating element emits a reset signal which locks both the corresponding output power stages, and resets

the second element of calculation.

  7) Installation according to one of the preceding claims,

  characterized in that the installation includes a voltage regulator for supplying

  the control system with a stabilized voltage which

  generates a reset signal in the event of under-

  voltage or during start-up, this reset signal being applied to the calculation element on the one hand

  not delayed and secondly delayed.

  8) Installation according to any one of the pre- claims

  cédentes, characterized in that the control installation is a control installation

  to control the driving power of a motor vehicle

  mobile, comprising a first calculation element and a second calculation element monitoring the first element, the power control being effected by a stage adjustment element

Release.

  9) Installation according to any one of the pre- claims

  cédentes, characterized in that the circuit is an AND-quadruple gate in integrated circuit, in

CMOS technique.

   ) Installation according to any one of the claims

  previous, characterized in that the output circuit can be locked and activated by at

  minus a calculation element, the corresponding signal also being

applied to the circuit.