FR2738682A1 - MOS integrated circuit active protection method for overvoltage protection - Google Patents

Abstract

The IC (15) is protected against overvoltages (+Vp) applied to first (12) and second (GND) conductors which are connected respectively to the drain (D) and source (S) of the IGFET (10). The control signal is applied to the gate (G) and a parallel parasitic bipolar transistor (14) becomes conducting when the control signal is active and non-conducting when it is inactive. The inactive level is approximately equal to the second conductor voltage and the active level lies between the inactive level and the first conductor voltage. The comparator (16) comprises a zener diode (Z), a resistive element (R1, R2) and one or more diodes (D). A variant of the invention has two such protective circuits in parallel.

Description

PROTECTION AGAINST OVERVOLTAGES
The present invention relates to a surge protection circuit used to protect MOS integrated circuits from high voltages applied to external pads.

 In the present description, reference will be made to MOS transistors because it is the term commonly used to designate any field effect transistor with insulated gate, not only those having in the literal sense a structure of the metaloxide-semiconductor type. It will be noted that the present invention and the present description generally relate to any type of insulated gate field effect transistor and not only those having a metal-oxide-semiconductor type structure.

 The very small dimensions of common MOS devices, such as the thickness of the gate insulator and the junction depth, mean that these devices are very sensitive to high voltages. Overvoltage protection circuits, also called voltage limiters, used to protect MOS devices must be able to react to electrostatic discharges of a few kilovolts applied to an integrated circuit and discharge the high voltage applied to ground, by limiting the voltage on the MOS integrated circuit at a safe level. It is known in such circuits to use a field effect transistor, the drain of which is connected to an external pad and the source to ground voltage. The protection circuits are integrated into the same integrated circuit as the MOS circuit to be protected. Conventional field effect transistors can be used, but it is preferred to use active transistors, that is to say transistors having layers d relatively thin grid insulation, as they react faster.

FIG. 1 represents an N-channel field effect transistor 10 used as a protection device against overvoltages. Its drain region D is connected to an external pad 12, maintained at a positive voltage + Vp. Its substrate or well connection B, its source region S and its gate electrode
G are connected to each other and to ground voltage
GND. Lightly doped regions (LDD) 13 are provided on the channel side of the source S and drain D regions, in accordance with current practice in the manufacture of MOS integrated circuits.

A MOS circuit 15 to be protected is connected to the drain D of the field effect transistor 10.

 An NPN parasitic bipolar transistor 14 exists in parallel on the field effect transistor. Its emitter corresponds to the source of the field effect transistor, its collector to the drain of the field effect transistor and its base to the substrate of the field effect transistor.

 Figure 2 shows an equivalent electrical diagram.

 Under the indicated polarization conditions, a substrate current Ib flows from the drain D to the substrate or well connection B. This current is the reverse bias leakage current from the drain-substrate junction of the field effect transistor. It increases by avalanche multiplication in response to an increase in the voltage + Vp applied to the external pad 12. The substrate current Ib, combined with the inherent resistance of the substrate, causes the appearance of a potential difference between the connection of substrate B and the semiconductor in the source region S. If the external voltage + Vp and therefore the substrate current Ib increase enough to raise the potential of the substrate in the source region above the direct voltage of the substrate junction -source, this junction is polarized live.

 Then, the parasitic bipolar transistor 14 becomes conductive and the source S and the drain D of the field effect transistor 10 are effectively connected to each other. The voltage at which this occurs is called the rollover voltage. The voltage + Vp on the external pad 12 drops to a lower value, called the reversal holding voltage, and the associated circuit 15 is protected from the high voltages applied.

 The parasitic bipolar transistor 14 is turned on for a higher voltage than the voltage which the transistors of an MOS integrated circuit can withstand. For current MOS integrated circuits, this voltage is close to 13 V for a typical transistor with a channel length of 0.5 μm. This threshold level protects circuits such as integrated circuit input and output amplifiers which are designed to withstand voltages of this level but is too high to protect more sensitive internal circuits from conventional MOS integrated circuits compared overvoltages.

For example, MOS circuits often contain transistors which have a length of less than 0.5 µm and a thickness of gate insulator of about 10 nm. Such transistors will be damaged by voltages of the order of 12 volts, generally at their drain-substrate junction.

 The invention aims to provide an efficient overvoltage limiting circuit which becomes active at lower voltages than those of conventional overvoltage limiting circuits.

 The invention further aims to provide such a circuit which limits the electrostatic discharge voltages of several kilovolts to safe levels for application to MOS devices.

 The invention further aims to provide such a circuit which becomes active before damage to any element of the circuit to be protected.

To achieve these objects, the present invention provides a method of protecting an integrated circuit against excessive values of a voltage + Vp applied between first and second conductors, comprising the following steps
produce a control signal at an inactive level when said voltage is lower than a predetermined level,
producing a control signal at an active level when said voltage exceeds the predetermined level, the control signal coming from said voltage,
applying the control signal to a gate terminal of an insulated gate field effect transistor, having its drain and source connected to the first and second conductors, respectively; a parasitic bipolar transistor inherently connected in parallel on the insulated gate field effect transistor becoming conductive for a level of protection of said voltage when the control signal is at its active level, and remaining non-conductive at the level of protection of said voltage when the control signal is at its inactive level.

 According to an embodiment of the present invention, the inactive level is substantially equal to the voltage of the second conductor.

 According to an embodiment of the present invention, the active level is between the inactive level and said voltage.

 The present invention also provides a protection circuit for protecting an integrated circuit from excessively high values of a voltage + Vp applied between first and second conductors of the integrated circuit, this protection circuit comprising a field effect transistor with insulated gate connected by its drain and its source, respectively, between the first and second conductors; a comparator for comparing said voltage with a reference voltage and for consequently supplying a control signal to the gate terminal of the transistor, at an active level when said voltage exceeds the reference voltage, and at an inactive level in other cases ; a parasitic bipolar transistor inherently connected in parallel to the insulated gate field effect transistor; the active level of the control signal being at a voltage chosen to bring the parasitic bipolar transistor into conduction for a level of protection of said voltage; the parasitic bipolar transistor remaining non-conductive for the level of protection of said voltage when the control signal is at its inactive level.

 According to an embodiment of the present invention, the first conductor is at a more positive voltage than the second conductor.

 According to an embodiment of the present invention, the inactive level is substantially equal to the voltage of the second conductor.

 According to an embodiment of the present invention, the active level is between the inactive level and said voltage.

 According to an embodiment of the present invention, the comparator comprises, between the first and second conductors, the series connection of at least one Zener diode and a resistive element.

 According to an embodiment of the present invention, the comparator comprises, between the first and second conductors, the series connection of at least one Zener diode, a resistive element, and one or more diodes.

These objects, characteristics and advantages as well as others of the invention will appear in more detail in the following description of particular embodiments given in relation, by way of nonlimiting example, with the attached figures, among which
Figures 1 and 2, described above, represent a device for protection against overvoltages according to the prior art
FIG. 3 represents the reversal characteristics of a typical N-channel MOS transistor
FIG. 4 represents a device for protection against overvoltages according to the invention;
FIG. 5 represents a particular embodiment of a device for protection against overvoltages according to the present invention
FIG. 6 represents a possible configuration of a protection transistor;
FIG. 7 represents a simulated timing diagram of certain voltages of the circuit according to an embodiment of the invention, after having been subjected to an electrostatic discharge (ESD);
Figure 8 shows a second embodiment of the present invention;
FIG. 9 represents a simulated timing diagram of certain voltages appearing in the circuit of FIG. 8 after having been subjected to an electrostatic discharge;
FIGS. 10A to 10E show various types of Zener diodes intended for use in integrated circuits, in top view and in section; and
Figures 11 and 12 are simulated timing diagrams of certain voltages of the circuit according to an embodiment of the invention, after occurrence of an electrostatic discharge.

 FIG. 3 represents the inversion characteristics of a typical N-channel field effect transistor, with a channel length of 0.5 μm and of the active type, that is to say with a small thickness of insulator grid, for different grid polarizations Vg.

 Reversal is a phenomenon that occurs in MOS transistors for drain-source voltages higher than the usual voltages, when the parasitic bipolar transistor in parallel with the MOS transistor becomes conductive. When this occurs, for the turn-over voltage, the drain-source voltage drops rapidly to a turn-around holding voltage, and the drain current Id flowing in the transistor increases rapidly.

 It can be seen that for a gate polarization Vg = 0, the reversing voltage VtrO is greater than 12 V. The reversing holding voltage is approximately 7.5 V. For such weak gate polarizations, the current drain-substrate of the transistor is weak. When the gate voltages Vg applied are increased, the turning-over voltage decreases.

A minimum reversal voltage Vtr3 is obtained in this case for a gate voltage Vg of approximately 3 volts. For higher values of the gate voltage, the rollover voltage increases again. This is due to the reduction of the field strength at the drain junction of the field effect transistor.

 The present invention provides a protective field effect transistor with optimal gate polarization during electrostatic or other overload, to allow the reversal to take place for a desired value + Vp. This desired value can typically be close to 7 volts.

FIG. 4 schematically represents a circuit according to the present invention. An external pad 12 is connected to a drain connection D of a protection transistor 10 which is an N-channel MOS transistor. The drain D and the pad 12 are connected to the circuit 15 to be protected. The source S and substrate B terminals of the transistor 10 are connected to each other and to ground.
GND. There is an NPN parasitic bipolar transistor 14 in parallel on the MOS transistor 10. According to the invention, there is provided a comparator 16 having a non-inverting input connected to the pad 12 and an inverting input connected to a determined reference voltage Vr by a required level of protection, as described below.

 The external stud is typically a pin of a box containing the integrated circuit to be protected. These external pins can undergo electrostatic discharges due for example to improper handling.

The comparator 16 compares the level of the pad voltage + Vp to the reference voltage Vr. If this comparison shows that the voltage of the external pad, + Vp, exceeds the reference voltage Vr, the comparator will apply a gate bias voltage Vg of predetermined value to the gate G, thus reducing the turn-on voltage of the transistor at field effect 10 at a required level determined by the value of the gate polarization Vg. For rapid operation, the gate polarization value must be adjusted so that the reversal voltage, in the presence of the gate polarization, is less than the reference value Vr. Thus, as soon as the plot voltage + Vp exceeds the reference voltage
Vr, the gate polarization will be applied, the reversal will take place and the protection device will immediately take action. In this case the protection voltage level is equal to the reference voltage Vr, and the protection becomes active when + Vp reaches the Vr value.

 The reversal leads to the connection of the pad 12 to the ground voltage GND. The reference voltage Vr must be chosen to correspond to the required protection voltage level. This typically corresponds to about 7 V for common CMOS, 0.5 µm dies. The smallest voltage against which one can protect oneself depends on the smallest possible reversal voltage of the field effect transistor 10 used as a protection device. In the particular example of FIG. 3, the lowest possible turning-over voltage is 7 V. Using this as the reference voltage value, as soon as the pad voltage exceeds 7 V, the gate polarization chosen Vg (in this example a gate polarization of 3 V) will be applied to the field effect transistor 10 and gives a protection level of 7 V.

 If the chosen reference voltage Vr is lower than the corresponding turning-over voltage, the protection device will act only after the voltage + Vp has increased until the turning-over voltage of transistor 10 for the gate voltage Vg applied. The level of protection then corresponds to the turning-over voltage.

 FIG. 5 illustrates a possible practical embodiment of the voltage clipping circuit according to the invention. The comparator 16 consists of a Zener diode Z, two resistors R1, R2 and a diode D connected in series between the external pad 12 and the GND ground. The other characteristics are identical to those described in connection with FIG. 4 and bear the same references.

The reference voltage Vr of this comparator is then determined by the Zener voltage of the Zener diode Z, the direct voltage drop of the diode D, and the values of the resistors R1 and R2 while they conduct the reverse leakage current of the Zener Z diode. Using conventional manufacturing methods, the Zener Z diode may include a lightly doped region such as regions corresponding to lightly doped drains (LDD). This produces very low leakage current Zener diodes. Since the overvoltage discharges through transistor 10, the Zener Z diode can be small (e.g. 10 µm x 10 pin). The power dissipated in the diode
Zener is reduced by choosing relatively high values for R1 and R2 (a few kilo-ohms).

 Since the overvoltage discharge current flows mainly in the parasitic bipolar transistor 14, the transistor 10 can have a short channel length, which saves the surface of the integrated circuit and also leads to a lower conduction voltage for the parasitic bipolar transistor (that is to say the voltage for turning over the field effect transistor). The difference between the turning-over voltage and the holding voltage depends essentially on the gain of the parasitic bipolar transistor.

This gain is increased by providing a short base region, that is to say a short channel length of the MOS transistor, and the high gain results in a low reversal holding voltage, which leads to low power dissipation. in the device.

Depending on the level of protection required, the values of
R1, R2 can be set, and one and / or the other of these resistors can be omitted, in the same way as the diode D.

Additional diodes can be added in series with diode D, each increasing the reference voltage Vr by an amount equal to its forward voltage drop.

 When a high voltage + Vp is applied to the external stud 12, of a value higher than the reference voltage, a current begins to flow in the Zener diode Z, the resistors R1, R2 and the diode D towards the ground GND. The voltage Vg on the gate of the field effect transistor will depend on the value of the resistor R2 and the current flowing there, offset by the direct voltage drop of the diode D. In any usual technology, there is usually only one type of Zener diode available. The choice of a possible addition of one or more diodes D and the values R1 and R2 will be made accordingly to obtain the required gate voltage.

 The values of R1, R2, D, Z must be chosen so that a gate bias capable of providing a minimum value of the reversal voltage (in the example of FIG. 3, approximately 3 V) is obtained at from the voltage + Vp when the Zener Z diode becomes conductive. The minimum turn-over voltage and the corresponding gate voltage are characteristics of a given field effect transistor and can be determined from a graph like the one in Figure 3. The values of resistors R1 and R2 must be chosen to ensure that the gate G is not maintained at a high level of polarization Vg, once the parasitic bipolar transistor has become conductive.

 The efficiency of the circuit according to the invention is determined by the performance with respect to the electrostatic discharges of the field effect transistor 10. The voltage Vd at the terminals of the transistor 10, 14 depends on the series resistance in the inversion mode . This is inversely proportional to the width of the transistor and varies with the length of the transistor. We must therefore choose a transistor of minimum length with a very wide channel region. This channel region typically has a width of a few hundred micrometers and a length of less than 0.5 pin and can take the form of a digested transistor. When the gate is polarized at the moment when the transistor enters the inversion mode, all the fingers of the transistor enter simultaneously the inversion mode, for the same gate and drain voltages Vg, Vd.

This effect is described in "Dynamic gate coupling of
NMOS for efficient output ESD protection "IEEE / IRPS Proceedings 1992, P. 141-150. All the parts of the transistor thus function in an identical way, from where it results that the performances with respect to electrostatic discharges are directly proportional to the width of the transistor.

 FIG. 6 shows, in top view, a possible configuration of a digital field effect transistor adapted to the circuit according to the invention. A gate electrode G has the shape of a two-sided comb, source and drain regions S and D alternating between the teeth of the comb and being arranged so that each source region S on one side of the comb is adjacent and opposite to a drain region, and vice versa.

All parts of the comb have an identical width L, which is the channel length of this digested transistor. The dimension L can be close to 0.5 pin. The effective width of this digitized transistor is the sum of the widths of the horizontal parts (illustrated by an arrow Wh in the figure) and all the widths of the vertical portions (illustrated by an arrow Wv in the figure)
To test ESD devices, we use a so-called human body model. This includes a 100 pF capacitor in series with a resistance of 1.5 kQ. This model is charged to appropriate high voltages and discharged to the device to be tested.

 FIG. 7 represents the result of such an ESD test on the circuit according to the invention, using a load of 4 kV. The protection transistor used had a width of 300 pin and a length of 0.5 pin, the Zener diode Z had a Zener voltage of 7 V, and we had R1 = 3 kQ and R2 = 0 Q.

 A maximum drain voltage Vd of approximately 9.5 V is reached approximately 1 ns after the start of the application of the high voltage. This peak corresponds to the conduction of the parasitic bipolar transistor 14. The drain voltage Vd then drops suddenly below 8 V due to the sudden increase in conductivity of the bipolar transistor but then continues to increase as a result of the increase of the current in the bipolar transistor 14 and of its series resistance. The maximum drain voltage Vd never exceeds 12 V and begins to drop while the human body model capacitor discharges through the bipolar transistor 14 to ground GND.

 The gate voltage Vg is also shown.

This rises to 3 volts after 1 ns from the start of the discharge, which corresponds to the conduction of the bipolar transistor 14. The gate voltage then drops as a result of the conduction of the bipolar transistor, reducing the voltage between the pad 12 and the GND ground. The subsequent increase in current in the bipolar transistor combined with the series resistance of the bipolar transistor increases the voltage + Vp of the pad 12 to put the Zener Z diode Z back into conduction approximately 3 ns after the application of the high voltage. The gate voltage Vg is determined by the resistors R1 and R2 and the number of diodes D. As shown in the figure, the gate polarization Vg never rises above 5 V. Considering Figure 3, we sees that the reversal voltage of the transistor for a Vg of 5 V is still lower than that which exists for Vg = 0 volt.

 More effective surge protection can be achieved by using two or more protection systems in parallel. This is electrically equivalent to multiplying the width of the field effect transistor 10. For a large MOS integrated circuit, several protection circuits such as that of FIG. 5 should be placed at various locations in the circuit. If this were not done, the interconnection resistance between the various points of the circuit could cause the appearance of voltages exceeding the safety level in certain parts of the circuit. FIG. 8 represents a circuit including two protection systems in parallel, each protection system being identical to that of FIG. 5. Identical characteristics to those of FIG. 5 bear identical references, those of the second protection system bearing a suffix at. More than two protection systems could of course be used. The field effect transistors 10, 10a do not share the same comparator circuit 16, 16a since the protection systems can be distributed at different locations of the MOS integrated circuit to be protected.

 FIG. 9 represents the drain and gate voltages as a function of time for a model discharge of the human body of 8 kV, with two protection systems in parallel, as described in relation to FIG. 8. It can be seen that, for the drain voltage Vd and the gate voltage Vg, there are two peaks which correspond to the two instants of activation of the protection systems. The first protection system goes into conduction and, after an initial fall, the gate Vg and drain Vd voltages begin to increase due to the series resistance of the bipolar transistor, as indicated above, until that the drain voltage Vd increases enough so that the second protection system also comes in conduction.

A sequence similar to that previously described causes an increase in the gate voltages Vg and drain
Vd, at the gate and the drain, and the applied high voltage + Vp discharges. As shown in the example in FIG. 9, the drain voltage never exceeds 12 V. The MOS circuit protected by the structure according to the invention is therefore not damaged, even by an 8 kV discharge.

 This achieves the main objects of the invention.

FIGS. 10A to 10E represent various possible physical embodiments of a Zener diode in a technology
Classic CMOS.

 As shown in section and in plan view, respectively in FIGS. 10A and 10C, the Zener diode required for the circuit according to the invention can be formed from a concentric configuration of a heavily doped P + type region 34 ; a lightly doped N-type LDD 36 region; and of a heavily doped N + type region 38 in an N 39 well on a P type substrate. These regions can correspond to source and drain implantations of P channel transistors; implantation of a lightly doped drain (LDD) of type N; and to source and drain implantations of N-channel transistors, all formed in a conventional N-type well. This constitutes the preferred type of Zener diode for the embodiment comprising a MOS transistor without LDD implantation.

An additional masking step is required to separate the type N or type P LDD implant from the implants
+ + N or P source and drain.

FIGS. 10B and 10D show respectively in cross-section and in top view a variant of Zener diode which could be used in the circuit according to the invention. This Zener diode can be formed from a concentric configuration of a heavily doped P + type region 34; of a lightly doped region of type P i and of a heavily doped region of type N in a well of type N on a substrate of type P. These regions can correspond to the implantations of source and drain of transistors to P channel; a P-type lightly doped drain implantation (LDD); and the implantation of source and drain of N channel transistors, all formed in a conventional N box on a type substrate
P.Inserting the Zener diode into a box of the type opposite to the substrate is necessary to isolate the Zener diode from other components of the integrated circuit. The Zener diode could also be formed in a P box on a type N substrate.

FIG. 10E represents, in section, a typical Zener diode produced in CMOS technology. A heavily doped N-type region 42, corresponding for example to the source and drain implantation of an N-channel MOS transistor, is adjacent to a heavily doped P-type region 44, corresponding for example to source implantations and drain a transistor
P-channel MOS This type of Zener diode typically has doping densities of around 1020 atoms / cm3 in regions 42 and 44 and a Zener voltage of around 5 V. By placing two heavily doped regions in the vicinity on the other, a significant leakage current results, under normal polarization conditions. The Zener diode of FIG. 10E cannot therefore be used in the circuit according to the invention because its leakage current would cause an unacceptable leakage from the pad 12 to ground.

 A thin-gate N-channel MOS transistor with LDD is very sensitive to a high-voltage stress from its gate insulator, mainly due to the presence of the LDD regions under the gate electrode.

 To obtain a more robust protection device, a MOS transistor without LDD can be used. This particular type of transistor is fabricated using all conventional steps, including in particular the formation of spacers adjacent to the gate electrode before the formation of the drain and source regions. It follows from these spacers that there is a semiconductor region on both sides of the gate electrode which is neither part of the drain region nor of the source region and which cannot be part of a channel inversion when a grid bias is applied. Consequently, this type of transistor can never form a channel between the source and the drain. The use of such a transistor in a circuit according to the invention to protect the input or output signal pads avoids the problems associated with the conduction of the channel by capacitive coupling of the gate of the MOS transistor.

Such MOS transistors without LDD implantation are described in "Suppression of soft failures in a submicron CMOS
Process "EOS / ESD Symposium Proceedings, 1993, page 117.

 This article also explains that transistors without LDD implantation are less susceptible to damage by repeated overvoltages than corresponding transistors with LDD implantation.

 A faster activation of the protection system is obtained by adding a dynamic effect to an improved embodiment of the circuit according to the invention which can be achieved by increasing the surface of the Zener Zode diode. This increases the capacity of the Zener diode when it is non-conductive and provides dynamic protection against overvoltages.

 If a brutal voltage pulse is applied to pad 12, this pulse will be transmitted by the capacitance of the Zener diode Z to the gate G of the transistor 10. Thus, the gate is polarized very quickly, even before the Zener Z diode is become a driver. This means that, firstly, a channel can be formed in the MOS transistor to start discharging the increasing voltage before it reaches the minimum reversal threshold voltage and, secondly, the gate is biased as soon as possible, so that the rollover occurs as soon as the applied voltage reaches the minimum rollover voltage.

However, this embodiment of the protection circuit occupies a larger area of the integrated circuit. This embodiment reacts faster than the previous embodiment. The response characteristic of such a circuit to applied voltage pulses depends on its time constant
RC which is the product of the capacitance of the Zener diode by the total resistance of R1 and R2.

 Figures 11 and 12 show the improvement in characteristics caused by the use of a high capacity Zener Z diode ensuring dynamic protection against overvoltages. FIG. 11 represents the drain voltages Vd and of the gate Vg of the field effect transistor in the circuit according to the invention with a Zener diode of 9 V of 300 um2, during a discharge of a load of 4 kV on a model of human body. (Here the Zener surface is chosen to be the product of the length and the width of the lightly doped region, 36, 40 in Figures 10A and 10B, respectively). The initial peak drain voltage Vd reaches a value of 13 volts. This may be enough to damage the MOS circuit connected to the protection device.

Using the same circuit and the same discharge voltage, but with a Zener diode of 600 pin2, we obtain the characteristic of figure 12. The maximum drain voltage
Vd when the Zener diode is turned on does not exceed 9 volts. Protection is therefore ensured.

 The use of LDD implants in Zener diodes can entail that a more complex or equivalent photographic masking step must be introduced during the LDD implantation steps.

 By using this masking step, the field effect transistor can be formed without LDD implantation, described above. The removal of the LDD implantations does not affect the level or the variation of the turning-over voltage used to make the parasitic bipolar transistor conductive.

 Although the invention has been described with reference to a limited number of particular embodiments, many variants will appear to those skilled in the art. In particular, the comparator circuit 16 can be constituted in any suitable way, provided that a very rapid response to an applied overvoltage can be ensured.

 The invention has been described in the form of a surge protection circuit, but finds applications in any MOS circuit in which a maximum voltage level must be respected. The circuit can therefore be used in any application where a voltage limiter is required in an integrated circuit of the MOS type.

 Although the invention has been described only with reference to N-channel protective MOS transistors, similar operation can be achieved by using a corresponding P-channel MOS transistor and reversing the polarity of all voltages and all doping.

Claims (9)

 1. Method for protecting an integrated circuit (15) against excessive values of a voltage (+ Vp) applied between first (12) and second (GND) conductors, comprising the following steps  produce a control signal (Vg) at an inactive level when said voltage is lower than a predetermined level,  producing a control signal at an active level when said voltage exceeds the predetermined level, the control signal coming from said voltage,  applying the control signal to a gate terminal (G) of an insulated gate field effect transistor (10), having its drain (D) and its source (S) connected to the first and second conductors, respectively; a parasitic bipolar transistor (14) inherently connected in parallel to the insulated gate field effect transistor becoming conductive for a level of protection of said voltage when the control signal is at its active level, and remaining non-conductive at protection level of said voltage when the control signal is at its inactive level.  2. Method according to claim 1, wherein the inactive level is substantially equal to the voltage of the second conductor.  3. Method according to claim 1, in which the active level is between the inactive level and said voltage (+ Vp).  4. Protection circuit for protecting an integrated circuit (15) of excessively high values of a voltage (+ Vp) applied between first and second conductors of the integrated circuit, this protection circuit comprising  an insulated gate field effect transistor (10) connected by its drain and its source, respectively, between the first and second conductors, characterized in that it further comprises  a comparator (16) for comparing said voltage (+ Vp) with a reference voltage (Vr) and for consequently supplying a control signal (Vg) to the gate terminal of the transistor, at an active level when said voltage (+ Vp) exceeds the reference voltage, and at an inactive level in other cases  a parasitic bipolar transistor (14) inherently connected in parallel on the insulated gate field effect transistor;  the active level of the control signal being at a voltage chosen to bring the parasitic bipolar transistor in conduction for a level of protection of said voltage (+ Vp); the parasitic bipolar transistor remaining non-conductive for the level of protection of said voltage when the control signal is at its inactive level.  5. The circuit of claim 4, wherein the first conductor is at a more positive voltage (+ Vp) than the second conductor.  6. The circuit of claim 4, wherein the inactive level is substantially equal to the voltage of the second conductor.  7. The circuit of claim 4, wherein the active level is between the inactive level and said voltage (+ Vp).  8. The circuit of claim 4, wherein the comparator comprises, between the first and second conductors, the series connection of at least  a Zener diode (Z), and  a resistive element (R1, R2).  9. The circuit of claim 4, wherein the comparator comprises, between the first and second conductors, the series connection of at least  a Zener diode (Z),  a resistive element (R1, R2), and  one or more diodes (D).