FR2729528A1 - Digital multiplexer circuit e.g. for clock control system - Google Patents

Abstract

The digital multiplexer (CM) includes a number of multiplex switching stages (1,2,3) which are fed by a digital word (N0-N7) source (S1). Each multiplex stage reduces the number of multiplex switches by a factor of 2. Each multiplex switch is controlled by a clock frequency (f) from a clock (H). Separate clock controlled command signals (C1-C4, C02, C13, C0213) are sent to each multiplex switch, with the repetition rate of the command decreasing with each stage and with the command effecting multiplexing. Phase offsets are also introduced from stage to stage.

Description

 The present invention relates to a multiplexing circuit for selecting and routing binary signals from several different inputs to an output.

 More particularly, the invention relates to multiplexing circuits intended to route multiple input signals having an output in a defined and unchanging order to an output.

 Figures 1 and 2 of the accompanying drawings show, as a typical example of the prior art, a 1: 8 MUX multiplexing circuit making it possible to cyclically deliver a binary signal among eight applied to the inputs NO to N7, on an output OUT in function of the state of three control inputs SO, S1 and S2.

 Multiplexing circuits of this kind are generally produced by means of a "tree" of elementary multiplexers or 2: 1 switches, each stage of this "tree" being controlled by one of the bits of the control signal.

So, in the example in Figure 2, the first floor
El comprises four elementary multiplexers delivering the variables QO to Q3 and controlled simultaneously by the signal
SO, a second stage E2 comprising two elementary multiplexers controlled simultaneously by the signal S1 and delivering the variables Q02 and Q13, and a third stage E3 controlled by the signal S2 and delivering the output variable
OUT.

 The advantage of these multiplexing circuits is that the output signals can be presented in any order, which is the case, for example, when several processing units have to be selectively connected to a bus. However, they have the drawback of accumulating the processing times of the stages of the circuit, so that the total transition time which elapses between the appearance of a signal at the output, is equal to the sum of the transition times. elementary multiplexers. Therefore, this total delay is relatively long, especially if the number of entries is large.

 However, in many cases, the sources to be multiplexed present their data in an order that is immutable and well defined. I1 is thus for example, when coefficients or commands must be selected in N tables of a memory, during the parallel-series conversion of data or when digital modules resulting from a parallelization are used. If in these cases, a multiplexing circuit designed according to FIGS. 1 and 2 described above is used, the time elapsing between the moment when the data appear at the input, and the moment when they appear at the output , becomes a major drawback.

 However, it has been found that for these cases, it is possible to overcome the drawbacks caused by the delay in question.

 The object of the invention is therefore to provide a multiplexing circuit intended to process input signals having a defined and unchanging order and making it possible to produce an output signal whose binary elements are spaced apart in time only in length. the working time of its top floor.

The invention therefore relates to a multiplexing circuit comprising in combination:
a data source intended to supply 2N binary data to be multiplexed, said data being presented in a predetermined fixed order,
a clock for delivering a plurality of control signals from a clock frequency, and
a tree-type multiplexer intended to multiplex said 2N data, where N is any integer, said multiplexer comprising N stages of switches 2 :: 1 with switches whose number decreases from 2N to 21 of stage d input from said multiplexer to the output stage, said turnouts being selectively controlled from one state to another by said control signals to ensure the transfer of said data through said multiplexer, this circuit being characterized in that in each stage , the points are controlled in sequence by said control signals and in that the frequency of said control signals decreases from one stage to another by a factor of two counted from the output to the input of said multiplexer.

Other characteristics and advantages of the invention will become apparent during the description which follows, given solely by way of example and made with reference to the appended drawings in which:
- Figure 1 is a basic diagram of a multiplexer according to the prior art;
- Figure 2 is a more detailed diagram of the multiplexer shown in Figure 1;
- Figure 3 shows a diagram of a multiplexer according to the invention;
- Figure 4 is a time diagram illustrating the operation of the multiplexer according to Figure 3;
- Figure 5 shows a diagram illustrating how a piece of data progresses in the multiplexer shown in Figure 3;
- Figures 6A to 6H are diagrams of the progression of the data considered at each of the periods of a work cycle of the multiplexer according to the invention;
- Figures 7A and 7B show the operation of a 2: 1 switch used in this multiplexer;
- Figure 8 is a diagram of a 16: 1 multiplexer produced according to the concepts of the invention;
- Figure 9 is a diagram of an application of the invention to a data extraction system from eight tables or memories connected in parallel;
FIG. 10 illustrates another application of the multiplexer according to the invention in a system constituting a converter of parallel data into serial data;
- Figure 11 shows a diagram of a shift register using the concepts of the invention;
- Figures 12A, 12B and 12C illustrate the application of the invention to a fast synchronous counter.

 We will first refer to FIGS. 3 to 7B to examine a first example of a multiplexing circuit CM according to the invention. This circuit comprises in combination a source S1 of signals to be multiplexed, a multiplexer N: l (N = 8 in this example) generally designated by M1, and a clock circuit H intended to supply control signals for the source S1 and the multiplexer M1.

 This comprises three stages 1, 2 and 3 composed in the order of four, two and a switch 2: 1 respectively carrying the references la to Id, 2a and 2b, and 3a. The switches 1a to 1d respectively receive the input data No-N4, N2-N6, N1-N5 and N3-N7 from the source S1 and supply the intermediate data Qo, Q2, Q1 and Q3 in order.

 These intermediate data are applied to the switches 2a and 2b of stage 2 which deliver the intermediate data Q02 and Q13. These are applied to the switch 3a of the last stage which in turn delivers the output signal OUT of the multiplexer.

 The data NO to N7 are presented to the multiplexer M1 always in the same order which, as will be seen below, is the case for many applications in which the invention can be used.

According to an important aspect of the invention, each 2: 1 switch forming part of the multiplexer M1 is controlled by its own control signal supplied by the clock H, this signal being different from the control signals applied to the other switches. In addition, these signals are:
a) increasing frequencies from the input stage to the output stage;
b) in each stage, phase shifted with respect to each other by a half-period of the control signal of the last stage.

FIG. 4 shows a time diagram illustrating the operation of the multiplexer M1 of FIG. 3 and in particular the time relationships of the control signals. We see that these are derived from a clock frequency f having a period 6 and supplied by the clock H associated with the multiplexer. This frequency f is divided several times by two, the result of the first division forming the control signal C0213 for the switch 3a, that of the second division the control signals C02 and
C13 for switches 2a and 2b, etc. It can also be seen that the control signals of the same stage are out of phase with respect to each other in period 6, except obviously the last.

 I1 results from this particular command that the multiplexer M1 delivers an output signal OUT derived, in order, from the input data at the rate of the period 6 of the clock signal f. The frequency of the output signal OUT is therefore equal to this clock frequency, the period of which must be adapted to the sole transition delay of the switch 3a of the last stage 3 of the multiplexer. In other words, only the delay of the last switch limits the working frequency at the output of the multiplexer according to the invention.

 It is true that each data item must wait for a complete work cycle T from the multiplexer, but this is not a problem since, since the data NO to N7 arrive in a well defined order, it suffices to wait for the processing of a complete series of input data before new data on the same input can begin to pass through the multiplexer.

 FIG. 5 shows how the data NO passes through the multiplexer M1 towards the output OUT. During the times t0 to t3, the control signal CO is at 1 so that the turnout la is on for the data item N4, but blocks the data item NO. During times t4 and t5, the control signal CO is at zero so that the turnout la is on for the datum NO, but blocks the datum N4. This switch therefore produces the signal QO which will be blocked by switch 2a, the control signal C02 being at zero. On the other hand, during times t4 and t5, the switch 2a is on for the signal Q2 which is delivered by the switch lb and represents the input data N6. This switch delivers the signal Q02.

 At time t6, the switch 2a also becomes on for the data NO under the control of the signal C02 which goes to zero. The data NO therefore appears in the form of the signal 002 at the output of the switch 2a. But during this time t6, the switch 3a is still blocked for this signal Q02. it lets through the signal Q13 coming from the switch 2b which then transmits the data N7.

 At time t7, the switch 3a turns on for the signal Q02 and therefore transmits the state of the data NO on the output OUT of the multiplexer under the control of the signal C0123 which is then zero.

 FIGS. 6A to 6H summarize the states of the switches and the passages of the data NO to N7 through them respectively during the times t0 to t7. In these figures, the horizontal segments represent the switches and the oblique segments symbolize the passing state of the switch of the upstream stage. It can be seen that the multiplexer provides an output signal at each clock stroke of the frequency f and that this data passing frequency is reduced each time by half, from the highest stage to the lowest stage.

 FIGS. 7A and 7B illustrate the operation of each switch of the multiplexer M1. I1 receives two input data Ni and Nj for which it becomes transparent respectively for the high and low states of a control signal Cij. Consequently, as seen in FIG. 7B, when a Ni or Nj data is present on the corresponding input of the circuit (time tn for the Ni data and time tn + l for the Nj data), the signal transition command passes any of these data to the Qij output.

 FIG. 8 shows an N: 1 multiplexer according to the invention in which N = 16. Consequently, this multiplexer which is designated by M2, has an additional stage compared to the embodiment which has just been described. More precisely, this multiplexer M2 has four stages 10, 11, 12 and 13 whose switches are divided into two groups, namely an even group P and an odd group I, with the exception of the output switch 13 which works alternately on group P or on group I. In the drawing, these groups are surrounded by mixed lines. Each of them comprises a multiplexing circuit identical to the multiplexer M1 shown in FIG. 3, the control being carried out as shown in FIG. 4.

Consequently, there are in FIG. 8 references identical to those used in FIG. 3 to designate the equivalent turnouts.

Of course, the control of the switch of the stage 13 is carried out using a frequency 2f double the frequency f used to control each of the groups P and
I. Furthermore, this multiplexer M2 is associated with a signal source and with a clock in a manner similar to that shown in FIG. 3, although these circuits are not represented in FIG. 8.

 In FIG. 8, it can also be seen that the input data NO to N16 are distributed into two groups, respectively even and odd, the data of each group being themselves distributed as the data applied to the multiplexer M1 of FIG. 3.

 FIG. 9 shows a first application of the multiplexer according to the invention to the production of a look-up table.

 This circuit comprises a plurality of multiplexers conforming to that of FIG. 3 arranged in parallel to be able to work on a number b of bits in parallel, in other words on binary words having the width b. We therefore find in Figure 9 the representation of a multiplexer of Figure 3 with the same reference numerals that must be represented extended in a direction perpendicular to the drawing plane. The width of the words processed (in other words the number b) can be arbitrary. The assembly thus designed (called complex multiplexer) is designated by the general reference M3 and in FIG. 9, it is surrounded by dashed lines.

 The multiplexer M3 is connected to a source S2 of signals to be multiplexed. More specifically, the switches 1a to 1d of all the stages 1 of the complex multiplexer M3 are respectively connected in parallel to memories 21A to 21H. Each of these memories cooperates with an address counter 22A at 22H. The memories 21A to 21H are loaded with data stored at addresses specific to each data. These addresses are managed by the counters 22A to 22H.

 It can be seen in FIG. 9 that the memories and the address counters which are associated with them are divided into two groups, respectively even P and odd I which are surrounded by dotted lines. Each of these groups is controlled alternately with the other group by the control signals CO to C3 and the control signals CO to C3.

 Referring to the time diagram in FIG. 3 (which applies to the operation of the table to consult in FIG. 9), it will be noted that, for example with regard to the data NO, the address of the word instruction to be read in the register 21A, is loaded into the counter 22A at time t0, while the word itself is read in the memory 22A during the times tO to t3, then the bits of the word progress in parallel in the multiplexer M3 complex to the OUT exit. The same process takes place for all the other words loaded into the registers at the appropriate times determined by the control signals CO to C3.

 The memories 21A to 21H are read at the frequency f / 8 and there is therefore a latency time before the data arrive at the output OUT. It should be noted, however, that this output provides the data at frequency f and that there is only a single switching delay between the rising edge of the signal and the appearance of data at the output OUT.

 FIG. 10 shows another application of the multiplexing circuit according to the invention to a parallel-series converter. This comprises a multiplexer identical to the multiplexer M1 in FIG. 3. The input data NO to N7 of this multiplexer come from a source S3 composed of a group of flip-flops D 31A to 31H which are connected to a register 32 intended to receive a binary word of b bits, b being equal to eight in the example shown. Of course, like the multiplexer M2 of FIG. 8, it will be possible to process words having any number of bits, for example sixteen, if the multiplexer of FIG. 8 is used.

The loading flip-flops 31A to 31H are divided into two groups P and I assigned respectively to the even data NO, N2, N4, N6 and odd N1, N3, N5, N7 processed by the multiplexer M1. Register 32 is loaded on the rising edge of the CO signal. Because of their speed of operation, the control of the loading scales does not need to be synchronous with the change of state of the turnout to which it transmits the data stored in the corresponding cell of the register 32. For example, with regard to the data NO, the control of the flip-flop 31A can intervene on the rising edge of the control signal
C2 (see FIG. 4), that is to say two periods of the clock signal later than the moment when the switch becomes transparent for the data NO. Likewise, the loading flip-flop 31B is controlled on the falling edge of the control signal C2, in other words two periods of the clock signal later than the switch lb becomes transparent for the data N4 which comes from cell 4 of the register 32. Furthermore, the loading flip-flop 31E which loads the data N1 is also controlled on the rising edge of the control signal C2 which falls a period before the switch lc is made transparent for the data N1.

 The example of application of the invention which has just been described shows that according to this application, the data having to pass through the multiplexer M1 can be presented to it at times which do not necessarily coincide with the switching moments of the switches from one state to another.

 FIG. 11 shows another example of a multiplexing circuit according to the invention. This example relates to a parallel shift register comprising a multiplexer M1 identical to that of FIG. 3. The inputs of the latter receive the data NO to N7 from a source S4 comprising eight sections or registers 33A to 33H each composed of a certain number of flip-flops of type D. These registers 33A to 33H receive in parallel a data stream on a single entry D 34. The registers 33A to 33H are controlled by the control signals CO to C3 and their complements at the rate of f / 8 (see figure 4).

 The advantage of this arrangement lies in the fact that only the first flip-flops D of the registers 33A to 33H and the switch 3a of the stage 3 of the multiplexer M1 must be able to work at the frequency f, assuming that this is also the frequency of the input signal D on terminal 34. Although this arrangement according to the invention cannot operate at a higher frequency compared to that of a conventional shift register of this type, it provides the advantage of consume much less energy since most of its components work at significantly lower frequencies.

 We will now refer to FIGS. 12A to 12C which represent another application of the multiplexing circuit according to the invention to a synchronous counter.

In the example, this is a parallel counter by sixteen.

 The signals CO to C3 and CO to C3 having the frequency f / 8 and coming from the clock H (not shown in this figure) are applied respectively to eight counters per n 35A to 35H with a width of four bits each (n = 2 in this example). This assembly forms the signal source S5 of this multiplexing circuit.

 The multiplexer M3 proper is similar to that of FIG. 9, the number of bits b being equal to four.

Each counter 35A at 35H passes between two states eight apart, as shown in the counting graph in FIG. 12C. The states of each counter appear in the rectangles which symbolize them in FIGS. 12A and 12B.

 This particular arrangement of the counters makes them particularly simple. Indeed, as shown more particularly in FIG. 12B as regards the counters 35A and 35B only (but the assembly is similar for all the counters), each of these comprises a divider by two 36 which according to the binary numbers that '' it is responsible for processing, is associated with four outputs (marked bit 1 to bit 4 in Figure 12C), two of which are formed by the true output and the output supplemented by the divider by two 36, and of which the other two are connected respectively as the case may be, at the positive supply terminal or at the opposite supply terminal, for example ground.

 This example shows once again that the delay of this counter is only determined by that of the last switch of the multiplexer M3 which, of course, here has a width of four bits. Compared to a non-parallel synchronous counter, that of FIGS. 12A to 12C is therefore much faster, because in the conventional counter, at each clock tick, a delay composed not only of the delay of the flip-flops of the registers must be taken into account, but also the delay of the combinatorial circuit of the counter.

 It has been found that a double counting speed can be obtained with the counter according to the invention compared to conventional counters, which therefore makes it possible, for the same counting speed, to lower the consumption and the voltage of food.

Claims (7)

 1. Multiplexing circuit comprising in combination:  a source (S1 to S5) intended to supply 2 binary data (NO to N7) to be multiplexed, said data being presented in a predetermined fixed order,  a clock (H) for delivering from a clock frequency (f) a plurality of control signals (CO to C3, C02, C13, C0213), and  a tree type multiplexer (M1 to M3) intended for multiplexing said data, where N is any integer, said multiplexer (M1 to M3) comprising N stages (1, 2, 3) of switches 2 :: 1 with points (la to ld, 2a, 2b, 3a) whose number decreases from 2N to 21 from the input stage of said multiplexer to the output stage, said points (la to ld, 2a, 2b, 3a) being selectively controlled from one state to another by said control signals (CO to C3, C02, C13, C0213) to ensure the transfer of said data (NO to N7) through said multiplexer (M1 to M3), this circuit being characterized in that in each stage (1, 2, 3), the switches (la to ld, 2a, 2b, 3a) are controlled in sequence by said control signals (CO to C3, C02, C13, C0213 ) and in that the frequency of said control signals decreases from one stage to another (1, 2, 3) by a factor of two counted from the output to the input of said multiplexer (M1 to M3).  2. Multiplexing circuit according to claim 1, characterized in that said multiplexer (M1, M2) is divided into two sections (P, I) one even and the other odd each each comprising a tree set of switches (the at ld, 2a, 2b) distributed in stages (10, 11), in that said sections (P, I) are connected to said source (S1 to S5) so as to receive the even and odd input data from them respectively (NO to N6; N1 to N7 or NO to N14; N1 to N15) in the order of their appearance, and in that the outputs of said sections (P, I) are connected to a common switch (3a, 13) which is alternately made transparent for the data coming from said even section (P) and from said odd section (I).  3. Multiplexing circuit according to any one of claims 1 and 2, characterized in that said data source (S1 to S5) is arranged to supply said data in the form of binary words of bit width (b) predetermined and in that each of said turnouts (la to ld, 2a, 2b, 3a) has a bit width adapted to said predetermined width.  4. Multiplexing circuit according to any one of the preceding claims, characterized in that it forms a table to be consulted and in that said source (S2) comprises memories (21A to 21H) intended to be loaded with data and address counters (22A to 22H) for controlling the reading of said data, from their address in said memories (21A to 21H) and in that said address counters are controlled with the control signals (CO to C3 , CO to C3) which are used to control the corresponding turnouts (la to ld) of the first stage (1) of said multiplexer (M3).  5. Multiplexing circuit according to any one of claims 1 to 3, characterized in that it forms a parallel-series converter and in that said source (S3) comprises a data register to be converted (32) loaded at the frequency (CO) of the first stage (1) of said multiplexer (M1) and the cells of which are respectively connected to locking circuits (31A to 31H) intended to supply said data (NO to N7) to the multiplexer under the control of said signals command (C0, C2, CO to C2).  6. Multiplexing circuit according to any one of claims 1 to 3, characterized in that it forms a shift register and in that said data source (S4) comprises as many registers (33A to 33H) as it there are data inputs (NO to N7) of said multiplexer, these registers being intended to store binary signals coming from a common input (34) providing data in series, said registers being respectively connected to the inputs of said multiplexer (M1 ), while the progression of the data in these registers is controlled respectively by the same control signals (CO to C3; CO to C3) and their complements which control the switches (la to ld) of the first stage of said multiplexer (M1).  7. Multiplexing circuit according to any one of claims 1 to 3, characterized in that it forms a synchronous counter and in that said data source (S5) comprises as many counters per n (35A to 35H) as there are inputs of said multiplexer (M3), in that the counting inputs of said counters are controlled by the same control signals (CO to C3; CO to C3) which control the switches (la to ld) of the first stage of said multiplexer (M3), and in that said counters by n (35A to 35H) count at a distance from each other equal to half the capacity of said synchronous counter.