FR2729498A1 - Procede de determination du seuil du debit de dose d'une irradiation capable de perturber une memoire - Google Patents

Procede de determination du seuil du debit de dose d'une irradiation capable de perturber une memoire Download PDF

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Publication number
FR2729498A1
FR2729498A1 FR9500565A FR9500565A FR2729498A1 FR 2729498 A1 FR2729498 A1 FR 2729498A1 FR 9500565 A FR9500565 A FR 9500565A FR 9500565 A FR9500565 A FR 9500565A FR 2729498 A1 FR2729498 A1 FR 2729498A1
Authority
FR
France
Prior art keywords
memory
content
state
dose rate
cells
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR9500565A
Other languages
English (en)
French (fr)
Other versions
FR2729498B1 (enrdf_load_stackoverflow
Inventor
Ronan Marec
Patrick Mary
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Direction General de lArmement DGA
Gouvernement de la Republique Francaise
Original Assignee
Delegation Generale pour lArmement
Gouvernement de la Republique Francaise
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Delegation Generale pour lArmement, Gouvernement de la Republique Francaise filed Critical Delegation Generale pour lArmement
Priority to FR9500565A priority Critical patent/FR2729498A1/fr
Publication of FR2729498A1 publication Critical patent/FR2729498A1/fr
Application granted granted Critical
Publication of FR2729498B1 publication Critical patent/FR2729498B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/005—Circuit means for protection against loss of information of semiconductor storage devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5002—Characteristic

Landscapes

  • Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
FR9500565A 1995-01-17 1995-01-17 Procede de determination du seuil du debit de dose d'une irradiation capable de perturber une memoire Granted FR2729498A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9500565A FR2729498A1 (fr) 1995-01-17 1995-01-17 Procede de determination du seuil du debit de dose d'une irradiation capable de perturber une memoire

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9500565A FR2729498A1 (fr) 1995-01-17 1995-01-17 Procede de determination du seuil du debit de dose d'une irradiation capable de perturber une memoire

Publications (2)

Publication Number Publication Date
FR2729498A1 true FR2729498A1 (fr) 1996-07-19
FR2729498B1 FR2729498B1 (enrdf_load_stackoverflow) 1997-03-07

Family

ID=9475274

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9500565A Granted FR2729498A1 (fr) 1995-01-17 1995-01-17 Procede de determination du seuil du debit de dose d'une irradiation capable de perturber une memoire

Country Status (1)

Country Link
FR (1) FR2729498A1 (enrdf_load_stackoverflow)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157335A (en) * 1989-08-18 1992-10-20 Houston Theodore W On-chip error detection circuit
EP0601392A2 (de) * 1992-12-08 1994-06-15 Siemens Aktiengesellschaft Verfahren zum Testen des Übersprechverhaltens von digitalen Speichern

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5157335A (en) * 1989-08-18 1992-10-20 Houston Theodore W On-chip error detection circuit
EP0601392A2 (de) * 1992-12-08 1994-06-15 Siemens Aktiengesellschaft Verfahren zum Testen des Übersprechverhaltens von digitalen Speichern

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
"SHADOW RAM CELL AND SHADOW RAM", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 33, no. 3B, NEW YORK US, pages 439 - 440, XP000124414 *
PASSOW ET AL: "CHARACTERISATION SUMMERY FOR A RADIATION HARDENED 16Kx1 SRAM", IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 33, no. 6, NEW YORK US, pages 1535 - 1540 *
SHIMANO ET AL: "THE MEASUREMENT AND PREDICTION OF PROTON UPSET", IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 36, no. 6, NEW YORK US, pages 2344 - 2348, XP000102559 *

Also Published As

Publication number Publication date
FR2729498B1 (enrdf_load_stackoverflow) 1997-03-07

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