FR2723495A1 - Echo suppression device for two coupled transmission channels - Google Patents

Abstract

The device includes a circuit which convolves an input signal (x) on one channel with the impulse response represented by filter coefficients to provide an estimated echo. The echo cancelling generates an output signal (e) from the signal received on the other channel and the simulated echo. The adaptation circuit adapts the coefficients from the output and input signals. The processing uses a fast Fourier transform (FFT) associated with a first controlled multiplexer (MXT) and two multipliers (MT1,MT2). Associated controlled multipliers (MX1A,MX1B,MX2A,MX2B) are connected to the input of an adder-subtractor (ADS). A number of delay lines (L1-L18) are selectively connected to the multiplexers and receive a number of signals determined by a logic control unit responding to the clock pulses (CLK).

Description

Echo cancellation device between two transmission channels

  coupled, in particular in hands-free telephony.

  The invention relates to the echo processing between two transmission channels having between them a coupling, in particular acoustic. The invention advantageously applies, but is not limited to the suppression of an acoustic echo in a telephone set or other hands-free type telephone terminal. Such an echo is in fact produced by the reflection on the walls of the room in which the hands-free telephone is located, of the acoustic signal emitted by the loudspeaker of this telephone and coming from the speech signal of the distant speaker. This reflected acoustic signal is retransmitted on the telephone line via the microphone of the telephone terminal. The distant speaker therefore hears his own words a second time, which is all the more unpleasant as the

  delay brought by the transmission line is significant.

  Echo processing devices are already known, intended to be inserted into the telephone set between the reception line and the transmission line, for example by French patent application No. 93 02 656. Such devices for processing 'echo use an adaptive identification technique which performs echo cancellation by subtracting an estimated echo from a model of acoustic coupling. In other words, the estimated echo is determined, from the signal received on one of the channels and from the estimated coupling between them, by a self-adaptive digital transversal filtering clocked at a

  predetermined clock frequency.

  This adaptive filtering algorithm is implemented in the time domain. However, although it gives satisfactory results, its speed of convergence in particular can prove to be insufficient in the case where the input signal is strongly correlated, such

than a speech signal.

  Also, it has been envisaged to use adaptive filtering algorithms in the frequency domain with low delay performing data processing in blocks. Among the block filtering algorithms that can be used, we can cite the GMDF algorithm (Generalized

  Multi-Delay Adaptive Filter) well known to those skilled in the art.

  In the GMDF algorithm, the reduction of the computational load is obtained by means of the fast convolution technique in the frequency domain, called Weighted OverLap-Add (WOLA), which is of a higher complexity. However, this WOLA technique allows more frequent updating of the coefficients of the adaptive filter, which results in a significant improvement in performance both from the point of view of convergence speed and from the point of view of tracking capacity. Consequently the adaptation of the coefficients of the adaptive filter is done at a rate higher than the size of the blocks (oversampling). The oversampling factor cx (number of adaptations of the filter coefficients per block) will be attached to the name of the algorithm which will be named GMDFoCL An implementation of this algorithm on a general purpose microprogrammed signal processor has already been made. However, problems with the operation of the algorithm in real time have been encountered since the computing power necessary for the implementation of the algorithm is greater than the power delivered by such a processor. In addition, the very large storage capacity necessary for the implementation of such an algorithm is generally carried out from static random access memories (RAM) and leads to

  very large component surfaces.

  The invention aims to provide a solution to this problem.

  An object of the invention is to provide an echo cancellation device using self-adaptive frequency filtering operating in blocks and in an oversampled manner, which is industrially feasible and usable by minimizing the surface of the

memory components required.

  The subject of the invention is therefore a device for echo cancellation between two coupled transmission channels, using self-adaptive digital frequency transversal filtering carried out at a predetermined clock rate, in blocks and in an oversampled manner, this device comprising: - means of convolution between an input signal received on one of the channels and the impulse response represented by the coefficients of the filter to deliver an estimated echo, - means of echo cancellation delivering a signal of output from the signal received on the other channel and from the estimated echo, - optionally, normalization means for calculating normalization coefficients from the power of the input signal, and, - adaptation means to adapt the filter coefficients from the output signal, normalization coefficients

input signal.

  According to a general characteristic of the invention, the means of convolution, cancellation, normalization and adaptation are produced according to an integrated and dedicated architecture and comprise: - a common processing unit comprising an operator of Fourier transform associated with input to a first controllable multiplexing means, and a single operative part having two multipliers associated as input to a second controllable multiplexing means and connected at output to the two inputs of an adder / subtractor, - a plurality of dynamic delay lines, controllable and loopable on themselves, intended to be selectively connected to the first and second multiplexing means, and, a logic control unit, capable, in response to the pulses of the clock signal, to deliver selectively and sequentially to the different lines delay and the first and second multiplexing means a plurality of control signals so as to cause the device to execute, sequentially and in a predetermined order, the convolution, cancellation calculations

  echo, standardization (possibly) and adaptation.

  The implementation of such self-adaptive digital frequency filtering on a dedicated architecture thus proves to be more efficient from the point of view of calculation speed and circuit area. It thus makes it possible to install filters having long impulse responses which is necessary in an application for suppressing an acoustic echo. Furthermore, in combination with the use of a dedicated architecture and the use of a common processing unit, the use of dynamic delay lines which are dynamic memories with sequential access that do not include address decoding. , very dense since they comprise in the proposed architecture only three transistors per memory point, and very fast, allow on the one hand to obtain a gain in surface area of the order of 30% compared to the use of static random access memories, and on the other hand to perform a read-write cycle in a single clock pulse which is necessary during the adaptation of the filter coefficients, thus making possible the use of multipliers and

  adders at their maximum throughput.

  The delay lines are advantageously controllable on the rising edges of the clock signal while the registers of the

  operative part are active on the falling edge of this clock signal.

  This allows correct synchronization of the operation of the

  different elements of the device.

  According to one embodiment of the invention, the means of convolution, cancellation, adaptation comprise a first group

  common delay lines, addressed sequentially.

  This first group of delay lines thus advantageously comprises: - a first delay line which can be looped back on itself via a first controllable multiplexer and a first auxiliary adder connected furthermore to the output of the adder / subtractor of the operative part, - a second delay line which can be looped back on itself via a second controllable multiplexer and a second auxiliary adder connected in addition to the output of the adder / subtractor of the operative part , one of the inputs of each of the first and second multiplexers being connected to the output of the Fourier transform operator, and the output of each of the first and second delay lines is connected to the first multiplexing means, and - a third delay line, loopable on itself, via a third controllable multiplexer, a second input of which is connected to the output e of the Fourier transform operator, and a third input of which is connected to the output of the adder / subtractor of the operative part, the output of this third delay line being connected to an input of the second

  means for multiplexing the operative part.

  The first and second delay lines can be used to respectively store the real and imaginary parts of vectors, resulting from a direct Fourier transform, or intended to undergo an inverse Fourier transform. In the latter case, the third delay line makes it possible to advantageously store the result

of the inverse transform.

  The means of convolution, adaptation and normalization advantageously comprise a second group of lines with common delay. According to one embodiment of the invention, this second group comprises: - a fifth delay line, which can be looped back on itself via a fifth controllable multiplexer, another input of which is connected to the operator's output Fourier transform, and - a sixth delay line which can be looped back on itself via a sixth controllable multiplexer, including another

  input is connected to the output of the Fourier transform operator.

  Thus, these fifth and sixth delay lines can respectively store the current blocks representing the real and imaginary parts of the Fourier transform of the samples of the

current block of the input signal.

  To this end, to store the 2N samples of the input signal, a fourth delay line is preferably provided, loopable back on itself via a fourth multiplexer, and another input of which is connected to the input of the first input signal. This fourth delay line is connected at output to the first multiplexing means. If ac designates the oversampling factor of the filter, and K the number of blocks, the device comprises, according to one embodiment of the invention, has ordered pairs of delay lines, called backup lines, of length equal to the product (Kl ) by (N + l), intended to store respectively the at (K-1) older time blocks of N + l values each representing the real parts of the corresponding input signals, and the a (K- 1) time blocks oldest of N + 1 values each representing the imaginary parts of these input signals. Furthermore, the control unit delivers at each instant t = s N / a, with s varying cyclically from 0 to (a-1) modulo a, a control signal in response to which convolution means connect the corresponding pair of delay lines at the second multiplexing means. In addition, before the transmission of the next control signal, the current block stored in the fifth and sixth delay lines, is saved in said pair.

  corresponding backup delay lines.

  The normalization means advantageously comprise a seventh delay line which can be looped back on itself via a seventh auxiliary adder, the other input of which is connected to the output of the adder / subtractor of the operative part, the output of this seventh delay line being connected to an eighth delay line intended for storing the inverses of the coefficients

standardization.

  According to one embodiment of the invention, the adaptation means comprise: - a ninth delay line which can be looped back on itself by means of a ninth auxiliary adder; this ninth delay line, the output of which is connected to the second multiplexing means of the operative part, is intended to store the real parts of the coefficient of the filter, a tenth delay line which can be looped back on itself by means of a tenth auxiliary adder; this tenth delay line, the output of which is connected to the second multiplexing means, is intended to store the imaginary parts of the coefficients of the filter, an eleventh delay line, the input of which is connected, by means of a eleventh multiplexer, at the output of the Fourier transform operator and at the output of the adder / subtractor, the output of this eleventh delay line being connected to the input of the first multiplexing means of the transform operator Fourier and to the other input of the ninth auxiliary adder of the ninth delay line, and, - a twelfth delay line, the input of which is connected, via a twelfth multiplexer, to the output of the operator of Fourier transform and at the output of the adder / subtractor of the operative part, the output of this twelfth delay line being connected to the input of the first means of multiplexing of the operator of transformation mée de Fourier and at the other input of the tenth adder

  auxiliary of the tenth delay line.

  The cancellation means advantageously include two auxiliary delay lines, looped back on themselves via two auxiliary multiplexers, the other respective inputs of which are connected to the output of the adder / subtractor of the operative part, the output one of the auxiliary delay lines being connected to one of the multipliers of the operative part and

  the output of the other delay line deliver the time error signal.

  The cancellation means also comprise the third delay line, connected to the second multiplexing means, by a divider by

  a., such as a shift register.

  Other advantages and characteristics of the invention

  will appear on examination of the detailed description of a mode of

  non-limiting embodiment, illustrated in the accompanying drawings in which: - Figure 1 very schematically shows the functional structure of an echo cancellation device according to the invention, Figure 2 schematically illustrates the dedicated architecture of the device of Figure 1, - Figures 3 and 4 illustrate more particularly a dynamic delay line structure of the device of Figure 1, - Figure 5 illustrates the principle of looping a delay line on itself, - Figure 6 illustrates schematically the structure of the operative part of the device, - Figures 7 and 8 diagrammatically store the input signals in the memory elements of the device, - Figures 9 to 11 diagrammatically evaluate the Fourier transform evaluation of the block current input and the storage of the corresponding values, - Figures 12 and 13 schematically illustrate the saving of older time blocks necessary for the s convolution operations, - Figures 14 and 15 schematically illustrate the updating of the normalization coefficients, - Figures 16 to 18 show schematically the convolution operation of the input signal with the impulse response represented by the filter coefficients, - Figures 19 to 23 schematically illustrate the evaluation of the error signal in the time and frequency domains, and - Figures 24 to 26 represent the adaptation of the coefficients

of the filter.

  As illustrated in FIG. 1, the processing device 1 is inserted in the telephone set between the telephone line 2 (comprising a reception 3 and transmission 4 channel), the loudspeaker 5 (disposed at the end of the reception channel 3), and the microphone 6 (disposed at the end of the transmission channel 4). The telephone set being placed in a room 9, the acoustic signal picked up by the microphone is composed of a real acoustic echo signal 7 and / or

  a speech signal 8 emitted by the local speaker.

  The device 1 comprises a processing block 10 receiving as input time samples x of the signal received on channel 3 and delivering as output on channel 4 an error signal e, from an estimated echo and from the signal d received by microphone 6 after passing through an analog / digital converter 13. This output signal, after echo processing, contains only the speech signal emitted by the local speaker freed from the echo resulting from the reflection of the acoustic signal emitted through speaker 5 and coming from the speech signal

spoken by the distant speaker.

  Of course, a digital / analog converter 12 is provided between the output of the processing blocks located on channel 3 and

speaker input 5.

  The determination of the estimated echo y (t) is carried out on the basis of a self-adaptive digital frequency transversal filtering carried out at a predetermined clock rate, by block and in an oversampled manner. The processing block 10 comprises means for convolution between the input signal x and the impulse response H

  represented by the filter coefficients, to deliver the estimated echo.

  Echo cancellation means are also provided which deliver the output signal from the signal d received on the other channel and from the estimated echo, as well as normalization means for calculating normalization coefficients from the strength of the input signal. In fact, although the computation of the normalization coefficients is not essential, their use makes it possible to improve the convergence capacities of the algorithm. Indeed, an adaptation step inversely proportional to the input power at the adaptation frequency of the filter coefficients (as described below in the GMDFax algorithm) makes it possible to compensate for the energy dispersion

of the input signal.

  Finally, adaptation means are provided for adapting coefficients of the filter from the output signal, coefficients of

  possible normalization and of the input signal.

  Of course, all these means are only shown very schematically in this FIG. 1 and their precise structure will be

  more particularly described with reference to FIG. 2.

  In addition, there is provided a logic control unit UCL which, in response to a clock signal CLK will deliver, as will be seen in more detail below, a plurality of control signals

  of the different elements of the device.

  Although the invention is in no way limited thereto, the echo cancellation device which will now be described in detail, implements the filtering algorithm known by a person skilled in the art under the name GMDFCt which belongs to the family of algorithms

adaptive block filtering.

  Generally, in a GMDF type algorithm, the filter coefficients are adapted to each block of N samples. The impulse response represented by the filter coefficients is divided into K segments (or blocks) of N samples, and therefore presents

a length L = K.N.

  The particularity of the algorithm (1) GMDFo comes from the fact that the processing is repeated at times t = sR with R = N / ct., A being the oversampling factor (overlapping factor), which characterizes the overlap on the samples of the input signal between two adjacent blocks. The convolution equation of this algorithm is written: K-1 YsR = F1 DsR-kN.H (k) (2) k = O YsR represents the estimated echo vector, D the Fourier transform of a block of 2N samples of the input signal x, H the impulse response represented by the coefficients of the filter and FP1

  the inverse Fourier transform operator.

  The frequency vector of error EsR is obtained by the formula EsR = F.f. (dsR -YsR) where f is a windowing matrix which consists in isolating the elements of the estimated echo which correspond to a linear convolution. In the case which will (3) be described, f is a rectangular window, that is to say an ill diagonal matrix of dimension 2N whose N first terms are 1, the following N being zeros. The operator F designates the direct Fourier transform operator. (4) To take account of the fact that the power of the input is unknown and varies over time, the adaptation step (5) g is taken such that / 'o T (s) 2N o T (s) is the normalization matrix. It is a square matrix of order 2N. Its elements can be given by the formulas: Tk (s) = '/ Pk (s) (6) Pk (s + 1) = Pk (S) + (1 - y) I DsR - kN2 In equation (5 ) is a factor, called "forgetting factor",

  allowing an exponential smoothing of the energy.

  The filter is adapted using the equations t (k) (s + l)) = / T (s) DHRiEsR 2N A (k) (s + 1) = rk) (S + 1) H (k) (s + 1) = H (k) (s) + A (k) (S + 1) In summary, the GMDFat algorithm is given by the equations: (1), (2), (3), (4), (5) and (6). In the case of the algorithm without

  constraint, r 'is taken equal to the identity matrix.

  In the case where the normalization coefficients are not used, the matrix T (s) is equal to the identity matrix and the equations

(4) and (5) are not applicable.

  The output signal e, or residual echo, is formed from the last ac vectors of time error esr using a synthesis technique known by a person skilled in the art under the term WOLA (Weighted OverLap-Add). More precisely, each value of the residual echo is calculated for ca successive blocks, the specific synthesis technique used here consisting in summing these values for

get the final value.

  FIG. 2 schematically represents the dedicated architecture, and produced in integrated form, of the device according to the invention. In general, this device comprises a common processing unit comprising an operator of Fourier transform FFT associated at input with a first controllable multiplexing means MXT. It also includes a single operative part having two multipliers MT1, MT2 connected at output to the two registers of a

ADS adder / subtractor.

  The multiplier MT1 is associated with two multiplexers MX1A and MX1B respectively connected at output to the two input registers of this multiplier. Similarly, the multiplier MT2 is associated with two multiplexers MX2A and MX2B connected at output to the two registers

input of this multiplier.

  In combination with this common processing unit, there is also provided a plurality of dynamic delay lines, referenced L1-L16 in this figure, controllable, and loopable back on themselves. These delay lines are intended to be selectively connected to the multiplexers MXT, MX1A, MX1B, MX2A and MX2B, via a plurality of control signals delivered by the logic control unit UCL (not shown in

  this figure for simplicity).

  In other words, all of these means form both the means of convolution, echo cancellation, normalization and adaptation, and it is the sequential and selective control of the various multiplexers and lines to delay which will allow the convolution, echo cancellation, normalization and

adaptation.

  For simplification purposes, the detailed architecture of this device will not be described here with reference to FIG. 2 but will be detailed function by function with reference to the following figures. Similarly, the control of the different delay lines by the different signals delivered by the logic control unit, as well as the control of the corresponding multiplexers will be described and illustrated from functional flowcharts relating to the different functions of the filtering algorithm and from specific figures representing for these different functions, the interconnections between the elements of the device concerned by these different functions. A person skilled in the art will thus be able to easily reconstruct the different time diagrams of the entire device and create the logic control unit, for example by

  classical logic synthesis software.

  Before returning in detail to the operation of the device, we will describe, with particular reference to Figures 3 and 4, the general structure of a dynamic delay line

used in the device.

  As illustrated in FIG. 3, the dynamic delay line LAR is intended to sequentially store a set of n data. In fact, FIG. 3 illustrates a memory plan intended to store a bit of each data item. Of course, the dynamic delay line LAR comprises several memory plans arranged in parallel, operating in synchronized fashion, and intended for storing respectively.

  all the bits of each data.

  Each memory plan comprises a matrix of storage cells CLM1-CLM6 (six cells by way of example in FIG. 3) capable of each storing a bit of the data set. Generally, the number of cells depends on the size of the data set to be stored sequentially. In principle, the number of cells in the matrix is greater than the number of data to be stored in order to avoid overwriting some of them. For each row of the cells of the matrix is provided a data writing bus BSE and a data reading bus BSL, to which the elementary data inputs and elementary data outputs are connected respectively.

cells in the row.

  Each cell also includes a write command input BCE and a read command input BCL. All the write control inputs BCE of the cells of the same column are connected by a write control bus BC1 to generation means MG making it possible to control sequentially and

  cyclically writing and reading data in the delay line.

  Likewise, all the BCL read control inputs of the cells of the same column are connected to the generation means by a control bus BC2, BC3, BC4. Furthermore, as can be seen in FIG. 3, the control buses BC2, BC3 are common to two columns of adjacent cells. In other words, the bus BC2 makes it possible to control both the read control inputs BCL of the cells CLM1 and CLM4 of a column and the control inputs

  writing ECB of cells CLM2 and CLM5 of the adjacent column.

  The generation means MG also comprises a plurality of time delays T. Each memory plane from one line to

  delay is clocked by a clock signal of predetermined frequency.

  The generation means are then able to generate, at each clock pulse, the respective write control signals and

  control command on the corresponding command bus.

  Concretely, the different control signals consist of control information, in this case a control bit capable of taking either the value zero or the value 1 and propagating cyclically in the generation means, at the rate of the clock signal and taking into account the time delays T. Thus, if it is assumed that the control signal is located at the level of the buses BC1 and BC4, during the input of a data by the input BE, this is stored in the cell CLM1 while the data present in the cell CLM3 is stored in the cell CLM4 and that the data stored in the cell CLM6 is delivered to the output BS. At the next clock pulse, the data stored in the cell CLM1 is stored in the cell CLM5 and that which was previously stored in the cell CLM4 is output. At the same time, the data present at the BE input is stored in the CLM2 cell. The dynamic delay line therefore behaves like a memory of the first in first out type (FIFO in English) and it allows, during the same clock cycle, simultaneous write and read access. Although other configurations can in principle be used, the memory cells here consist of points

  dynamic memory with three transistors as illustrated in FIG. 4.

  Thus, the drain of the transistor Tl forms the elementary data output of the current cell CLM while the source of the transistor Tl is connected to the drain of the transistor T3, itself connected to the ground via its source. The source of transistor T2 forms the data input of this cell CLM while the drain of this transistor T2 is connected to the gate of transistor T3. Furthermore, the respective gates of transistor T1 and T2 form the read control and write control inputs of the CLM cell. Bit storage

  stored in this cell takes place at the transistor T3.

  Due to the intrinsically inverting structure of the memory cell used, an IV1 (IV2) inverter is provided connecting the

  bus for reading a line to the write bus for the neighboring line.

  A person skilled in the art will therefore have noticed that each memory plane forms a one-bit dynamic delay line with 3 transistors per stored bit, this dynamic delay line having no addressing system. A gain in size is achieved as well since a static random access memory comprises 6 transistors and an addressing system, while a shift register comprises 8 transistors in the case of a dynamic register and 14 in the case of a static register. In FIG. 5, the general structure of a dynamic delay line LAR used in the device according to the invention is shown diagrammatically, and looped back on itself by means of a multiplexer M controlled by the control signal Concretely, the data output DO of the delay line is connected to the zero input of the multiplexer M. The input 1 of this multiplexer M can receive data, and the output of this multiplexer is connected to the input data line of the delay line. For clarity, the different memory cells CLMa-CLMz of this delay line have been shown in this figure stacked on top of each other. The number of memory cells defines the length

of the delay line.

  When the delay line is looped back on itself, i.e.

  say when the signal S is set to zero, and the delay line is activated by the clock signal CLK, the data present in the cell

  CLMz is output and is stored in the CLMa cell.

  At the same time, data is shifted in the different memory cells. Thus, the data which was stored in the cell CLMa is now stored in the cell CLMb. Also, the loopback of a delay line on itself and its activation by the

  clock signal makes it possible to read its content.

  On the other hand, when the control signal S of the multiplexer is set to 1, and the delay line is activated by the clock signal, the new value v present at the input of the multiplexer is stored in the cell CLMa and the value which was stored in the cell

  CLMz is overwritten (in the configuration illustrated in Figure 5).

  In the remainder of the text, the notation Rot (L) means that the delay line L is activated by the clock signal and that the corresponding input multiplexer is controlled by the signal S, so that the contents of this delay line. Similarly, the notation Rot (L, v) means that the delay line L is activated by the clock signal and that the input multiplexer of this delay line is controlled by the control signal S, so as to authorize the writing in this delay line L, of the different values v occurring at the input of the multiplexer M or of the delay line (if the multiplexer is omitted). Finally, the notation DO (L) represents the value of the data at the output of the delay line L. As we have seen previously, the operative part consists of the two multipliers MTI, MT2 and the adder / ADS subtractor (Figure 6). The two multipliers are associated as input to the multiplexers MXlA and MX1B and MX2A and MX2B. The input registers of the multipliers are activated at the falling edge CLK of the clock signal as are the registers of the adder / subtractor. Furthermore, the latter receives a specific control signal enabling it to be configured as an adder or

as a subtractor.

  It should be noted here that the control of the registers of the operative part by the falling edge CLK of the clock signal on the one hand and the activation of the dynamic delay lines by the rising edge CLK of the clock signal on the other hand hand allows synchronization

  correct operation of the device.

  As an example, the multiplication of two complex numbers X = (Xr, Xi) and H = (Hr, Hi) is done as follows (Figure 6):

  Z = X.H = (Xr, Xi) (Hr, Hi) = (XrHr-XiHi, XrHi + XiHr) = (Zr, Zi).

  During the first clock cycle the control signal S of the multiplexers MX1B and MX2B is at 0, the first multiplier performs the product of the real parts Xr.Hr, the second performs the product of the imaginary parts XiHi and the adder / subtractor

  performs the subtraction of the two partial products, thus obtaining Zr.

  The transition from S to 1 in the second clock cycle makes it possible to calculate Zi. Therefore the complex product is calculated in two clock cycles. We will now describe in detail with particular reference to Figures 7 and following, the different

  functionalities of the device according to the invention.

  The first step of the calculation begins after the arrival, at time sR (R = N / a), of R new samples of the input x: (x (sR + R-1) ...., x ( sR + 1), x (sR)). These samples constitute with the 2N-R preceding samples the current vector xsR. This vector is

  saved in a delay line L1 of dimension 2N.

  Likewise, the R new samples of the signal d are

  stored in a delay line L5 of dimension N (FIG. 8).

  This storage in the delay lines Li1 and L5 is carried out according to the flow diagram illustrated in FIG. 7. The control signals of the multiplexers M1 and M5 associated with the delay lines Li and L5 are chosen so as to authorize this storage (Rot (Ll, x),

Rot (L5, d), step 70).

  On this flowchart, CKE designates the sampling clock signal of the input signal, making it possible to activate the delay lines L1 and L5. Typically, the frequency of this signal is of the order of 16 KHz while the clock signal CLK clocking the others

  elements of the device according to the invention is of the order of 50 MHz.

  When the R new samples have been saved in the delay lines L1 and L5, filtering of the signal at the current time t = sR can then begin. We first evaluate the direct Fourier transform of the current input block represented by the 2N samples of the vector

xsR input.

  The direct Fourier transform of the current vector of the input signal xsR at time sR (real signal of dimension 2N) is the complex signal DsR whose N-1 values are symmetrical. By

  Consequently, it suffices to memorize N + l different complex values.

  The delay line L2 is used to save the real values, L3 for the imaginary values. These delay lines L2 and L3 are therefore of length N + 1. This evaluation of the Fourier transform

  direct input is illustrated in Figures 9 to 11.

  The multiplexer M1 of the delay line Li is positioned so as to allow the reading of the content of this delay line L1. Furthermore, the logic control unit connects, via the multiplexer MXT, the output of the delay line L1 to the input of

  the FFT Fourier transform operator.

  In parallel, the two multiplexers M2 and M3 associated with the delay lines L2 and L3 are positioned on their inputs connected to the output of the Fourier transform operator, so as to authorize

  writing in these lines L2 and L3.

  Thus, the delay line Li1 activated by the clock signal CLK delivers the 2N samples of the input signal to the operator FFT (FIG. 9, step 90). The real and imaginary parts of the Fourier transform of these 2N samples are respectively stored in the delay lines L2 and L3 activated by the clock signal CLK (Rot (L2, va), Rot (L3, vb) step 91) . In FIG. 9 va and vb respectively denote the values present at the input of L2 and

  L3 and delivered by the FFT operator.

  To carry out the convolution product of the input signal with the impulse response represented by the filter coefficients, it is advisable to memorize the last [ca (K-1) + l] blocks X (') sR (k = O, l , .., K-1; s - 0 =, l, .. at-l (mod) ax), where the notation (mod) means modulo. To this end, while the delay lines L2 and L3 are used to memorize the Fourier transform of the current input block, provision is made for delay lines L7q, L8q, with q varying from 1 to a, to save the c (K-1) older time blocks. In fact, each delay line L7q, of dimension (K1) (N + 1) is intended to store the real part of the corresponding block while the homologous delay line L8q, of the same dimension, is intended to store the imaginary part of this block. In FIG. 12, for simplification purposes, only one delay line L7q has been shown and

a single delay line L8q.

  Before the arrival of the R new samples of the input signal at time (s + l1) R, it will be necessary to save the values stored in the delay lines L2 and L3, in one of the delay lines L7q and L8q. Although this backup is performed at the end of processing, it will now be described here in order to specify in particular that of the delay lines L7q, L8q which will be used for the

  calculation of the convolution product at the current time t = sR.

  In FIG. 12, this saving is carried out by connecting the output of the delay lines L2 and L3 to the respective inputs of the delay lines L7q and L8q selected, by means of the associated multiplexers M7 and M8, by looping back on themselves the delay lines L2 and L3, and activating these four delay lines by the clock signal CLK. In fact, at each current time t = sR, s varying from 0 to oa-l (modulo a) only the pair of delay lines L7at and L8ac (with a = s + l) is selected. For this purpose, two demultiplexers are provided (not shown here for simplification purposes) arranged between the delay lines L2, L3 and the multiplexers M7 and M8, having one input and one outputs, and controlled by a counter varying cyclically from 0 to ac-1, so as to select according

  of the value of a, the appropriate pair of delay lines L7q and L8q.

  Concretely, in the case for example o N = 2, ac = 2 and K = 3, and assuming that the real parts of the Fourier transforms of the successive input vectors take respectively the values 0,1,2; 3,4,5; 6,7,8; ... the storage of these values in the lines to

  delay L71 and L72 is carried out as illustrated in FIG. 13.

  Thus, for s = 0, the storage takes place in the delay line L71, for if it takes place in the delay line L72 and so on. Of course, as already mentioned above, this backup from the delay lines L2 and L3 to the delay lines L7q and L8q takes place only at the end of processing, before arrival, at time t = (s +1) R, of the following R samples. However, it is from the content of these delay lines L7q and L8q selected that will be performed at time t = sR, the product of convolution between the input signal and the impulse response represented by the coefficients of the filter. For this purpose, there are provided, at the output of the delay lines L7q and L8q also two auxiliary multiplexers (not shown here for simplification purposes) having cc inputs and one output and connecting these delay lines respectively to the multiplexers MX1A and MX2A of the operative part. These auxiliary multiplexers not shown here are also controlled by the cyclically varying counter.

from 0 to "-1.

  We will now describe, with particular reference to FIGS. 14 and 15, the updating of the normalization coefficients which is carried out in accordance with equation (5), although this updating can be carried out after the calculation properly

said of the convolution product.

  Firstly, the logic control unit loops the delay lines L2 and L3 back on themselves and respectively connect their output to the two input registers of the two multipliers MT1 and MT2 of the operative part by the four multiplexers MX1A, MX1B and MX2A, MX2B. The activation of the delay lines L2 and L3 as well as those of the two multipliers and of the adder of the operative part makes it possible to effect the sum of the squares of the respective outputs of the delay lines L2 and L3. Then, the logic control unit connects the output of the adder using the register inputs of a multiplier, for example the multiplier MT1, via the multiplexer MXl while the other multiplexer MX1B allows force the other input register of the multiplier MT1 to the value 1-y. The product (1-y) by the sum of the squares previously calculated is stored in one of the registers of the adder while the other register is forced to zero which allows to obtain as output the product (1-y ) by the sum of the squares of the outputs

  delay lines L2 and L3 respectively ((DO (L2) 2 + DO (L3) 2) (1-y)).

  The values, calculated at the previous instant t = (s-1) R, of the normalization coefficients are stored in a delay line L15

  of dimension N + 1 associated as input to an auxiliary adder A15.

  One of the inputs of this adder is connected to the output of this delay line L15 and the other input of this adder is connected to the output of the ADS adder / subtractor of the operative part. Otherwise,

  the output of this adder is connected to the delay line input L15.

  Another delay line L16 of dimension N + 1 is also provided, intended to store the inverses Tkk of the normalization coefficients Pk. This delay line L16 is therefore associated with a multiplexer M16 one of whose inputs is connected to the output of the delay line L16 and whose other input is connected to the output of the auxiliary adder A15 by l via a DV divider which can either be integrated into the device or be part of equipment

  annex to the device, such as a microprocessor.

  To calculate the normalization coefficients P and save them in the delay line L15 at time t = sR, the unit of

  logic command activates the delay line L15 and loops back on it-

  even through the adder A15 which also receives the output from the ADS adder / subtractor. The new value of P (step 140) is thus firstly saved in the delay line L15 (Rot (L15, P); step 141) and after division (step 142; taking into account the coefficient go), the value of T is stored in the delay line L16 (itself activated by the clock signal CLK), via the multiplexer M16 (Rot (L16, T); step 143). A new reading of L2 and L3 (Rot (L2), Rot (L3); step 144) is then performed to

  the next sample to NWme.

  The calculation of the convolution product in the frequency domain is illustrated by the flowchart of FIG. 16 and the corresponding interconnections of the various elements of the device.

are illustrated in Figure 17.

  In addition to the various delay lines already described, the convolution means of the device comprise two other delay lines L9 and L10, of dimension K (N + I) each intended to memorize respectively the real and imaginary parts of the coefficients of the filter. These delay lines L9 and LO10 are respectively associated with two auxiliary adders A9 and AO10. One of the inputs of each adder is connected to the output of the corresponding delay line and

  the output of the adder is connected to the input of this delay line.

  Furthermore, the other input of each auxiliary adder is connected to the output of a multiplexer M9, (M10) with two inputs. One of the inputs of each multiplexer M9 (M10) can be forced to zero while the other input is connected to the output of the delay line L13 (L14). Finally, the output of the delay line L9 is connected to the multiplexer MX2B associated with one of the registers of the multiplier MT2 of the operative part, as well as to the multiplexer MX1B associated with the homologous register of the other multiplier MT1. Likewise, line out at

  delay L10 is connected to these same multiplexers MX1B and MX2B.

  The complex vector Y resulting from this convolution product in the frequency domain is stored in two delay lines LI11 and L12 of dimension N + 1 each. More precisely, the delay line L 1 is intended to store the vector YR representing the real parts of the complex vector Y and the delay line L12 is intended to store the vector Yi representing the imaginary parts of the complex vector Y. To these two lines with delay Lii and L12 are respectively associated two auxiliary adders All and A12 which will make it possible to carry out the operations of reading, addition and

  writing in one CLK clock cycle.

  More precisely, one of the inputs of each adder All (A12) is connected to the output of the corresponding delay line while the other input of this adder is connected to the output of a two-multiplexer M20 (M21) starters. One of the inputs of the multiplexer M20 (M21) may be forced to zero, and the other input of this multiplexer is connected to the output of the adder /

  ADS subtractor of the operative part.

  Finally, the output of each adder All, (A12) is connected to one of the inputs of a MlI 1 multiplexer (M12), the other input of which is connected to the output of the Fourier transform operator. The output of each multiplexer Mll (M12) is connected to the input of the line at

corresponding delay L 11 (L 12).

  For the calculation of the convolution product, the input of the multiplexers M9 and M10 is forced to zero and the delay lines L9 and L10O successively deliver their values DO (L9) and DO (LlO) to

  multiplexers of the operative part (Rot (L9), Rot (L10) step 161).

  Furthermore, as long as j remains below K-2 (flow diagram in FIG. 16), the pair of delay lines L7q and L8q, corresponding to the value of s in progress, also successively delivers their contents DO (L7q), DO (L8q) to the multiplexers of the operative part which makes it possible to carry out the elementary complex multiplications of the convolution product (step 160). During the last incrementation of the index j, the current block is taken into account to perform the elementary complex multiplication of the convolution product and therefore, this time it is the delay lines L2 and L3 which are

  connected to the multiplexer of the operative part (step 162, 163).

  The looping back on themselves of the delay lines L11 and L12 by means of the adders A11 and A12 and the multiplexers M11 and M12 makes it possible to determine and save the values of the

  vectors YR and YI (Rot (L1 1, YR), Rot (L12, YI), steps 161, 163).

  The computation of the convolution product YsR in the time domain (equation 1), illustrated in FIG. 18, is obtained by forcing the value zero on one of the inputs of the adder Al l and A12 via the multiplexers M20 and M21 and by looping back on themselves the delay lines L11 to L12 so that they deliver, after activation, their content to the Fourier transform operator FFT via the multiplexer MXT. This operator therefore performs an inverse Fourier transform operation and the result is a vector of dimension 2N which is stored in a delay line L4 connected to the output of the operator FFT by

  through an M4 multiplexer.

  The evaluation of the time error signal e and of the complex error signal EsR (equation 2) are illustrated particularly on

Figures 19 to 23.

  The error vector e in the time domain is calculated according to the flowchart of FIG. 19. More precisely, the difference of the output of the delay line L5 and the delay line is first calculated (step 200) L4, which is multiplied by the output of the delay line L6 which stores the coefficients of the window f. In practice, in the present case, the coefficients of the window f are equal to 1. This value y thus calculated, is then stored (step 201) in the line to

  delay L4 via the multiplexer M4 (RotL4, y).

  In order to perform the calculation of the error by the WOLA synthesis, a specific block WL is provided having an input E and two outputs Si and S2 and therefore the structure is more particularly detailed in FIG. 20. This block WL comprises a line delay L17 of dimension NR, the output of which is connected on the one hand to the output S2 of the block WL and on the other hand to the input of the delay line L17 via one of the inputs of a M17 multiplexer. The other input of this multiplexer is connected to input E of the WL block. Another delay line L18, of dimension R, is also associated with a multiplexer M18. The output of the delay line L18 is connected to the output S i of the block WL which delivers the time error signal and, on the other hand, to the input of the delay line L18 via the multiplexer L18 . The other input of the L18 multiplexer is connected to

entry E of block WL.

  The delay line L4 is connected at the output, via a shift register RDL (which makes it possible to carry out a division by a by carrying out Logcx shifts to the right, a being a power of 2), to the one of the registers of the multiplier MT1 of the operative part, while the output S2 of the block WL is connected to the homologous register of the other multiplier MT2. The other two registers of the multipliers are forced to 1 via the multiplexers associated with this operational part. Finally, the output of the ADS adder / subtractor from

  the operative part is connected to input E of the WL block.

  The R error values are synthesized in accordance with

the flowchart in Figure 21.

  After N shifts of the delay line L4 (step 210) a value S is calculated. This value S is equal to the output of the delay line L4 divided by oc (step 210) in the case where ox is equal to 1. It is equal to the output of the delay line L4 divided by this increased by the value of the delay line output L17 in the case oc is

different from 1 (step 212).

  This value S is then stored in the delay line L18 (Rot (L18, S); step 213). It is this delay line L18, dimension R

  which contains the R synthesized values of the error.

  In the case where cx is greater than 2, the delay line L26 is updated, in steps 215 and 217 by the values of S calculated

  in steps 214 and 216 respectively.

  If c is equal to 2, the delay line L17 is updated in

step 217 only.

  If c is equal to 1, all the WOLA technique is not used, because in this case, the R outputs of the error are none other than the R

  last values of the vector e stored in L4.

  The complex vector EsR, of dimension N + 1, is obtained by performing a direct Fourier transform of the time error vector e contained in the delay line L4, in accordance with FIG. 23. For this purpose, we use to save the real parts and

  imaginary of the complex vector Es, the delay lines Ll 1 and L12.

  The adaptation of the filter coefficients is carried out in accordance with the three equations (6) as well as with the flowchart illustrated in FIG. 24. This adaptation is also represented, at the level of the interconnections between the different elements of the

  device, in Figures 25 and 26.

  According to one of the equations (6), it is necessary for the adaptation of the coefficients of the filter, to determine the vector A. This vector A is a complex vector whose real and imaginary parts are respectively stored in delay lines L13 and L14 of dimension N + l each. These two delay lines are associated with two multiplexers M13 and M14 respectively connected at the input, on the one hand at the output of the ADS adder / subtractor from the operative part, and on the other hand, at the output of the operator. FFT Fourier transform. Furthermore, the output of the delay line L13 is connected on the other hand to the Fourier transform operator by means of the multiplexer MXT and on the other hand to the input of the delay line L9 (intended for store the real parts of the filter coefficients), via the other input of the multiplexer M9. Likewise, the output of the delay line L14 is connected on the one hand to the input of the Fourier transform operator FFT via the multiplexer MXT and, on the other hand, to the input of the delay line L10, (intended to store the imaginary parts of the coefficients of the filter),

  via the other input of the M10 multiplexer.

  In the flow diagram of FIG. 24, ZR denotes the vector of the real parts of the complex vector A and ZI the vector of the imaginary parts of the complex vector A. As long as j remains less than K-2, ZR and ZI are calculated according to the equations from step 240. In practice, the coefficients T (DO (L16)) are delivered by the delay line L16. The complex multiplication between the input vector and the complex error vector is obtained from the values delivered by the delay lines L11 and L12 on the one hand, and the pair of delay lines L7q and L8q selected as a function of the value of s (analogously to the convolution product), on the other hand. Of course, all of these multiplications, additions or subtractions are carried out in several clock cycles with possibly loopbacks between the output of the ADS adder / subtractor and the input of the multiplexers in particular to take into account the coefficient pg / 2N which is a constant. The calculated values ZR and ZI are then stored in the

  delay lines L13 and L14 (Rot (L13, ZR), Rot (L14, ZR), step 241).

  When the value of j corresponds to the current input block, it is this time the output of the delay lines L2 and L3 which is taken into account at

  instead of that of the delay lines L7q and L8q (step 242).

  In the case of a constrained algorithm, the updating of the filter coefficient is obtained by performing an inverse Fourier transform of the complex vector ZR, ZI the response being saved in the delay line L4 (steps 243, 244). Then, the last N values of the delay line L4 are set to zero (steps 243, 246) and then a direct Fourier transform is carried out of the content of the delay line L4 (steps 247, 248). The result of this Fourier transform is again stored in the delay lines L13 and L14

(steps 249, 250).

  The update of the filter coefficient is obtained by adding the corresponding value of A (stored in delay lines L13 and L14) to the old value of the filter coefficient. To do this, the outputs of the delay lines L13 and L14 are respectively connected to the input of the delay lines L9 and LO10 via the

* adders A9 and A10 allowing the addition operation to be carried out.

  The adaptation in the constrained case is illustrated more

particularly in Figure 26.

  In the case of an algorithm without constraint, that is to say that when the matrix F is equal to the unit matrix, the adaptation of the coefficients of the filter is done by adding to the old value of the coefficient, the corresponding value of the component of the vector A. However in the unconstrained case the two delay lines L13 and L14 are not used. The adaptation of the filter coefficients is then carried out, after step 240 (242), in accordance with the formulas Rot (L9, ZR + DO (L9)) and Rot (L10, ZI + DO (L10)). In other words, the two delay lines L13 and L14 are eliminated and the second input of the multiplexer M9 (M10) is then directly connected to the output of

the ADS adder.

  The embodiment which has just been described allows the implementation of the GMDFoa algorithm. However, the invention, providing for the use of a single operative part and the use of several dynamic delay lines, can be adapted to other algorithms for block frequency filtering, in particular the UFLMS ("Unconstrained Frequency-") algorithm. Domain LMS "), or the algorithm

  FELMS ("Fast Exact LMS"), known to those skilled in the art.

Claims (12)

  1. An echo cancellation device between two coupled transmission channels, based on a self-adapting digital frequency transversal filtering carried out at a predetermined clock rate, in blocks and in an oversampled manner, comprising means of convolution between a signal d input received (x) on one of the channels and the impulse response (H) represented by the coefficients of the filter to deliver an estimated echo (y), echo cancellation means delivering an output signal (e) from the signal received on the other channel and from the estimated echo, and adaptation means for adapting the coefficients of the filter from the output signal, and the input signal, characterized in that the means of convolution, cancellation, and adaptation are carried out according to an integrated and dedicated architecture and include: -a common processing unit comprising a Fourier transform operator (FFT) associated as input to a p remier controllable multiplexing means (MXT), and a single operative part having two multipliers (MT1, MT2), associated as input to a second controllable multiplexing means (MX1A, MX1B, MX2A, MX2B) and connected as output to the two inputs d '' an adder / subtractor (ADS), - a plurality of dynamic delay lines (L1-L18), controllable and loopable on themselves, intended to be selectively connected to the first and second multiplexing means, and - a control unit logic (UCL), adapted in response to the pulses of the clock signal (CLK), to selectively and sequentially deliver to the different delay lines and to the first and second multiplexing means a plurality of control signals so as to cause the device, and according to a predetermined order, the convolution, echo cancellation and adaptation calculations. 2. Device according to claim 1, characterized in that the delay lines are controllable on the rising edge (CLK) of the clock signal while the registers of the operative part are   active on the falling edge (CLK) of the clock signal.   3. Device according to claim 1 or 2, characterized in that the delay lines comprise three transistors (T1, T2, T3) by memory point.   4. Device according to one of claims 1 to 3, characterized   by the fact that the means of convolution, cancellation, adaptation comprise a first group of common delay lines (L11, L12, L4), addressed sequentially 5. Device according to claim 4, characterized in that the first group of common delay lines comprises:   - a first delay line (LI 1), loopable on it-   even via a first controllable multiplexer (Mll 1) and a first auxiliary adder (A 11) also connected to the output of the adder / subtractor (ADS) from the operative part,   - a second delay line (L12) loopable on it-   even via a second controllable multiplexer (M12) and a second auxiliary adder (A12) also connected to the output of the adder / subtractor (ADS) from the operative part, one of the inputs of each of the first and second multiplexer (Mll, M12) being connected to the output of the Fourier transform operator (FFT), and the output of each of the first (L11) and second (L12) delay lines being connected to the first multiplexing means (MXT), - a third delay line (L4) which can be looped back on itself via a third controllable multiplexer (M4), a second input of which is connected to the output of the transform operator of Fourier (FFT), and a third input of which is connected to the output of the adder / subtractor (ADS) of the operative part, the output of this third delay line (L4) being connected   to an input of the second multiplexing means (MX1B).   6. Device according to one of the preceding claims,   characterized by the fact that it includes normalization means, incorporated in said integrated and dedicated architecture, for calculating normalization coefficients (P. T) from the power of the input signal, the filter coefficients then being adapted also   from the normalization coefficients.   7. Device according to claim 6, characterized in that the means of convolution, adaptation and normalization   have a second group of common delay lines (L2, L3).   8. Device according to claim 7, characterized in that it comprises   - a fourth delay line (L 1) which can be looped over it -   even via a fourth multiplexer (M1), also connected to the input receiving the first input signal (x), to store 2N samples of the input signal, this fourth delay line being connected to the output the first multiplexing means (MXT),   - a fifth delay line (L2), loopable on it-   even via a fifth multiplexer (M2), another input of which is connected to the output of the Fourier transform operator (FFT), - a sixth delay line (L3), loopable back on itself by via a sixth controllable multiplexer (M3), another input of which is connected to the output of the Fourier transform operator (FFT), and by the fact that the fifth and sixth delay lines (L2, L3 ), belonging to the second group of common delay lines, are intended to store respectively two current blocks of N + 1 values representing the real and imaginary parts of the   Fourier transform of the 2N samples of the current input signal.   9. Device according to claim 8, characterized in that, a denoting the oversampling factor of the filter, and K the number of blocks, the device comprises a ordered pairs of lines at   convolution delay (L7q, L8q), of length equal to the product (K-   l). (N + l), intended to store respectively the cc (Kl) temporally older blocks of N + l values each representing the real parts of the corresponding input signals, and o (Kl) temporally older blocks of N +1 values each representing the imaginary parts of these input signals, by the fact that the control unit (UCL) delivers at each instant t = sN / o, with s varying from 0 to cx-1 modulo oc, a control signal in response to which the convolution means connect the corresponding pair of delay lines to the second multiplexing means (MX 1A, MX2A), and by the fact that, before the emission of the next control signal, the current block stored in the fifth and sixth delay lines (L2, L3) is saved in said pair (L7q, L8q)   selected by the control signal.   10. Device according to one of the preceding claims,   characterized by the fact that the normalization means comprise a seventh delay line (L 15) looped back on itself via an adder (A15) whose other input is connected to the output of the adder / subtractor (ADS) of the operative part, and the output of which is connected to an eighth delay line (L16) intended for   store the inverses (T) of the normalization coefficients (P).   11. Device according to one of the preceding claims,   characterized by the fact that the adaptation means comprise: - a ninth delay line (L9) which can be looped back on itself via a ninth adder (A9), and the output of which is connected to the second multiplexing means (MX1B, MX2B), intended to store the real parts of the coefficients of the coefficients of the filter, - a tenth delay line (L10) loopable on itself via a tenth adder (A10), and whose output is connected to the second multiplexing means (MX1B, MX2B), intended to store the imaginary parts of the coefficients of the filter, - an eleventh delay line (L13) whose input is connected, via an eleventh multiplexer ( M13), at the output of the Fourier transform operator (FFT) and at the output of the adder / subtractor (ADS) from the operative part, and the output of this delay line being connected to the input of the first means of multiplexing (MXT) and to the other input of the ninth adder (A9), a twelfth delay line (L14) whose input is connected, via a twelfth multiplexer (M14), to the output of the Fourier transform operator and to the output of the adder / subtractor of the operative part, and the output of this delay line being connected to the input of the first multiplexing means   (MXT), and to the other input of the tenth adder (A10).   12. Device according to one of the preceding claims,   characterized by the fact that the cancellation means comprise two auxiliary delay lines (L17, L18), looped back on themselves via two auxiliary multiplexers (M17, M18), the other respective inputs of which are connected to the output of the adder / subtractor (ADS), the output of one of the auxiliary delay lines (L17) being connected to one of the multipliers (MT2) of the operative part, and the output of the other line to auxiliary delay (L18) delivering the time error signal (e), and, - the third delay line (L4), connected to the second multiplexing means by an ot divider (RDL), such as a shift register .