FR2713797B1 - Access protocol controller by a central unit to peripheral units. - Google Patents

Access protocol controller by a central unit to peripheral units.

Info

Publication number
FR2713797B1
FR2713797B1 FR9314918A FR9314918A FR2713797B1 FR 2713797 B1 FR2713797 B1 FR 2713797B1 FR 9314918 A FR9314918 A FR 9314918A FR 9314918 A FR9314918 A FR 9314918A FR 2713797 B1 FR2713797 B1 FR 2713797B1
Authority
FR
France
Prior art keywords
central unit
access protocol
peripheral units
protocol controller
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9314918A
Other languages
French (fr)
Other versions
FR2713797A1 (en
Inventor
Michel Porcher
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Matra MHS SA
Original Assignee
Matra MHS SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matra MHS SA filed Critical Matra MHS SA
Priority to FR9314918A priority Critical patent/FR2713797B1/en
Publication of FR2713797A1 publication Critical patent/FR2713797A1/en
Application granted granted Critical
Publication of FR2713797B1 publication Critical patent/FR2713797B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
FR9314918A 1993-12-13 1993-12-13 Access protocol controller by a central unit to peripheral units. Expired - Fee Related FR2713797B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9314918A FR2713797B1 (en) 1993-12-13 1993-12-13 Access protocol controller by a central unit to peripheral units.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9314918A FR2713797B1 (en) 1993-12-13 1993-12-13 Access protocol controller by a central unit to peripheral units.

Publications (2)

Publication Number Publication Date
FR2713797A1 FR2713797A1 (en) 1995-06-16
FR2713797B1 true FR2713797B1 (en) 1996-02-09

Family

ID=9453845

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9314918A Expired - Fee Related FR2713797B1 (en) 1993-12-13 1993-12-13 Access protocol controller by a central unit to peripheral units.

Country Status (1)

Country Link
FR (1) FR2713797B1 (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4928260A (en) * 1988-05-11 1990-05-22 Advanced Micro Devices, Inc. Content addressable memory array with priority encoder

Also Published As

Publication number Publication date
FR2713797A1 (en) 1995-06-16

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Legal Events

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TP Transmission of property
ST Notification of lapse

Effective date: 20130830