FR2711861A1 - DC voltage generator with optimal control - Google Patents

Abstract

The invention relates to the DC voltage generators of the resonance converter type operating in continuous or discontinuous mode according to the hyporesonant mode. The invention lies in a digital calculation circuit (42) which makes it possible, in the course of each half-cycle of the converter (41), to calculate the instant of triggering of the semiconductor of the converter (41) for the following half-cycle so as to obtain, on the one hand, as short as possible a time for establishing the high voltage (V) and, on the other hand, to achieve minimum low-frequency residual ripple. The invention applies to voltage generators used to supply X-ray tubes.

Description

CONTINUOUS VOLTAGE GENERATOR
OPTIMALLY CONTROLLED
The invention relates to regulated direct voltage generators of the resonance converter type operating in continuous or discontinuous conduction below the resonance frequency Fr of the oscillating circuit (hyporesonant mode).

Such voltage generators are used in particular to obtain a high direct voltage which is applied between the cathode and the anode of an X-ray tube.

An X-ray tube 10, for medical diagnosis for example, is constituted (FIG. 1) like a diode, that is to say with a cathode 11 and an anode 12 or anticathode, these two electrodes being enclosed in an envelope 13 vacuum tight, which allows for electrical isolation between these two electrodes. The cathode 11 produces an electron beam 8 and the anode 12 receives these electrons over a small surface which constitutes a focal point from which the X-rays are emitted.

When a high supply voltage is applied by a generator 14 at the terminals of the cathode 11 and of the anode 12 so that the cathode is at a negative potential -HT and the anode at a potential + HT positive relative to that of the cathode, a so-called anode current is established in the circuit through the generator 14 producing the high supply voltage; the anode current crosses the space between the cathode and the anode in the form of the electron beam 8 which bombards the hearth.

For better dissipation of energy, the anode 12 has the shape of a flat disc which is carried by a shaft 18 of axis 17 secured to a rotor 16 of an electric motor whose stator 15 is arranged at outside the envelope 13. To cool the tube 10, the latter is placed in an enclosure 19 filled with an insulating and refrigerating fluid 9.

The characteristics of the X-rays which are emitted by the tube, in particular their hardness, depend on many parameters and one of them is the value of the high voltage which is applied to them, this high voltage having to be adjustable to obtain the characteristics required and must remain constant throughout the duration of the radiological exposure so as not to modify the operating characteristics of an X-ray receiver which receives the X-rays having passed through the object under examination.

Furthermore, since such a tube for medical diagnosis operates in pulses, it is important that the time for establishing the high voltage as well as the time for this high voltage to return to zero is as short as possible.

Generators for obtaining an adjustable direct high voltage are known and are based on the rectification and filtering of an alternating voltage, the latter being supplied either by the 50/60 hertz network, or by a converter operating at a frequency generally higher than ten kilohertz.

A high voltage generator of the converter type comprises, as shown in FIG. 2, a supply circuit 20 which supplies a direct voltage E, possibly adjustable, from an alternating voltage "e" supplied by the sector. Voltage E is applied across an inverter circuit 21 which includes a chopper circuit 22, an oscillating circuit 27 and a control circuit 24.

The alternating signal supplied by the inverter circuit 21 is applied to a step-up transformer 25, the secondary winding 25s of which is connected to a rectification and filtering circuit 26. This circuit 26 supplies a direct voltage Vs which is applied between the anode 12 and the cathode 11 of the X-ray tube 10.

Conventionally, the chopper circuit 22 comprises, for example, a first pair of transistors T1l, T12 which are connected in series on the output terminals of the supply circuit 20. Diodes D11, D12
D21 and D22 are respectively connected in parallel between the collector and the emitter of transistors T1l, T12 T21 and T22 so that their anode is connected to the emitter of the corresponding transistor. The bases of the transistors T11, T12 T21 and T22 are connected to the control circuit 24 which supplies switching signals for the transistors. The two output terminals of the chopper circuit 22 are formed, on the one hand, by the common point A of the transistors T11 and T12 and, on the other hand, by the common point B of the transistors
T21 and T22
The oscillating circuit 27 comprises, for example, in series a coil L1, a capacitor C1 and the primary winding 25p of the transformer 25. One of the terminals of the coil L1 is connected to the output terminal A of the chopper circuit 22 and the terminal of the primary winding 25p of the transformer 25, the one which is not connected to the capacitor C1, is connected to the output terminal B of the chopper circuit 22.

The transformer 25, of the voltage booster type, comprises, in addition to the primary winding 25p, the secondary winding 25S whose output terminals are connected to the rectification and filtering circuit 26.

The rectification circuit consists, for example, of a bridge with four diodes D1, D2, D3 and D4 which supplies a full-wave rectified current applied to the filtering circuit constituted by a capacitor Cf.

It is the output voltage Vs at the terminals of this capacitor Cf which is applied between the anode 12 and the cathode 11 of the X-ray tube 10.

The control circuit 24 essentially comprises a comparator 23, a circuit 28 for measuring the current I1 in the oscillating circuit 27 and a circuit 29 for producing the switching signals of the transistors T11, T22, T12 and T21 of the chopping circuit 22.

The two input terminals of the comparator 23 are connected, one, to the common point of the resistors R1 and
R2 of a voltage divider to which the voltage Vs is applied and the other to a reference or reference voltage source of value Vc which is proportional to the value Vs to be obtained. The output terminal of the comparator 23 supplies a signal whose amplitude is proportional to the difference of the signals V's and Vc applied to the input terminals (Ves being proportional to Vs) and is connected to an input terminal of the circuit 29. It is this difference which causes the frequency F of the control signals of the transistors T11, T22, T12 and T21 to change.
The signals which are applied to the input terminals of the comparator 23 are proportional to the voltage V
Vs at the terminals of the tube and the other Vc at the voltage Vs to be obtained but, in the following description, we will assimilate them to Vs and Vc.

Furthermore, the output terminal of the current measurement circuit I1 is connected to another input terminal of the circuit 29 and the corresponding signal is used, in particular, to detect and avoid certain malfunctions of the inverter circuit 22.

The generator of FIG. 2 and, more particularly the inverter 21, can operate in discontinuous or continuous conduction according to the hyporesonant mode.

As indicated above, the invention relates to a generator in which the converter operates in continuous conduction in the hyporesonant mode.

According to a variant, provision is made to operate the hyporesonant converter in discontinuous mode.

The time diagram of FIG. 3e illustrates the operation in continuous conduction according to the hyporesonant mode by indicating, on the one hand, the shape (curve 31) of the current I1 in the primary winding and, on the other hand, the diodes or the transistors which are conductive during each part of the curve 31 of variation of the current I1. The time diagram of FIG. 4e illustrates the operation in discontinuous conduction according to the hyporesonant mode. It indicates, on the one hand, the shape (curve 32) of the current I'1 in the primary winding and, on the other hand, the diodes or the transistors which are conductive during each part of the curve 32 of variation of the current I'1.

The time diagrams of FIGS. 3f and 4f illustrate the current I2 or I'2 which flows in the secondary winding 25s after rectification.

The other time diagrams in FIGS. 3a to 3d and in FIGS. 4a to 4d illustrate the control signals
Cd1l, Cd22 Cd12 and Cd21 which must be applied to transistors T11, T22, T12 and T21 respectively to obtain curves 31 and 32.

FIG. 5 is a diagram showing the variation of the high voltage Vs as a function of time t during a pulse corresponding to an examination time. This diagram shows - that this high voltage does not settle and does not
not disappear instantly because it takes a certain
rise time tone to reach Vc as well as a
certain descent time toff for return to the state
rest; - and that this high voltage is affected by a certain
residual ripple vr which is the result of two
components
i) a high frequency component, which can range
up to 100 KHz or more, which is related to the
operating frequency of the inverter 21,
ii) a low frequency component, which can range
up to 360 HZ, which results from the rectification and
line voltage filtering e.

The known regulating devices, in particular that described in the published French patent application No. 2 684 503, are intended to obtain rise and fall times toff as small as possible and to minimize the low residual ripple frequency vr so that the high voltage Vs remains equal to the setpoint Vc during the texa examination time (FIG. 4).

In the regulation device described in the aforementioned patent application, regulation is said to be of the linear type and is shown diagrammatically in FIG. 6. The set value Vc is compared to the measurement Vs in a circuit 30 to obtain an error E. This error E is amplified and filtered in a regulation circuit 31 which provides a control variable for a power circuit 32 constituted by the inverter 21 (FIG. 2) followed by the transformer 25 and the rectification and filtering circuit 26.

The control variable is the delay Td when the transistors T11, T22, T12 and T21 are started from the instant when the current I1 of the inverter goes to zero.

The regulation circuit 31 is an integral proportional corrector, that is to say that Td is the sum of a part proportional to E and a part proportional to the integral over time of the error E.

The disadvantage of this type of regulation is to introduce error filtering and, consequently, a delay between the observation of the error E and the corrective action on the delay Td and therefore on the power circuit. . This delay limits the speed with which the high voltage Vs is established at the start of the exposure, that is to say that the rise time ton (FIG. 4) is lengthened. It also limits the speed with which the disturbances due to the low frequency residual ripple of the DC supply voltage E of the inverter are rejected.

One of the aims of the invention is therefore to produce a DC voltage generator in which the high voltage is reached in minimal time and without overshoot.

Another object of the invention is to provide a DC voltage generator in which the low frequency residual ripple has a minimum value.

The invention relates to a generator of a high direct voltage of the hyporesonant converter type comprising - a supply circuit for developing a voltage
continuous, - a semiconductor type inverter circuit for
undulate said DC voltage so as to obtain
alternating pulses of frequency lower than
the resonant frequency of the oscillating circuit of the
inverter circuit, - a pulse type isolation transformer
whose primary winding is connected to the output
of said inverter circuit, - a rectification and filtering circuit which is
connected to the secondary winding of the transformer
isolation to rectify and filter pulses
alternatives provided by the inverter circuit by
via said isolation transformer, - a circuit for detecting the passage of current from said
inverter circuit at zero value, - a device for controlling the inverter circuit which
provides high frequency pulses to control
the conduction of the semiconductors of said circuit
inverter, said pulses appearing a certain
delay after switching to zero for each
alternating pulse supplied by said circuit
inverter, characterized in that said control device comprises - measuring circuits for measuring, at each
pulse, certain generator parameters, - digital type means to calculate during the
duration of the alternating pulse during said
inverter circuit the value of the pulse delay
following according to the values of said parameters,
and - a sequential control circuit which supplies the
semiconductor control signals of said circuit
inverter from the calculated delay value.

Other characteristics and advantages of the present invention will appear on reading the following description of a particular embodiment, said description being made in relation to the accompanying drawings in which - Figure 1 is a schematic view of a tube at
X-rays with anode and cathode supplied
by a high voltage generator; - Figure 2 is a block diagram of a generator
high voltage according to the prior art; - Figures 3a to 3g are time diagrams of
signals in the case of a hyporesonant mode in
continuous operation; - Figures 4a to 4f are time diagrams of
signals in the case of a hyporesonant mode in
discontinuous operation; - Figure 5 is a time diagram showing the
variation of the high supply voltage of a tube
x-ray during a radiological examination; - Figure 6 is a block diagram of a generator
DC voltage with a loop of
regulation carried out according to the prior art; - Figure 7 is a block diagram of a generator
optimum control DC voltage according to the invention; - Figure 8 is a simplified theoretical diagram of a
power converter used in generator
DC voltage according to the invention; - Figure 9 is a simplified theoretical diagram of a
analog to digital converter used in
the invention; - Figure 10 is a block diagram of a circuit
sequential control which generates the control signals
transistors of a converter in accordance with the
present invention; - Figure 11 is a block diagram of a circuit
calculation which makes it possible to determine the optimal instant of
switching of transistors; - Figures 12a and 12b are time diagrams
showing the variation of the output voltage V of the
converter (figure 12b) as a function of the pulses
of current supplied by the inverter circuit at the start
of the pose; - Figure 13 shows the variation curves of the
voltage across the circuit capacitor
oscillating of the converter as a function of the current
crossing the oscillating circuit; - Figure 14 shows curves of establishment of the
high voltage according to the prior art and according to the invention.

Figures 1 to 6, which aim to locate the field of the invention and present the prior art, will not be described here again but they are, however, an integral part of the following description of the invention.

An optimally controlled DC generator 40 (FIG. 7) comprises a power circuit 41 and a control device 42. The power circuit 41, also called converter, is analogous to the power circuit 32 of FIG. 6 and comprises in known manner all the elements of the generator of FIG. 2 with the exception of the X-ray tube 10 and the control circuit 24.

The control device 42 comprises - measuring circuits 43 of a certain number of
parameters of converter 41 which will be defined
below, - an analog-digital converter 44 which calculates
a numerical value of each of the measured parameters, - a calculation circuit 45 which, from the values
numerical parameters, calculates a duration Td which
will be defined below, - a state machine 46 or control circuit
sequential which is triggered by a signal
representative of the duration Td, and - an adapter circuit 47 which, from the signals
of the sequential control circuit 46, develops
semiconductor control signals from
the converter inverter 41.

An exemplary embodiment of the converter 41 is given in FIG. 8, the diagram of which corresponds to that of FIG. 2 with the same references for the identical elements of the two figures. Of course, other converter diagrams can be implemented in the context of the invention.

To calculate Td, it is necessary to know the values of the following parameters - the supply voltage E of the converter, that
applied to the input of the inverter, - the output voltage V of the converter, that to
terminals of the capacitor Cf, - the current It in the tube, - the initial voltage Vci at the terminals of the capacitor C1
from the inverter at the start of the alternation on this
capacitor, and - the difference between the output voltage V and the
reference value Vref to be reached, this difference
being noted E.

This is due to the fact that the output voltage V during an alternation depends on the current It of the X-ray tube and on the current I supplied by the inverter. Furthermore, the latter itself depends on the supply voltage E, on the output voltage V, on the delay time at ignition Td and on the initial voltage Vci on the capacitor C1.

Thus, knowledge of the parameters E, V, Td, Vci, and It requires the variation SV of the output voltage during the alternation as well as the final voltage Vcf at the end of the alternation on the capacitor C1. We then deduce that knowledge of the parameters E, V,
It, Vci and 6V are used to determine Td.

The values of the parameters E, V and 6V are measured during operation of the generator while the values of the other parameters It and Vci are calculated.

As regards Vci, an intermediate parameter is used which is the charge Q of the capacitor C1 during an alternation increased by a charge Qd corresponding to the charge during the time Td of conduction of the diode, ie (Q + Qd) which is a monotonic function of Vci.

Furthermore, we also measure the error E that we are looking to cancel and which corresponds to the 6V variation of the output voltage which will cancel the error E.

In the analog-digital converter 44 (FIG. 9), the values are not coded directly but are divided first by E for a "scaling" while the parameter E is put in the form 1 / E. The number 1 associated with V, E, 6V, Q and Qd indicates the rank of the alternation or of the inverter pulse with reference to Figure 12. For the next pulse, these letters will be assigned the number 2 and so immediately for the following pulses.

For the calculation of the delay Td3 corresponding to the third half-wave, calculation which must be carried out during the second half-wave, the measurements of E, V, (Q + Qd) and 6V are used during the first half-wave (El, V1 , (Ql + Qdl) and 6V1) and the measurement of E2 at the start of the second half-cycle because only these measurements are available during this second half-cycle.

For the calculation of the delay Td4 corresponding to the fourth half-wave, the measures E2, V2, (Q2 + Qd2) 6V2 and E3 will be used and so on for the calculation of the following delays.

These codings of the parameters 1 / El, Ql + Qdl, V1, E2 and 6V1 are carried out sequentially, the sequence being symbolized by the switches 50 (FIG. 9) whose closing is controlled by sequential phase signals PO, P1, P2, P3, and P4. The analog-digital converter 49 also receives the voltage El for the division operation by El. For an analog input signal Vin, a digital code corresponding to the value Vin / El is obtained at the output of the converter 49.

During the second half-cycle, it is from the numerical values of El, Ql + Qdl, V, E2 and SVl that the value Td3 of the third half-wave can be calculated, i.e. the duration of conduction of the couples diodes (D11, D22) and (D12, D21), duration at the end of which the conduction of the pairs of transistors (Tl2 T21) and (T11, T22) begins respectively.

This calculation of the duration Td3, or of Td in general, is carried out by means of digital calculation circuit 45 which essentially comprises a memory 51 (FIG. 11) whose addressing is carried out by the digital values of Vin / El different parameters.

The calculations performed by the calculation circuit 45 are carried out according to a certain algorithm which will be described below and lead to a digital value of Td, the countdown of which provides a signal which controls the different states of the sequential circuit 46.

Sequential circuit 46 has seven states referenced
STO to ST6; the state STO is the quiescent state, the states ST1 and ST4 are states of conduction of the diodes (duration Td) and the states ST2, ST3, ST5 and ST6 are states of conduction of the transistors. For example, the state ST1 corresponds to the conduction of the diodes D12 and D21 while the state ST4 corresponds to the conduction of the diodes D11 and D22. State ST3 corresponds to the conduction of transistors T11 and T22 while state ST6 corresponds to the conduction of transistors
T12 and T21 The states ST2 and ST5 are intermediate states which have a duration Ts.

The passage from the state of rest STO to the state ST1 is controlled by a signal for the start of exposure D while the reverse transition is controlled by a signal for the end of exposure F.

The transition from state ST1 to state ST2 is controlled by the end of delay Tdl signal. The transition to the state ST3 takes place for a certain time Ts after the transition to the state
ST2, for example Ts = 1 microsecond, so as not to immediately pass to the state ST4 when the conduction of the transistors has not yet started.

This means that the state ST2 lasts a time Ts.

The transition from state ST3 to state ST4 of conduction of the diodes D11, D22 takes place when the current in the inverter changes polarity, for example becomes negative (signal I-).

The transition from state ST4 to state ST5 of conduction of transistors T12 T21 is effected by the signal for the end of the delay Td2. The transition to the ST6 state takes place for example Ts = 1 microsecond later. The return to the conduction state ST1 of the diodes D12 and D21 takes place when the current in the inverter becomes positive (signal I +).

If there is no signal F of end of exposure, the system goes to state ST2 at the end of the delay Td3 instead of Tdl during the first round. The system continues to run at the rate of the signals marking the end of the delays Td4, Td5 of the polarity inversions (I-, I +) and of the end of delay signal Ts counted down from the end of the delays Td3,
Td4, Td5 etc ...

The calculations to determine the durations Td, with the exception of Tdl and Td2 which are fixed by the maximum value of the current of the inverter, are carried out from measurements of the parameters indicated in FIG. 9, parameters which are used to address a memory 51 (FIG. 11) containing various information. This information is obtained either experimentally or by computer simulation.

In the case of a computer simulation, a program is implemented to determine for E = 400 V the values Vcf, SV, Q, Qd, SV 'and Ism from the values of V, Vci, Td and It, these each taking five different values, for example
V = 0V, 40 kV, 80 kV, 120 kV, 160 kV
Vci = 0V, -400 V, -800 V, -1200 V, -1600 V
Td = 0.8Us, 2.8 ps, 4.8 Us, 6.8 sss, 8.8 sss
It = OmA, 250 mA, 500 mA, 750 mA, 1000 mA
These values will be called "round" or rounded values, or even main parts.

- Vcf is the final value reached by the voltage at
terminals of capacitor C1, - 6V is the difference between the value of the voltage at
the end of the pulse and the voltage value
at the start of the pulse (Figure 12), - Q is the charge of the capacitor Cf during the pulse, - Qd is the charge of the capacitor Cf during the
diode conduction time Td, - 6V 'is the difference between the maximum reached by the
voltage during the pulse and the value of the
voltage at the start of the pulse (Figure 12), and - Ism is the average charge current of the capacitor Cf.

By this simulation, we obtain a "table" of 625 lines, one per group of values different from V,
Vci, Td and It, and 9 columns, one per parameter.

The first twenty-five lines of this "table" are for example in the form of TABLE 1.

TABLE 1
Addressing codes. Values of variables. Simulation values nV. nit. nTd. nVci. V. It. Td. Here. Vcf. NOT . (O + Qd). 8V '. Ism
1 1 1 1 0 0.00 0.8 0
1 1 1 2 0 0.00 0.8 - 400
1 1 1 3 0 0.00 0.8 800 1 1 1 4 0 0.00 0.8 - 1200 1 1 1 5 0 0.00 0.8 - 1600 1 1 2 1 0 0.00 2.8 0 1 1 2 2 0 0.00 2.8 - 400
1 1 2 3 0 0.00 2.8 - 800
1 1 2 4 0 0.00 2.8 - 1200 1 1 2 5 0 0.00 2.8 - 1600 1 1 3 1 0 0.00 4.8 0 1 1 3 2 0 0.00 4.8 - 400
1 1 3 3 0 0.00 4.8 - 800 1 1 3 4 0 0.00 4.8 - 1200 1 1 3 5 0 0.00 4.8 - 1600 1 1 4 1 0 0.00 6.8 0 1 1 4 2 0 0.00 6.8 - 400 1 1 4 3 0 0.00 6.8 - 800 1 1 4 4 0 0.00 6.8 - 1200 1 1 4 5 0 0.00 6, 8 - 1600 1 1 5 1 0 0.00 8.8 0 1 1 5 2 0 0.00 8.8 - 400 1 1 5 3 0 0.00 8.8 - 800 1 1 5 4 0 0.00 8 .8 - 1200 1 1 5 5 0 0.00 8.8 - 1600
TABLE 2
Measurement and conversion of V1, # V1, e2, 1 / El and (Ql + Qdl)
Reading 1: V1, Tdl, (Ql + Qdl) PC1 Vci2
Reading 2: V1, Tdl, (Ql + Qdl), # V1 PG1 Itl
Reading 3: V1, Td2, Vci2, Itl PG2 # V2
Reading 4: V1, Td2, Vci2 PC2 Vci3
Reading 5: V1, 1 / El, Vci3 Td3min
Reading 6: V1, Vci3, Itl, (E2-SV2) PG3 Td3
TABLE 3
Phases Conversion Operation Result
YEAR
PO Q1 + Qdl
P1 # V1 Vl, Tdl, (Ql + Qdl) Vci2
P2 E2 V1, Tdl, (Ql + Qdl), SV1 Itl
P3 1 / El V1, Td2, Vci2, Itl 6V2
P4 V1 V1, Td2, Vci2 Vci3
P5 V1, 1 / El, Vci3 Td3min
P6 V1, Vci3, Itl, (E2-SV2) Td3
P7 Td3
selected
The information contained in TABLE 1 or 625-line memory is used to calculate digital values to be recorded in a memory 51 of the calculation circuit 45 (FIGS. 7 and 11). These digital values which are recorded in the memory 51 make it possible to calculate the value of the delay Td according to a calculation algorithm given by TABLE 2, algorithm which takes place according to phases P0 to P7 (TABLE 3).

The numerical values contained in the memory 51 are the parameters Vci, It, 6V, Vcf, Td and Tdmin.

The addressing of these parameters is carried out by, on the one hand, the measured values E, V, E, 6V and (Q + Qd) and, on the other hand, the values Vci, It, 6V and Vcf read in the memory during previous phases.

The addressing of the memory 51 is carried out by the most significant digits of the coded values, for example 3 or 4 digits, and one therefore obtains in reading only approximate values corresponding to the so-called main part. Also, it is planned to record in this memory 51, the partial derivatives of the values recorded with respect to each of the input variables. The addressing of the memory to read these partial derivatives is obtained using the same codes as for the main part but by adding an additional digit (0 or 1) to indicate that it is

These different operations of the algorithm are carried out in eight phases numbered PO to P7 which take place according to TABLE 3.

These TABLES 2 and 3 correspond to the calculations carried out during the second half-cycle to obtain, at the end of the half-cycle, the values of Td3 and Td3min of the third half-cycle. These values which are used are those of the first alternation for V1, Tdl, Q1,
Qdl, 1 / El and the values E2 and Td2 of the second half-wave which are known at the end of the first half-wave.

During the generator operation, the same calculation algorithm takes place during the next alternation, for example the third alternation, to determine Td4 and Td4min using V2, Td2, (Q2 + Qd2), 1 / E2 and the values E3 and Td3 of the alternation in progress and so on for the determination of Td5, Td6, etc ...

In TABLES 2 and 3 as well as in the description, the values (Ql + Qdl), 6V1, E2 and V1 are so-called scale values, i.e. the values measured and divided by El, as shown in Figure 9.

Before describing the operation of the calculation algorithm, the operations to be performed on the digital values contained in the memory partially represented by TABLE 1 will be described in order to obtain the digital values to be recorded in the memory 51. These operations are in fact carried out using a calculator to which the values contained in the 625 lines of TABLE 1 are supplied.

These operations will be explained with the help of Tables 1, 2 and 3 and Figures 11, 12 and 13. Thus Figure 12a is a diagram showing a curve 58 of variation of the current at the secondary of the transformer 25 before rectification and filtering, in function of time t while FIG. 12b is a diagram showing, in accordance with FIG. 12a, a curve 59 of concomitant variation in the output voltage V of the converter. Curve 59 of FIG. 12b corresponds to three operating modes, a first mode for establishing the high voltage for pulses 1 and 2 and the pulses which precede them, a second mode at steady or steady state for pulses 5 , 6 and following and a third mode for a transient regime between the first and the second.

FIG. 13 is a diagram known as a "phase diagram" or "Lissajous plane" which shows the curve of variation of the voltage Vci on the capacitor C1 as a function of the current I supplied by the converter. At all times,
Vc and I each have a certain value and to this pair of values corresponds a point of the plane. Over time, this point changes in time in the direction of the arrows.

In FIGS. 12 and 13, the points numbered 1, 2, 3, 4, 5 and 6 designate the instants at which the transistors are switched on. The values Vcil to Vci6 are the voltages across the capacitor C1 when the current I is zero. According to the calculation algorithm (TABLE 2), the memory 51 must supply Vci2 during the
Reading 1 from the values of V1, Tdl and (Ql + Qdl), value Vci2 which is not given by TABLE 1 because the latter cannot be addressed by (Ql + Qdl). It is therefore necessary to carry out particular readings of TABLE 1 and to carry out calculations on the values read. To this end, we read TABLE 1 by addressing it with a first pair of values V and Td and we read the five round values of
Vci and the five values of (Q + Qd), which makes it possible to trace the curve (Q + Qd) = f (Vci) for this first couple of V and Td and therefore to match a value of (Q + Qd) to any value of Vci. This curve makes it possible to determine the five round values of (Q + Qd) for the first pair of values V and Td to which correspond five values of Vci not rounded.

This operation is repeated for the other twenty-four pairs of values V and Td, which leads to 125 round values of (Q + Qd) to which 125 values of
Here. Now we are trying to obtain the final values Vcf (or
Vci2) from (V, Td and Q + Qd).

To obtain the value Vcf corresponding to Vci, we read the five values of Vci and Vcf from TABLE 1 corresponding to a couple of V and Td so as to draw the curve Vcf = f (Vci) from which we draw by interpolation the five values of Vcf corresponding to five values of Vci among the 125 obtained at the end of the preceding operation.

This last operation is repeated 25 times to obtain 125 values of Vcf, that is to say that a table has been produced which matches a value of
Vcf, corresponding to Vci2, for a triplet of round values V, Td and (Q + Qd) among 125. These 125 values of Vcf are recorded in memory 51 so as to be read by addressing the latter by the most significant digits of V, Td and (Q + Qd).

As indicated above, the values of V, Td and (Q + Qd) are round values which are not very precise and the same is true of the value Vcf which corresponds to them.

It is therefore planned to perform an interpolation to obtain a more precise value of Vcf (or Vci2). To this end, in addition to the calculation of the 125 values of Vcf, each of the partial derivatives of Vcf with respect to V, Td and (Q + Qd) is calculated, i.e. the slopes of each linear segment of the curve between two consecutive round values, each curve being defined by
Vcf = f (V), Vcf = f (Td) and Vcf = f (Q + Qd).

This interpolation is illustrated by the known mathematical formula
F (xl + dxl, x2 + dx2, .., xn + dxn) = F (x1, x2, .., xn) + dF (1)

According to the calculation algorithm, the memory 51 must supply Itl during Reading 2 from the values of
V1, Tdl, (Ql + Qdl) and EV1, value which is not given by TABLE 1 because it cannot be addressed by (Q + Qd) and 6V1. It is therefore necessary, as previously for Vci2, to carry out particular readings from TABLE 1 and calculations on the values read to determine values of It which will each correspond to an addressing quadruplet (V, Td, Q + Qd, 6V).

For this purpose, the first operation consists in reading a first line of TABLE 1 for a triplet of round values V, Td and It so as to read for the five round values of Vci, the values (Q + Qd) and 6V which do not are not round. This allows to draw a first curve (Q + Qd) = f (Vci) and a second curve 6V = f (Vci). With the first curve, five round values of (Q + Qd) and five corresponding values of Vci are calculated and these last five values are plotted on the second curve to obtain five values of 6V.

This first operation is repeated 125 times, which makes it possible to obtain a table of 625 lines comprising the round values V, Td, (Q + Qd) and It and the corresponding values Vci and 6V.

The second operation consists in reading a first line of this new table for a triplet of round values V, Td and Q + Qd so as to read for the five round values of It, the values 6V which are not round. We can then draw a curve CV = f (It) from which we draw five round values of CV to which correspond five values of It.

This second operation is repeated 125 times, which makes it possible to obtain a table of 625 lines comprising the round values V, Td, (Q + Qd) and CV to which a value It corresponds for each line.

These 625 values of It are recorded in memory 51 so as to be read by addressing the latter with the most significant digits of V, Td, (Q + Qd) and CV.

Each of the 625 values of It is associated with four partial derivatives of It with respect to V, Td, (Q + Qd) and CV which are calculated using the curves It =
It = f (Td), It = f (Q + Qd) and It = f (EV) which are plotted using the table defined in the previous paragraph.

According to the calculation algorithm of TABLE 2, the memory 51 must supply the main part of CV2 during the
Reading 3 from the round values of V1, Td2, Vci2 and Itl. This main part of CV2 is given directly by the most significant figures of CV of TABLE 1 assuming that V1 = V2 and Itl = It2 from one alternation to the next but it must be completed by a characteristic part which is calculated by interpolation using partial derivatives.

These partial derivatives of CV2 for each variable
V, Td, Vci and It are calculated using the curves CV2 = f (V), CV2 = f (Td), CV2 = f (Vci) and CV2 = f (It) which are plotted using the TABLE 1. Each value of CV2 corresponds to four partial derivative values.

The 625 CV2 values as well as the four partial derivatives associated with each CV2 value are recorded in the memory 51 so as to be read by addressing the latter by the most significant digits of V, Td, Vci and It.

According to the calculation algorithm of TABLE 2, the memory 51 must supply the main part of Vci3 during the
Reading 4 from the round values of
V1, Td2 and Vci2. This main part is given directly by the most significant figures of
Vcf of TABLE 1 assuming that V1 = V2 but it must be completed by a characteristic part which is calculated by interpolation using partial derivatives. These partial derivatives of Vcf for each scale value of a variable V, Td and Vci are calculated using the curves Vcf = f (V), Vcf = f (Td) and Vcf = f (Vci) which are plotted using Table 1.

Each value of Vcf corresponds to three partial derivative values.

The 125 values of Vcf (or Vci3) as well as the three partial derivatives associated with each value Vcf are recorded in memory 51 so as to be read by the most significant digits of V, Td and Vci.

According to the calculation algorithm, the memory 51 must provide the main part of Td3min during the
Reading 5 from the round values of V1, 1 / El and
Vci3. This Td3min value not being contained in the
TABLE 1, it must be determined for each of the 125 round values of V1, 1 / El and Vci3 from TABLE 1 knowing that Td3min is defined by the maximum value of the mean current Ism of charge of the capacitor Cf and that the value of Ism is directly proportional to E.

In TABLE 1, for each line defined by a triplet
V, Td and Vci corresponds an Ism value for the value
E = 400 volts which is used by its inverse 1 / E.

From this line, we can create a table with five lines, each line corresponding to a value different from E (or 1 / E) to which a value of Ism corresponds. So if E goes to 800 volts, the value of Ism will be doubled to take the value Isr.

By repeating the above operation for each V triplet,
Td and Vci, we obtain a table of 625 lines from which we draw a first curve Isr = f (Td) while keeping constant the values of V, 1 / E and Vci. This curve makes it possible to determine the value Td3min for the maximum value allowed for Isr, for example 1100 mA. This curve plotting is repeated for each of the 125 lines defined by V, 1 / E and Vci, which determines 125 values of Td3min. We thus created a table which gives a value of Td3min for each triplet of values V, 1 / E,
Here.

This new table is used to calculate the partial derivatives of Td3min with respect to each of the variables V, 1 / E and Vci by plotting the curves
Td3min = f (V), Td3min = f (1 / E) and Td3min = f (Vci).

The 125 values of Td3min and the values of the three partial derivatives are recorded in memory 51 so as to be read by the most significant digits of V, 1 / E and Vci.

In the last phase of the calculation algorithm, the memory 51 must provide the main part of Td3 from the round values of V1, Vci3, Itl and (E2- & V2) in which E2 is measured while 6V2 has been calculated during a previous phase. The measured value (E2-6V2) corresponds to (6V3 + 6V'4), 6V3 being relative to the next pulse (third pulse) for which Td3 is calculated and EV'4 being relative to the fourth pulse at the end of which we must have reached
Vref. In TABLE 1, EV'4 corresponds to the line selected by the quadruplet (V4, It4, Vci4, Td4) which gives the value Vcf corresponding to the initial value
Vci5 of the fifth pulse, the first pulse of the steady state.

However, this steady state is characterized by a value of 6V which is zero and a value of Vci which is the same from one pulse to the next.

The second characteristic (Vci = Vcf) is implemented in TABLE 1 to determine the values of
Td for which this condition is fulfilled by selecting a line from TABLE 1 with a doublet (V, Vci) and plotting the curve Vcf = f (Td) for the five values of Td. This curve makes it possible to determine the value of Td for which Vcf = Vci.

By repeating these operations for the other doublets (V, Vci), we obtain an array of 25 lines which maps a value of Td to a doublet (V, Vci), this value Td corresponding to Vci = Vcf.

The first characteristic (6V = 0) leads to selecting in TABLE 1 a line corresponding to a triplet (V, It and Vci) and to draw for this triplet the curve 6V = f (Td) of the values of 6V for the five values Td rounds. This curve makes it possible to correspond a value of 6V to a value of Td, which was determined above thanks to the condition Vci = Vcf, for the doublet (V, Vci) contained in the triplet (V, It,
Vci). By repeating these operations for each triplet (V, It, Vci), we obtain an array of 125 lines which, for each quadruplet (V, It, Vci, Td), corresponds to a value of 6V. V, It and Vci are then round values and Td corresponds to Vci = Vcf.

This last table makes it possible to plot by triplet (V, Vci,
Td) a curve 6V = f (It) which gives the value of It for 6V = 0. At the end, we obtain a table of 25 lines which gives the values (V, Vci, Td and It) for which 6V = 0 and Vci = Vcf, that is to say for the steady state obtained at the end of the fourth pulse.

These preliminary operations being carried out to take account of the permanent regime which must be achieved, the following operation consists in selecting from the
TABLE 1 the lines corresponding to a triplet of round values (V, It and Vci) and, for each triplet, draw the curve Vcf = f (6V ') for the five scale values of Td corresponding to this triplet. On this curve, the value of 6V 'is determined which corresponds to the value of Vcf of the steady state for the same triplet. By repeating these operations for each of the 125 triplets (V, It and Vci), we create a new table which, for each round value of a triplet (V, It, Vci,), matches a new value of 6V 'different that of TABLE 1 but which corresponds to the steady state.

As Vcf of an alternation corresponds to Vci of the following alternation, each triplet (V, It, Vcf) makes it possible to select in TABLE 1, 125 values of 6V 'each corresponding to a round value of
Vcf (or Vci of the following alternation).

This last table makes it possible to plot, for each doublet (V, It), a curve 6V'4 = f (Vci) from which the value EV'4 is determined for the value Vcf obtained by TABLE 1 by selecting a line by the round values (V, It, Vci, Td). We thus create a first line of a new table with 625 lines which, for each quadruplet (V, It, Vci, Td), matches values 6V'4 and 6V3. The other rows of the table are obtained in a similar manner.

This table of 625 lines makes it possible to plot, for each triplet (V, It, Vci) of round values, a curve (6V + 6V ') = f (Td) from which five round values of (6V + 6V) are determined ') to which correspond five values of Td. A new table is thus created which is saved in memory 51 and which gives the value Td when it is addressed by the quadruplet (V, It, Vci, 6V + 6V ').

For each value of Td3, the partial derivatives of
Td3 with respect to V, It, Vci and (6V + 6V ') which are also recorded in memory 51.

The operations which have just been described in relation to tables 1, 2 and 3 and FIGS. 11, 12 and 13 have made it possible to "create" or "fill" a memory 51 which contains the information necessary for the different phases of the calculation algorithm, this information consisting of - 125 values of Vci (or Vci2) as well as 375 values of
partial derivatives which are addressed by
most significant figures of the triplet
(V1, Tdl, Ql + Qdl), - 625 values of It (or Itl) as well as 2500 values of
partial derivatives which are addressed by
most significant digits of the quadruplet
(V1, Tdl, Ql + Qdl, 6V1), - 625 values of 6V (or 6V2) as well as 2500 values of
partial derivatives which are addressed by
most significant digits of the quadruplet
(V1, Td2, Vci2, Itl), - 125 values of Vci (or Vci3) as well as 375 values of
partial derivatives which are addressed by
most significant figures of the triplet
(V1, Td2, Vci2), - 125 values of Tdmin (Td3min) as well as 375 values of
partial derivatives which are addressed by
most significant figures of the triplet
(V1, 1 / El, Vci3), and - 625 values of Td (or Td3) as well as 2500 values of
partial derivatives which are addressed by
most significant digits of the quadruplet
(V1, Vci3, Itl, E2-6V2).

As an indication, the diagram of the calculation circuit 45 of FIG. 11 shows that the addressing of the memory 51 is obtained by an address code having at most 15 digits plus a digit corresponding to the choice between main part and partial derivatives and plus two digits used to define the reading to be performed. The values read are in the form of eight-digit codes corresponding to the main reading to which are added in an adder circuit 57 the eight digits corresponding to the characteristic part calculated using partial derivatives and the least significant digits of the values. addressed in multiplier circuits 52, 53, 54 and 55 and an adder circuit 56. Circuits 52 to 57 carry out the mathematical operations defined by formulas (1) and (2).

The calculation circuit of FIG. 11 is under the control of the phase signals PO to P7 which are produced by the sequential circuit 50 in accordance with table 3.

The codes which are used to address the memory 51 to obtain the main digital part of the values
Vci2, Itl, SV2, Vci3, Td3min and Td3 and to control the multiplier circuits 52 to 55 to obtain the characteristic part of these same values are supplied, through an addressing circuit 62, by on the one hand, the analog-digital converter 44 (FIG. 7) for the values (V1, El, EV1, E2, Ql + Qdl) and by the adder circuit 57 for the values (Vci2, Itl, 6V2, Vci3).

The generator according to the invention has markedly improved performance compared to the generators of the prior art and in particular compared to that described in the aforementioned French patent application No. 2,684,503 as shown by the two curves in FIG. 14. Curve 60 corresponds to the prior art and shows that the establishment time of the high voltage is at least one millisecond while the establishment time for curve 61 is approximately 300 microseconds, which constitutes a significant improvement.

In addition, if the variations in the high voltage are measured under steady state conditions, the deviations from Vref are less than one per thousand with respect to the low frequency component of the residual ripple vr.

All the description has been made on the basis of the measured values V, E, 6V, E and (Q + Qd) but it is clear that the invention can be implemented by measuring other characteristic values.

Claims (5)

 inverter from the calculated delay value (Td).  semiconductor control signals of said circuit  parameters (V1, El, 6V1, E2 and Ql + Qdl) and - a sequential control circuit (46) providing the  the next pulse depending on the values of said  of said inverter circuit, the delay value (Td) of  for the duration of the current alternating pulse  and Ql + Qdl) of the generator, - means (44) (45) of digital type for calculating  pulse, certain parameters (V1, El, 6V1, E2  inverter, characterized in that said control device (40) comprises - measuring circuits (43) for measuring, at each  alternating pulse supplied by said circuit  delay (Td) after switching to zero for each  inverter, said pulses appearing a certain  the conduction of the semiconductors of said circuit  provides high frequency pulses to control  of said inverter circuit at zero value, - a control device (40) of the inverter circuit which  through said isolation transformer, - a circuit for detecting (28) the flow of current  alternatives provided by the inverter circuit by  isolation to rectify and filter pulses  connected to the secondary winding of the transformer  at the output of said inverter circuit, - a rectification and filtering circuit (26) which is  pulse whose primary winding is connected  oscillating of the inverter circuit, - an isolation transformer (25) of the type  lower than the resonance frequency (Fr) of the circuit  obtain alternating frequency pulses (F)  to undulate said direct voltage (E) so as to  continuous (E), - an inverter circuit (21) of the semiconductor type  CLAIMS 1. Continuous high voltage generator (V) of the hyporesonant converter type comprising - a supply circuit for developing a voltage 2. Generator according to claim 1, characterized in that the means (44) (45) of digital type for calculating during a pulse the value of the delay (Td) comprise (a) an analog-digital converter for coding  the values that have been measured  (V, E, SV, e, Q + Qd) during the previous  impulse, (b) a delay calculation circuit (Td) of  the next impulse which includes  - a digital memory (51) which contains, at least  the following values  - Vci2 for each triplet of values  (V1, Tdl, Ql + Qdl),  - Itl for each quadruplet of values  (V1, Tdl, Ql + Qdl, EV1),  - EV2 for each quadruplet of values  (V1, Td2, Vci2, Itl),  - Vci3 for each triplet of values  (V1, Td2, Vci2),  - Td3min for each triplet of values  (V1, 1 / El, Vci3),  - Td3 for each quadruplet of values  (V1, Vci3, Itl, E2-SV2), the numbers 1, 2, 3 indicating the rank of the pulse, 2 for the current alternation, 1 for the previous alternation and 3 for the next alternation,  - Vci being the initial voltage across the  oscillator circuit capacitor (C1)  inverter circuit (21) at the start of  the pulse of rank i,  - It being the current in the load, such as a  x-ray tube,  - SV the variation of the output voltage (V) at  during a pulse,  - Td being the start-up time of the semi  conductors after the start of the pulse,  and  - Tdmin being the minimum value of this delay  which corresponds to a current  maximum admissible by the converter, (c) an addressing circuit (62) of the memory (51) to  using combination of the numerical values of  measurements and numerical values read in said  memory (51), and (d) a circuit (50) for controlling the calculation phases. 3. Generator according to claim 2, characterized - in that the memory (51) also contains, for  each addressing triplet or quadruplet, the values  numerical partial derivatives of values  (Vci2, Itl, SV2, Vci3, Td3min, Td3) compared to  different variables of said triplet or quadruplet  addressing, - in that the means for calculating the boot time  (Td) include multiplier circuits (52 to  55) and adder circuits (56, 57) for  add to the numeric value read from memory 51  corresponding to the main part, part  characteristic given by the partial derivatives, and - in that the addressing circuit (62) is provided for  address the memory (51) using the digits  most significant addressing codes and to  apply the least significant figures to  multiplier circuits to constitute the  multipliers of partial derivatives. 4. Generator according to any one of the preceding claims, characterized in that the sequential control circuit (46) comprises at least five stable states (ST0, ST1, ST3, ST4 and ST6), one of which (STO) corresponds to stopping while the other four correspond to states whose passage from one to the other is controlled by the delay signal (Td) or by the detection signal (I +, I-) of the zero value of the current in the inverter circuit. 5. Generator according to claim 4, characterized in that the sequential control circuit (46) further comprises two other states (ST2, ST5) which are intermediate states of constant duration (Ts).