FR2711817B1 - Interface de connexion entre un microprocesseur et un bus. - Google Patents

Interface de connexion entre un microprocesseur et un bus.

Info

Publication number
FR2711817B1
FR2711817B1 FR9312966A FR9312966A FR2711817B1 FR 2711817 B1 FR2711817 B1 FR 2711817B1 FR 9312966 A FR9312966 A FR 9312966A FR 9312966 A FR9312966 A FR 9312966A FR 2711817 B1 FR2711817 B1 FR 2711817B1
Authority
FR
France
Prior art keywords
microprocessor
bus
connection interface
interface
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9312966A
Other languages
English (en)
Other versions
FR2711817A1 (fr
Inventor
Guillemin Pierre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Priority to FR9312966A priority Critical patent/FR2711817B1/fr
Publication of FR2711817A1 publication Critical patent/FR2711817A1/fr
Application granted granted Critical
Publication of FR2711817B1 publication Critical patent/FR2711817B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
FR9312966A 1993-10-29 1993-10-29 Interface de connexion entre un microprocesseur et un bus. Expired - Fee Related FR2711817B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9312966A FR2711817B1 (fr) 1993-10-29 1993-10-29 Interface de connexion entre un microprocesseur et un bus.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9312966A FR2711817B1 (fr) 1993-10-29 1993-10-29 Interface de connexion entre un microprocesseur et un bus.

Publications (2)

Publication Number Publication Date
FR2711817A1 FR2711817A1 (fr) 1995-05-05
FR2711817B1 true FR2711817B1 (fr) 1996-01-12

Family

ID=9452381

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9312966A Expired - Fee Related FR2711817B1 (fr) 1993-10-29 1993-10-29 Interface de connexion entre un microprocesseur et un bus.

Country Status (1)

Country Link
FR (1) FR2711817B1 (fr)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5123107A (en) * 1989-06-20 1992-06-16 Mensch Jr William D Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto

Also Published As

Publication number Publication date
FR2711817A1 (fr) 1995-05-05

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20060630