FR2710766B1 - System for transmitting instructions from intranodal commands or internodal communications in a processor node. - Google Patents

System for transmitting instructions from intranodal commands or internodal communications in a processor node.

Info

Publication number
FR2710766B1
FR2710766B1 FR9311586A FR9311586A FR2710766B1 FR 2710766 B1 FR2710766 B1 FR 2710766B1 FR 9311586 A FR9311586 A FR 9311586A FR 9311586 A FR9311586 A FR 9311586A FR 2710766 B1 FR2710766 B1 FR 2710766B1
Authority
FR
France
Prior art keywords
intranodal
commands
processor node
transmitting instructions
internodal communications
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9311586A
Other languages
French (fr)
Other versions
FR2710766A1 (en
Inventor
Georges Quenot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HYPERPARALLEL TECHNOLOGIES
Original Assignee
HYPERPARALLEL TECHNOLOGIES
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HYPERPARALLEL TECHNOLOGIES filed Critical HYPERPARALLEL TECHNOLOGIES
Priority to FR9311586A priority Critical patent/FR2710766B1/en
Priority to PCT/FR1994/001055 priority patent/WO1995009398A1/en
Priority to AU76593/94A priority patent/AU7659394A/en
Publication of FR2710766A1 publication Critical patent/FR2710766A1/en
Application granted granted Critical
Publication of FR2710766B1 publication Critical patent/FR2710766B1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/126Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multi Processors (AREA)
FR9311586A 1993-09-29 1993-09-29 System for transmitting instructions from intranodal commands or internodal communications in a processor node. Expired - Fee Related FR2710766B1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR9311586A FR2710766B1 (en) 1993-09-29 1993-09-29 System for transmitting instructions from intranodal commands or internodal communications in a processor node.
PCT/FR1994/001055 WO1995009398A1 (en) 1993-09-29 1994-09-07 System for transmitting intranodal command instructions or internodal communications in a processor node
AU76593/94A AU7659394A (en) 1993-09-29 1994-09-07 System for transmitting intranodal command instructions or internodal communications in a processor node

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9311586A FR2710766B1 (en) 1993-09-29 1993-09-29 System for transmitting instructions from intranodal commands or internodal communications in a processor node.

Publications (2)

Publication Number Publication Date
FR2710766A1 FR2710766A1 (en) 1995-04-07
FR2710766B1 true FR2710766B1 (en) 1995-12-01

Family

ID=9451360

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9311586A Expired - Fee Related FR2710766B1 (en) 1993-09-29 1993-09-29 System for transmitting instructions from intranodal commands or internodal communications in a processor node.

Country Status (3)

Country Link
AU (1) AU7659394A (en)
FR (1) FR2710766B1 (en)
WO (1) WO1995009398A1 (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4449182A (en) * 1981-10-05 1984-05-15 Digital Equipment Corporation Interface between a pair of processors, such as host and peripheral-controlling processors in data processing systems
JPS5995660A (en) * 1982-11-22 1984-06-01 Nec Corp Data processor
JPH04242852A (en) * 1990-02-13 1992-08-31 Internatl Business Mach Corp <Ibm> Control mechanism and method of first-in first-out buffer queue for multiprocessing

Also Published As

Publication number Publication date
AU7659394A (en) 1995-04-18
WO1995009398A1 (en) 1995-04-06
FR2710766A1 (en) 1995-04-07

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Legal Events

Date Code Title Description
ST Notification of lapse