FR2710475B1 - Current controlled TTL output stage. - Google Patents
Current controlled TTL output stage.Info
- Publication number
- FR2710475B1 FR2710475B1 FR9311167A FR9311167A FR2710475B1 FR 2710475 B1 FR2710475 B1 FR 2710475B1 FR 9311167 A FR9311167 A FR 9311167A FR 9311167 A FR9311167 A FR 9311167A FR 2710475 B1 FR2710475 B1 FR 2710475B1
- Authority
- FR
- France
- Prior art keywords
- output stage
- current controlled
- ttl output
- controlled ttl
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09425—Multistate logic
- H03K19/09429—Multistate logic one of the states being the high impedance or floating state
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9311167A FR2710475B1 (en) | 1993-09-20 | 1993-09-20 | Current controlled TTL output stage. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9311167A FR2710475B1 (en) | 1993-09-20 | 1993-09-20 | Current controlled TTL output stage. |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2710475A1 FR2710475A1 (en) | 1995-03-31 |
FR2710475B1 true FR2710475B1 (en) | 1995-11-24 |
Family
ID=9451026
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9311167A Expired - Fee Related FR2710475B1 (en) | 1993-09-20 | 1993-09-20 | Current controlled TTL output stage. |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2710475B1 (en) |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4959561A (en) * | 1989-01-04 | 1990-09-25 | Motorola, Inc. | MOS output buffer with reduced supply line disturbance |
JP3014164B2 (en) * | 1991-05-15 | 2000-02-28 | 沖電気工業株式会社 | Output buffer circuit |
-
1993
- 1993-09-20 FR FR9311167A patent/FR2710475B1/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2710475A1 (en) | 1995-03-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20130531 |