FR2706065A1 - Address generator with zig zag scan - Google Patents

Abstract

The address generator with zig zag scan according to the invention comprises a line address generator (100) intended for generating a line address signal which stops, increases or decreases a state present in response to an enable signal (EN), and a column address generator (200) intended for generating a column address signal which stops, increases or decreases a state present with the enable signal (EN). Thus, the address generator with zig zag scan can generate addresses with zig zag scan according to a zig zig scan process and simplify the circuit layout thereof.

Description

ZIGZAG SCANNING ADDRESS GENERATOR

  BACKGROUND OF THE INVENTION The present invention relates to an address generator, and more particularly, to a zigzag scan address generator intended to scan according to a

zigzag pattern.

  A zigzag address scanning method can be adapted to video coders for use on a videophone or videoconference device or on any ordinary video equipment intended to produce a high quality image. In particular, the method can be adapted to a video compression method intended for high-definition television systems (HDTV) using the techniques of

  next generation digital compression.

  For example, during data transmission, video data compression is performed by a discrete cosine transform (TCD) operation, using variable length quantization or coding. With these latter methods, the TCD coefficients are generally concentrated in a low-frequency area after execution of the TCD operation and of the quantization. Consequently, when the coefficients are arranged sequentially from a low frequency zone to a high frequency zone, an irregular arrangement results, that is to say the coefficients with larger values are found in the low zone frequency and the coefficients with lower values (close to zero), in the zone to

high frequency.

  The method mentioned above intended to sequentially arrange the quantization coefficients can also be classified according to a method of

  orthogonal scanning or a zigzag scanning method.

  Although the DCT coefficients are concentrated in the low frequency area, as described above, the orthogonal scanning method by which the sequential scanning is performed from the low frequency area to the high frequency area, performs compression in a manner ineffective. In contrast, the zigzag scanning method by which the scanning is performed in a zigzag pattern starting with the low frequency area in which the coefficients with larger values are concentrated, fully transmits the coefficients with larger values but omits the zeros from the high frequency zone (in which zeros are frequently generated) and transmits only the number of successive zeros, thus performing a

  more efficient data compression.

  It is for this reason that the zigzag scanning process has been recognized as an internationally standardized technique for digital video compression (e.g., JPEG or H.261 processes). However, despite its advantages, the zigzag scanning method is not yet widely used due to the associated drawbacks.

to its establishment.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a zigzag scanning address generator for zigzag scanning by which signal compression and restoration are performed in response to a quantized digital video signal and a signal. video

decoded with variable length.

  Another object of the present invention is to provide a zigzag scan address generator which

  simplifies circuit configuration.

  To accomplish the above object of the present invention, the zigzag scanning address generator includes a line address generator for generating a line address signal which stops, increases or decreases a state present in response to a validation signal, and a column address generator for generating a column address signal which stops, increases or decreases a present state

  in response to the validation signal.

Brief description of the drawings

  The above objects and advantages of the present invention will appear more clearly thanks to the

  detailed description of a preferred embodiment of the

  present invention and with reference to the accompanying drawings, in which: Figure 1 shows a conventional method for generating zigzag scanning addresses; FIG. 2A is a state diagram showing the state conversion of the row addresses of table 1; FIG. 2B is a state diagram showing the state conversion of the addresses of columns of table 1; Figure 3 is a block diagram of the zigzag scan address generator according to the present invention; and FIG. 4 is a circuit diagram of a preferred embodiment of the address generator to

  zigzag scanning according to the present invention.

  Detailed description of the invention

  In Figure 1, the 2nx2n screen video data is scanned in numerical order, i.e. in

  the order following the arrow marked in dotted line.

  In other words, when the data is saved to, or read from, the memory in which the 2nx2n video data on the screen is stored, the data is scanned in a zigzag order. When data is saved to, or read from, memory, the sequential increment address counter used in conventional memory does not

  cannot perform a zigzag scan.

  Table 1 illustrates the generation of addresses

  zigzag scanning according to the present invention.

TABLE 1

  order address column row address

1 0 0

2 O 1

3 1 0

4 2 0

1 1

  2nx2n-1 2n-1 2n-2 2nx2n 2n-1 2n-l In Table 1, the 1st address in Figure 1 corresponds to the row address O and to the column address O. In addition, the 2nd address corresponds to row address O and to address of column 1, then continues in this way, so that, finally, the 2nx2n th address corresponds to line address 2n-1 and to address of column 2n-1. Here, the line address of an address is the upper binary and the address of

column, the lower binary.

  Figure 2A is a state diagram of addresses

rows of table 1.

  In the state diagram of FIG. 2A, a non-change of address to the next state is represented by a stop state 41, an increase in address to the next state is represented by a state of increase 42, and a decrease in address to the next state is represented by a decrease state 43. In other words, referring to Table 1, since there is no change of address when passing from the 1st address to the 2nd address relative to the line (upper binary), this condition is called a stop state. However, the address increasing by one unit from the 2nd address to the 3rd address, there is an increase, and the address decreasing by one unit from the 4th address to the 5th

  address, there is a decrease.

  This amounts to saying that, when the RSO condition is satisfied, that is to say that the row address is O or the column address is 2n-2, the address undergoes a state increase, which is represented by the RSO transition from the stop state 41 to the increase state 42. When the RSO condition is not satisfied, the address undergoes a state decrease, which is represented by the RSO transition from the stop state 41 to the decrease state 43. When the condition RS1, that is to say that the line address is 2n-2 or 2n-l, is not satisfied, l address stops increasing, which is represented by the transition

  RS1 from the state of increase 42 to the state of stop 41.

  When the RS2 condition is satisfied, i.e. the column address is 0, the address becomes a decrease state 43 from an increase state 42, which is represented by a transition RS2. When neither the RS1 condition nor the RS2 condition are satisfied (RS1.RS2), the address is maintained at an increase state 42, as indicated by the curved arrow. When the condition RS3 is satisfied, that is to say that the line address is 1 1, the address stops decreasing, which is represented by the transition RS3 from the state of decrease 43 to 1 'stop state 41. When the RS4 condition is satisfied, that is to say that the column address is 2n-2 or 2n-1, the address becomes an increase state 42 from a state of decrease 43, which is represented by a transition RS4 from the state of decrease to the state of increase. When neither the RS3 condition nor the RS4 condition are satisfied (RS3, RS4), the address is maintained in a state of decrease

  43, as indicated by the curved arrow.

  FIG. 2B is a state diagram illustrating the state conversion of the addresses of columns of table 1. In the state diagram of FIG. 2B, a non change of address to the following state is represented by a state stopped 51, an increase in address in the next state is represented by a state of increase 52, and a decrease in address in the next state is represented by a state in decrease 53. In other words , referring to Table 1, since the address increases by one unit from the 1st address to the 2nd address, there is a state of increase, and the address decreases by one unit from the 2nd address at the 3rd address, there is a decrease. However, since there is no change of address when going from the 3rd address to the 4th address relative to the column (lower binary),

  this condition is called a stop state.

  This amounts to saying that, when the condition CSO is satisfied, that is to say that the column address is O, the address undergoes a state increase, which is represented by the transition CSO from the state d 'stop 51 in the state of increase 52. When the CSO condition is not satisfied, the address undergoes a state decrease, which is represented by the transition CSO from the state of stop 51 to l decrease state 53. When the condition CS1 is satisfied, that is to say that the column address is 2n-2 and the row address is neither O nor 2n-1, the address stops increasing, which is represented by the transition CS1 from the increase state 52 to the stop state 51. When the condition CS2 is satisfied, that is to say that the column address is O, the address becomes a decrease state 53 from an increase state 52, which is represented by a transition CS2 from the increase state to the decrease state. When neither the condition CS1 nor the condition CS2 are satisfied (CSl.CS2), the address is maintained at an increase state 52, as indicated by the curved arrow. When condition CS3 is satisfied, i.e. the column address is 1 and the row address is not 2n-2, the address stops decreasing, which is shown by the transition

  CS3 from the decrease state 53 to the stop state 51.

  When condition CS4 is satisfied, that is to say that the line address is 2n-2, the address becomes an increase state 52 from a decrease state 53, which is represented by a transition

  CS4 from the state of decrease to the state of increase.

  When neither the condition CS3 nor the condition CS4 are satisfied (CS3. CS4), the address is maintained at a state of decrease 53, as indicated by the curved arrow. Table 2A is a state transition table of line addresses according to the state diagram of the

Figure 2A.

TABLE 2A

  Present state RS0 RS1 RS2 RS3 RS4 Next state

0 0 1 X X X X 1 0

00 0 X X X X 1o

X 0 0 X X 10

X 1 O X X 0 0

1 0 X O 1 X X Ol1

01 X X X 1 0 0 0

01 X X X 0 1 10

  Note: X is the condition * unimportant * In table 2A, for a present state "0 0" and given that RSO is 1 and that RS1, RS2, RS3 and RS4 are all X, the line address s increase of a unit to become "1 O" since the address transitions from a stop state 41 to an increase state 42, as can be seen in the state diagram of FIG. 2A . Referring further to Table 2A, for a present state "1 0" and since RS1 and RS2 are both 0 and RS3, RS4 and RS5 are all X, the original state is maintained, c that is, it remains at "1 0" since the address state is maintained at an increase state 42. Likewise, for a present state "O 1" and given that RSO, RS1 and RS2 are all X and RS3 and RS4 are both 0, the original state is maintained since the address state is maintained at a decrease state 43. This

  is to say that the next state is still 0 1 ".

  Table 2B is a state transition table of column addresses according to the state diagram of

Figure 2B.

TABLE 2R

  Present state CSO CS1 CS2 CS3 CS4 Next state

0 0 1 X X X X 1 0

00 0 X X X X 0 1

X 0 O X X 10

X 1 O X X 0 0O

X O 1 X X 0 1

0 1 X X X O O 0 1

I ol I xlxlxlo o oo

0 1 X X X 1 X O 0

Gil x lx lx i o o

01 X X X O 1 10

  Note: X is the% unimportant condition In table 2B, for a present state "O 0O and given that CSO is 1 and that CS1, CS2, CS3 and CS4 are all X, the column address increases of a unit since the address transitions from a stop state 51 to an increase state 52, as can be seen in the state diagram of FIG. 2B, and the following state becomes " 1 O ". Referring further to Table 2B, for a present state" 1 0O and since CS1 and CS2 are both 0 and CS3, CS4 and CS5 are all X, the original state is maintained, that is, it remains at "1 Or since the address state is maintained at an increase state 52. Similarly, for a present state" O 1 "and given that CS0, CS1 and CS2 are all X and that CS3 and CS4 are both 0, the original state is maintained since the address state is maintained at a decrease state 53. This amounts to saying that l next state ant is also "0 1" Figure 3 is a block diagram of the zigzag scan address generator according to the present invention. In FIG. 3, the zigzag scanning address generator is composed of a row address generator 100 validated by a validation signal EN, intended to generate row addresses, and a column address generator 200 , also validated by an EN validation signal, intended to validate column addresses. Here, the line address generator 100 consists of a line state register decoder 110, a following line state generator 130 and a first up / down counter 120, and the line generator column addresses 200 consists of a column state register decoder 210, a generator of next column states 230

  and a second up / down counter 220.

  The line state register decoder 110 receives the predetermined validation signal as its input, so as to start the compression or the restoration of the data, and delivers the control signals of the stop, increase and decrease states. intended for the generator of following line states 130 and for the first up / down counter 120 using an internal register with two binaries. The first up / down counter 120 maintains its counted value when the present line status signal indicates a stop state, increases its counted value by one when a valid increase status signal is received and decreases the counted value of one when a valid decrease status signal is received. Also, the three-bit data generated in the first up / down counter 120 is used by the memory address and is transmitted to the next line state generator 130 to generate the next line state. The next line state generator 130 receives a line state signal present and the output signals of the first and second up / down counters 120 and 220 as inputs, so as to thus generate the next line state according to the

  transition condition as described above.

  The operation of the column address generator 200 is the same as that of the generator

of line addresses 100.

  As described above, ADDR 2n binary addresses {R [n], C [n]} can be generated by setting the line address R [n] with n binary as upper binary and the address C [, respectively] n] of column

  with n binaries as lower binaries.

  Figure 4 is a detailed circuit diagram of a preferred embodiment of the address generator to

  zigzag scanning according to the present invention.

  In FIG. 4, the line state register decoder 110 comprises flip-flops RS 110d and 110e, each having a reset terminal R to which an enable signal EN is applied and an initialization terminal S connected to ground, an AND gate 110a intended to perform an AND operation as a function of the inverted outputs (Q) of the flip-flops RS 110d and 110e, an AND gate 11Ob intended to carry out an AND operation as a function of the output Q of the flip-flop RS 11Od and of the output inverted (Q) of the flip-flop RS e, and an AND gate 11Oc intended to perform an AND operation as a function of the inverted output (Q) of the flip-flop RS 110d and of the output (Q) of the flip-flop RS e. The column state register decoder 210 comprises an RS flip-flop 210d whose initialization terminal S receives a validation signal EN and whose reset terminal R is connected to ground, an RS flip-flop 210e whose reset terminal R receives an validation signal EN and whose initialization terminal S is connected to ground, an AND gate 210a intended to perform an AND operation as a function of the inverted outputs (Q) of the flip-flops RS 210d and 210e, an AND gate 210b intended to perform an AND operation as a function of the output (Q) of the flip-flop RS 210d and of the inverted output (Q) of the flip-flop RS 210e, and an AND gate 210c intended to perform an AND operation as a function of the reverse output (Q) of the RS 210d flip-flop and of the output (Q)

of the RS 210e scale.

  The first up / down counter 120 comprises a down / down counter 120a intended to generate addresses of lines with three binary numbers using a HOLD access port to which the output of the AND gate 110a is applied and a COUNTING / DECOUNTING access of coefficient coefficient control up / down counting to which the output of the AND gate 11Ob is applied, and a decoder 120b intended to decode the output signal of the

up / down counter 120a.

  The second up / down counter 220 comprises a down / down counter 220a intended to generate column addresses with three binary numbers using a HOLD access port to which the output of the AND gate 210a is applied and a COUNT / DOWN COUNT access for controlling the coefficient of coefficient up / down counting to which the output of AND gate 210b is applied, and a decoder 220b intended to decode the output signal of the

up / down counter 220a.

  The following line state generator 130 comprises inverters 130a, 130b, 130c and 130d intended to respectively invert the eighth, seventh, second and first output signals of the decoder 120B, an OR gate 130e intended to perform an OR operation in function the first output signal from the decoder 120b and the seventh output signal from the decoder 220b, an AND gate 130f intended to perform an AND operation as a function of the outputs of the OR gate 130e and of the AND gate 110a, an AND gate intended for perform an AND operation as a function of the outputs of the AND gate 110b and of the inverters 130a and 130b and of the inverted signal of the first output signal from the decoder 220b, an AND gate 130h intended to perform an AND operation according to the output of the door AND 11Oc and the eighth output signal from decoder 220b, an AND gate 130i intended to perform an AND operation as a function of the output signals from AND gate 110a and inverters 130d and 230b, an AND gate 130j intended to perform an AND operation as a function of the output signal of the AND gate 110b and the first output signal of the decoder 220b, an AND gate 130k intended to perform an AND operation as a function of the output signals of the AND gate 110c, of the inverter 130c and of the inverted signal of the eighth output signal from the decoder 220b, an AND gate 1301 intended to perform an AND operation as a function of the output signals of the AND gates 130f, 130g and 130h, and a AND gate 130m intended to perform an AND operation as a function of the output signals from the gates 130i, 130j

and 130k.

  The next column generator 230 includes an AND gate 230e intended to perform an AND operation as a function of the output signals of the AND gate 210b and of the inverter 130d and of the eighth output signal of the decoder 120b, an AND gate 230f intended to carry out an AND operation as a function of the output signals of the AND gate 210b and of the inverter d, an AND gate 230g intended to carry out an AND operation as a function of the first output signal of the decoder 120b and of the output signal of the AND gate 210a, an OR gate 230h intended to perform an OR operation as a function of the output signals of the AND gates 230e and 230f, an AND gate 230i intended to carry out an AND operation as a function of the first output signal of the AND gate 210C and seventh output signals from decoder 120b, an AND gate 230j intended to perform an AND operation as a function of the output signal from AND gate 210a and second output signals from decoder 220b, u an AND gate 230k intended to perform an AND operation as a function of the output signal of the AND gate 210b and the first output signal of the decoder 120b, an AND gate 2301 intended for an AND operation as a function of the output signals of the AND gate 210c , from the inverter 130b and from the inverter 230c, an AND gate 230m intended to perform an AND operation as a function of the output signals of the AND gates 230g and 230i and of the OR gate 230h, and an AND gate 230n intended to effect an AND operation according to the output signals of the

AND gates 230j, 230k and 2301.

  The operation of the zigzag scanning address generator according to the above configuration, goes to

present be described.

  With the input of a logic validation signal "high" EN, the output states of flip-flops D 11Od and e become "00" and the output states of flip-flops D 210d and 210e become "10". That is, the row state becomes an "OFF" state as shown in Figure 2A, and the column state becomes an INCREASES state as shown in Figure 2B. At this time the outputs of the first and second up / down counters 120 and 220 are reset, and the outputs 01 of the decoders 120b and 220b are both at "1u, while the other outputs are all at" 0 ". The resulting address outputs R (n) and C (n) become "000 000". Then the outputs of OR gates 130 and 130m are "1" and "O" respectively, and the outputs of OR gates 230m and 230n are "0" and u "1", respectively. Then, with the input of a logic validation signal "high" EN, the output states of flip-flops 110d and 110e become "10" and the output states of flip-flops 210d and 210e become "01" ". That is, the row state becomes an INCREASE state" as shown in FIG. 2A and the column state becomes a "DECREASE" state as shown in the

Figure 2B.

  At this time the output of the counter 120a is maintained, the output of the counter 220a becomes "001" and the output 02 of the decoder 220a becomes "1", while

  the other outputs of the decoder 220a are all "0".

  The resulting address outputs R (n) and C (n) become "* 000 001". Thus the outputs of OR gates 1304 and 130m become "1" and "0o", respectively, and the outputs of OR gates 210d and 210e become "0" and "0", respectively. Then, with the input of a logic validation signal "high" EN, the output states of flip-flops 110d and 110e become "10" and the states of

  output of flip-flops 210d and 210e become "00".

  That is, the row state becomes a "GROWTH" state as shown in Figure 2A, and the column state becomes a "STOP" state as shown in Figure 2B. Thus the output of the counter 120a becomes "001" and the output of the counter 220a becomes OOO. That is, the resulting address output

becomes 001,000 ".

  In the present invention, n represents the number of binaries and, in the above embodiment, n is equal to three. However, for higher values of n, an identical circuit configuration is possible

  by simply adding the corresponding register.

  In the operating procedure, the states make the transition according to the row and column state tables. The row and column addresses have a new state - or maintain the previous state at each clock pulse according to the diagrams in the figures

2A and 2B.

  It is obvious to a person skilled in the art that other embodiments of the present invention can be accomplished by scanning the data from a memory using a zigzag scanning method when decoding the data, as this is the case

  with the method described above.

Claims (9)

  1. Zigzag scanning address generator comprising: line address generation means (100) intended to generate a line address signal which stops, increases or decreases a state present in response to a validation signal ( IN); column address generation means (200) for generating a column address signal which stops, increases or decreases a present state   in response to said validation signal (EN).   2. Zigzag scanning address generator according to claim 1, in which said means (100) for generating line addresses (100) comprises: means for memorizing and decoding line states (110) intended to responding to a validation signal by receiving a next line state signal and thereby decoding said next line state signal; first up / down counting means (120) intended to count up / down the output signal of said means for storing and decoding row states in response to them, and to generate a column address signal; and next line state generating means (130) for generating a next line state signal by receiving output signals from said line state storage and decoding means, the output signals from said first up / down means and column address signals. 3. Zigzag scanning address generator according to claim 2, in which said means for memorizing and decoding line states comprise: first and second flip-flops having an initialization input access initialized by said validation signal and a reset connection connected to ground, intended respectively to receive the output signal of said generator of following line states at its data entry ports; first AND operation means for performing an AND operation as a function of the inverted output signals from said first and second flip-flops; second AND operation means for performing an AND operation as a function of the output signal of said first flip-flop and the inverted output signal of said second flip-flop; and third AND operation means intended to carry out an AND operation as a function of the inverted output signal of said first flip-flop and of the signal   output of said second flip-flop.   4. A zigzag scanning address generator according to claim 3, in which said first up / down counting means comprise: a first up / down counter having a holding access which receives the output signal of said first AND operating means and a up / down counting access which receives the output signal of said second AND operating means, intended to count in response to the output signal of said second AND operating means, so as to thus generate a line address signal with three binary numbers ; and a first decoder intended to decode the signal of   output of said first up / down counter.   5. A zigzag scan address generator according to claim 1, wherein said column address generation means (200) comprises: means for storing and decoding column states (210) intended to respond to a enabling signal by receiving a next column status signal and thereby decoding said next column status signal; second up / down counting means (220) for counting / down counting in response to the output signal from said column state storage and decoding means, and for generating a column address signal; and next column state generating means (230) for generating a next column state signal by receiving the output from said column state storage and decoding means, and the output signals said second up / down counting means and the signals column addresses.   6. Zigzag scanning address generator according to claim 5, in which said means for storing and decoding column states comprises: a third flip-flop intended to receive a first output signal from said generator of states of lines following to its data input access, its initialization input access being initialized by said validation signal and its reset access being connected to ground; a fourth flip-flop intended to receive a second output signal from said generator of following line states at its data input access, its reset input access being reset by said validation signal and its initialization access being at the mass; fourth AND operation means for performing an AND operation as a function of the inverted output signals from said third and fourth flip-flops; fifth AND operation means for performing an AND operation as a function of the output signal of said third flip-flop and the inverted output signal of said fourth flip-flop; and sixth AND operation means intended to perform an AND operation as a function of the inverted output signal of said third flip-flop and of the signal   output of said fourth flip-flop.   7. Zigzag scanning address generator according to claim 6, in which said second up / down counting means comprise: a second up / down counter having a holding access which receives the output signal of said first AND operating means and a up / down counting access which receives the output signal of said second AND operating means, intended to count in response to the output signal of said second AND operating means, so as to thereby generate a column address signal with three binary ; and a second decoder intended to decode the signal of   output of said second up / down counter.   8. A zigzag scanning address generator according to claim 4 or 7, wherein said following line state generation means comprise: first, second, third and fourth inverters intended to invert the eighth, seventh, second and first output signals from said first decoder; first OR operation means for performing an OR operation as a function of the first output signal from said first decoder and the seventh output signal from said second decoder; seventh AND operation means for performing an AND operation as a function of the output signal of said first OR operation means and of the output signal of said first AND operation means; eighth AND operation means for performing AND operation based on the output signals of said second AND operation means and said first and second inverters and the inverted signal of the first output signal of said second decoder; ninth AND operating means for performing an AND operation as a function of the output signal of said third AND operating means and the eighth output signal of said second decoder; tenth AND operation means for performing AND operation based on the output signals from said first AND operation means and said fourth inverter and the seventh inverted output signal from said second decoder; eleventh AND operation means for performing an AND operation as a function of said second AND operation means and the first output signal of said second decoder; twelfth AND operating means for performing an AND operation according to the output signals from said third AND operating means and said third inverter and the eighth inverted output signal from said second decoder; thirteenth AND operating means for performing an AND operation as a function of the output signals from said seventh, eighth and ninth AND operating means; and fourteenth AND operation means for performing an AND operation as a function of the output signals of said tenths, eleventh and twelfth means AND.   9. A zigzag scanning address generator according to claim 4 or 6, in which said following column state generation means comprise: fifteenth AND operation means intended to carry out an AND operation as a function of the output signals of said fifths AND operating means and of said fourth inverter and of the eighth output signal of said first decoder; sixteenth AND operating means for performing an AND operation as a function of the output signals from said fifth AND operating means and said fourth inverter; seventh AND operation means for performing AND operation as a function of the first output signal from said first decoder and the output signal of said fourth AND operation means; second OR operating means intended to perform an OR operation as a function of the output signals of said fifteenth and sixteenth AND operating means; eighteenth AND operation means for performing an AND operation as a function of the output signal of said sixth AND operation means and the seventh output signal of said first decoder; nineteenth AND operation means for performing an AND operation as a function of the output signal of said fourth AND operation means and the second output signal of said second decoder; twentieth AND operating means for performing an AND operation as a function of the output signal of said fifth AND operating means and the first output signal of said first decoder; twenty-first AND operation means for performing an AND operation as a function of the output signals from said sixth AND operation means, said second and seventh inverters; twenty-second AND operation means for performing an AND operation as a function of the output signals from said seventeenth and eighteenth AND operation means and said second OR operation means; and twenty-third AND operation means for performing an AND operation according to the   exit of said nineteenths, twentieths and twenty-and- second means of operation AND.