FR2698188A1 - Computer cache memory and method for producing control signals from such a memory. - Google Patents

Abstract

Zero wait state system cache (207) for use in computer systems. The present invention uses groups of non-interlaced asynchronous static random access memories with separate control lines. Zero wait state operation is achieved (202) by correlating control signals on the cache memory to control clock signals used by the processor such that there is a zero delay when switching. providing the system clock signal and cache control signals. Processor burst access (201) to memory is supported by an internal sequencer which determines subsequent burst addresses based on an initial burst address generated by the processor.

Description

The present invention relates generally to the field of systems

  second level cache memories which represent the level of the memory hierarchy in a computer system located between the central processing unit (CPU) cache and the

main memory.

  Historically, the search for performance for microprocessor technology has progressed at a faster rate than the search for performance for technologies of information carriers such as DRAM (dynamic random access memory) and logic.

  (TTL) / programmable (Logic Transistors-

  Transistors / Programmable) Recent trends further exacerbate this mismatch in the following ways First, the clock speeds of the microprocessors quickly approached, and in some cases exceeded the clock speeds of the support logic. standard information In addition, the number of clock pulses per instruction has decreased rapidly, resulting in a very high bandwidth requirement for memories. More recent designs such as RISC architectures even require a bandwidth of the

  larger memory to run the same amount of work.

  The memory bandwidth requirement has been further increased by the need for direct memory access (DMA) in devices such as coprocessor or multiprocessor devices Finally, the speed at which new devices are introduced the market is accelerating, making the problems that

previous.

  As a result of these trends, performance bottlenecks have emerged and they continue to influence the way systems are designed Memory bandwidth, as a performance limiter, has already resulted in memory usage caches in many microprocessor systems For example, the use of cache memories is in common use in the generation of 386 microprocessors (registered trademark) manufactured by Intel Corporation In addition, Intel 486 processors (registered trademark ) and i 860 (registered trademark) (also called i 860 XP (registered trademark)) from Intel include caches on chip arrays in order to increase performance It is clear that other modifications in the memory hierarchy ( primary cache, secondary cache, DRAM architectures, etc.) will be required to support

  performance increases in future generations.

  (Intel, 386, Intel 486, i 860 and i 860 XP are all brands

Intel Corporation).

  A didactic description of the concepts of cache memory

  can be found in the publication "Cache Tutorial" available from Intel Corporation, at the following address: Literature Sales, PO Box 7641, Mt Prospect, IL 60056-7641, US A Known cache memories are designed in two levels: first level cache and second level cache A first level cache is a single layer of high speed memory between the microprocessor and the DRAM memory of the main system The first level caches keep copies of the codes and data most frequently used by the microprocessor The first level caches typically have a small size (4 K-bytes to 64 K-bytes) The first level caches can be either internal or external to the device (which is for example a microprocessor) which

constitutes the processor.

  A second level cache is a second layer of high speed memory located between the first level cache and the DRAM memory of the main system. The second level caches also keep copies of the codes and data frequently used by the microprocessor. second level are typically external to the device that constitutes the processor A second level cache handles more RAM requests than those that the first level cache lets or misses In order to simplify the handling of requests that the first level cache misses, the second level cache typically includes all data from the first level cache and and also includes other data. As a result, a second level cache is always larger (64 K-bytes to 512 K-bytes) than a cache of

first level.

  In order to obtain optimal performance, it is desirable that the cache performs operation with zero wait state The absence of a wait state at zero implies that the processor does not have to wait for data coming from the cache memory For example, the timing according to which the cache memory produces valid data on the data bus should not cause the processor to waste valid data waiting cycles. Known systems ensure operation with zero waiting state in using a particular type of static random access memory (SRAM) called "burst SRAM" or "synchronous SRAM" or by using interleaved groups of SRAM which are accessed alternately A negative aspect of using a "burst SRAM" is its cost A "burst SRAM" is more expensive than a conventional asynchronous SRAM. SRAM's interleaved groups add a certain amount of logic and control circuit to a cache controller In addition, the use of an interleaved structure leads to data bus conflicts during switching between groups This phenomenon of conflict has effects on the timing of the system since during the period during which a given group is deactivated and another group is activated, the two groups may have to cause data on the same line of bus This reduces the long-term reliability of the SRAM components themselves In addition, caches implemented using interleaved SRAM groups cost more than those using non-interleaved groups although their cost is lower than that of a burst SRAM. Thus, an essential object of the present invention consists in proposing a cache controller having an operation with zero waiting state without the high cost of burst SRAMs and

  without reduced reliability of an interlaced cache structure.

  Another object of the present invention is to provide a cache system which uses conventional asynchronous SRAM devices, which reduces the overall cost of the system. A system cache memory with zero wait state for use in computer systems is described. The present invention uses non-interleaved asynchronous static random access memory (SRAM) groups, each of which is controlled independently. The components used

  are conventional level asynchronous SRAM chips.

  Using a non-interleaved data access scheme eliminates data conflicts. In addition, independent control of memory groups allows the cache controller to support larger cache sizes while at the same time suggesting greater savings. since all

  groups do not have to be used.

  Zero standby operation is achieved by correlating cache control signals relating to

  the clock and control signals used by the processor.

  In the presently particular embodiment of the present invention, the correlation is carried out by 1) clocking cache operations at twice the clock frequency of the microprocessor and 2) by correcting the asymmetry of the control signals resulting from the circuit channels different ones provided for each of the cache control signals The asymmetry of the control signals is corrected by identifying the control signal or signals having maximum delays and then introducing a delay circuit in the circuit of the control signals and clock

with less delays.

  Processor burst access to memory is supported by an internal sequencer which predicts subsequent burst addresses based on the initial addresses produced by

the processor.

  The present invention will be better understood in the light of

  the description which follows which will be read in relation to the drawings

  annexed among which: FIG. 1 is a block diagram of a computer system in which the presently particular embodiment of the present invention can be implemented; FIG. 2 is a functional diagram of a circuit implanted on a group of chips which can be used to constitute a base for a computer system as shown in FIG. 1, the presently particular embodiment of the present invention being a component of this circuit implanted on a group of chips; Figure 3 shows the signal interfaces for a cache DRAM controller (CDC) component of the presently particular embodiment of the present invention; FIG. 4 is a block diagram which represents the interfaces of the signals of the cache controller when using static random access memory (SRAM) groups of the presently particular embodiment of the present invention; FIG. 5 is a block diagram of the functionality of the cache controller of the presently particular embodiment of the present invention; FIG. 6 is a timing diagram for explaining a read intervention, by means of an operation with zero waiting state, and a double write or delayed write write mode, in the presently particular embodiment of the present invention; FIG. 7 is a time diagram for explaining a writing intervention by means of an operation with zero waiting state in the duplicate writing mode in the presently particular embodiment of the present invention and FIG. 8 is a time diagram for explaining a write intervention by operating with zero waiting state in the delayed write mode in the write mode

  presently particular embodiment of the present invention.

  A circuit which implements a controller for a

  cache system is described In the following description,

  many specific details are highlighted, such as the specific numbers of bytes, bits, devices, etc. in order to ensure a thorough understanding of the particular embodiment of the present invention. It will be apparent to those skilled in the art that the present invention can be implemented without these specific details Furthermore, well-known circuits have been represented in the form of a functional diagram instead of being in detail in order to avoid complicating in a non-compliant manner.

  necessary description of the present invention.

  During the description of the present invention, a

  Frequent reference can be made to the use of the cache controller invented in conjunction with certain specific CPU architectures and / or with certain types of microprocessors

  specific such as the Intel 486 DX microprocessor from Intel.

  These implementations simply reflect the presently particular embodiment of the present invention. It is understood that the concepts implemented in the present invention may apply or may be extended to other

  types of processors as well as other types of architectures.

  Furthermore, when describing the present invention,

  reference is made to mode specific signal names

  presently a specific embodiment A description of

  each of these signals is produced in the text and in appendix A A reference made to these names of specific signals should not be considered as limiting the scope of the present invention.

  GENERAL OVERVIEW OF A COMPUTER SYSTEM IN THIS MODE

OF REALIZATION

  The presently particular embodiment of the present invention can be implemented for use in a computer system such as that shown in FIG. 1 The present invention can be implemented on a microcomputer for use general such as one of the members of the family of IBM compatible personal computers (registered trademark) or on one of the numerous workstation or graphics computer devices which are currently commercially available A computer system such as optionally used by the particular embodiment generally comprises a bus or other communication means 101 making it possible to communicate information, a processor means 102 coupled to said bus 101 for processing information, a random access memory (RAM) or any other other storage device 103 (conventionally called main memory) coupled to said bus 101 for storing information and instru ctions for said processor 102, a read only memory (ROM) or any other static storage device 104 coupled to said bus 101 to store static information and instructions for said processor 102, a data storage device 105, such as a disk magnetic and a disk drive, coupled to said bus 101 for storing information and instructions, an alphanumeric input device 106 including alphanumeric keys or the like, which device is coupled to said bus 101 for communicating selections of information and of commands to said microprocessor 102, a cursor control device 107 such as a mouse, a movement ball, cursor control keys, etc., which device is coupled to said bus 101 to communicate selections of information and commands to said processor 102 and to control the movement of the cursor In addition, it is useful that the system includes a copy device on paper support ier 109 such as a printer to produce permanent copies of information The paper copy device 109 is coupled to processor 102 through the

bus 101.

  Note that in the above description, the bus

  101 is used in a generic sense to indicate a coupling between the various components contained in the computer system As will be described in more detail below, the bus 101 may in fact be constituted by a plurality of structures buses each of which is interconnected to the others and each of which is used to support a class

device specific.

  GENERAL OVERVIEW OF THE SYSTEM EMBODIMENT

  The presently particular embodiment of the present invention is implemented in a component of

  computer system called Cache DRAM Controller (CDC).

  The term DRAM is a well-known term which relates to memory devices known as dynamic random access memories DRAMs are conventionally used as main memories of computer systems Whatever the case, the CDC is part of a chip array A chip array refers to a collection of intimately linked integrated circuits, which circuits fulfill the functionality of the heart of a computer system The use of array chips significantly reduces the effort involved in the design, manufacture and testing of a

computer system.

  The chip grouping of the presently particular embodiment is described with reference to FIG. 2 The components of a chip group are a CDC 202, a microprocessor 201, a data channel unit (DPU) 203 and a data unit system input / output (SIO) 204 The chip grouping of the present invention interconnects three different chip structures A host bus is designed internally for specific devices, for example the processor, the coprocessor and the system memory A bus Peripheral Component Interface (PCI) is intended to couple input / output (I / O) devices suitable for PCI to the system. Finally, a bus interface whose architecture corresponds to the industry standard architecture (ISA) is provided to allow connection of an existing class of I / O devices to the system In general, the bus PCI works faster than the ISA bus and provides a different functionality It should also be noted that each of these buses

  contains sub-buses of data, addresses and commands.

  The DPU 203 provides data bus connections for the microprocessor, for the local bus and for the DRAM data bus The SIO 204 serves as a bridge between the PCI local bus and an ISA bus In addition, it incorporates a DMA controller ISA compatible, a timer / counter and an interrupt controller and it also incorporates PCI local bus arbitration logic The microprocessor 201 of the presently particular embodiment is one of the microprocessors at 25 or 33 M Hz i 4865 X , i 487 SX, i 486 DX, i 486 DX 2 or other Intel microprocessors compatible with bus or higher class processors, all these processors being available from Intel Corporation, Santa Clara, California and constituting of

  designations of registered trademarks.

  In the presently particular embodiment, the CDC 202 includes a dual port DRAM controller which interfaces the DRAM 206 with respect to the host CPU bus and the PCI bus. The DRAM controller sends addresses 213 and signals commands 214 to the DRAM 206 as well as control signals from DPU 215 to the DPU 203 This results in the transfer of data to the DPU 203 and then to the processor 201 The CDC 202 supports an organization of DRAM interleaved with bidirectional communication The CDC 202 also includes a cache controller which supports 64 K-bytes, 128 K-bytes, 256 K-bytes or 512 K-bytes of a secondary cache which uses standard asynchronous SRAMs The CDC's integrated cache controller supports either duplicate write cache protocols or write-back cache protocols CDC provides other functionality to the computer system, including generation of system clock and

  production of a system reset logic.

  As described in more detail below, the generation of the system clock plays a role in obtaining the

  cache operation with zero waiting state.

  Referring again to FIG. 2, a host bus 205 is used to couple the processor 201 to critical system components such as the DRAM 206, the cache memory arrangement 207 and a coprocessor 208 It should be noted that the arrangement of cache memory includes all the labels (called TAG) and data (DATA) as well as other storage areas necessary for the cache system A second bus, in this case a PCI bus 209, is used to couple components of second row In the PCI architecture, the components can be either master devices 210 or slave devices 211 A master device is a device which can drive and control the PCI bus 209 A slave device is a device which responds to requests from of a master device on the PCI bus 209 or from another component defined as a master component which can be physically placed on another bus Finally, an ISA bus 212 is used to pair devices

ISA compatible.

  The present invention relates to the cache controller part of the CDC 202 However, it will be apparent to those skilled in the art that the present invention can be implemented as a discrete component or can be packaged as a component having a functionality more important The present invention can be implemented either as

  first level cache, either as a second level cache.

  1 1 Furthermore, the present invention relates to a cache system which is external to the microprocessor. In the present particular embodiment, the cache is a second level cache. This is due to the fact that the microprocessor supported in the particular embodiment includes an internal first level cache However, it will be apparent to those skilled in the art how to implement the present invention as

first level cache.

  Signal interfaces Figure 3 shows the interface modules and signal interfaces for the CDC component of the operating mode.

  presently particular realization.

  With reference to FIG. 3, a host CPU interface module 301 is used for coupling to the host processor The specific signals are produced on a higher class processor via a higher class processor interface module 302 A processor of higher class is a processor which replaces an original processor A processor of higher class achieves an increased performance compared to that of the original processor The cache control interface 303 is used to make an interface with the groups of cache memories An interface of DRAM control

  304 is used to interface with the system DRAM.

  A PCI 305 local bus interface is an interface to

  local bus screw A reset and clock module 306 produces system clock signals while receiving the clock signal 2 X Finally, a DPU control interface 307 constitutes a vis- with respect to the DPU unit of

  chip array A full description of all

  signals is produced in Appendix A. Figure 4 is a block diagram which represents the coupling of the cache controller interface signals with the various other components The cache write enable signals (CWE 3 #, CWE 2 #, CWE 1 #, CWEO #) and the chip exit validation signal (COE #) are respectively coupled to each group taken from the SRAM groups, to group 401 and to group 402 A chip selection signal (respectively CC 51 # and CC 52 #) is coupled to validate each of the groups 401 and 402 The label part of each of the SRAM groups, here represented in 403, as well as valid bits 404 are coupled to receive the validation signals d 'write (TWE #) and output validation (TOE #) The write validation signal allows the updating of the label part The output validation signal allows the reading and the use of the content of the label part The label parts 403 and the bits goes lides 404 are also coupled to label areas of

  the address produced by the processor (HAl 31: 2 l).

  Modification bits 406 corresponding to lines contained in the SRAM groups are used to signal that a corresponding line in the SRAM has been modified This

  is controlled by signals DWE #, DIRTYD and DIRTYQ.

  In addition, CA (3: 2), CA (18: 4) cache addresses are coupled to groups 401 and 402 to access locations in cache groups. Finally, the cache latch enable signal 405 (CALE) is coupled to a locking device which is used to

  create addresses on a cache address bus (CAl 18: 4 l).

  Cache system of the presently particular embodiment In the presently particular embodiment, a first level cache system is integrated in the presently specific i 486 microprocessor. The organization of the cache is a game of 4 ways: associative and each line of cache has a width of 16 bytes The first level cache memory is physically separated into 4 blocks with 2 K-bytes each of which contains 128 lines Labels of 12821 bits are associated with each block of 2 K-bytes Labels are used to identify the contents of a corresponding entry in the cache memory The writing strategy used is a duplicate writing Other details on the top-level cache Intel 486 can be found in the publication Microprocessors Volume I available from Intel Corporation

  via Intel Literature Sales, P O Box 7641, Mt Prospect, IL 60056-

  7641. The second level cache is a direct implementation in which each cache line has a width of 16 bytes The cache can have a dimension of 64 K-bytes to 512 K-bytes The write strategy can be either a write in double or a delayed write The writing strategies

  are discussed briefly below.

  In the presently particular embodiment, the writing strategy for the second level cache may be different from that for a first level cache. However, an implementation of first and second level caches which

  uses writeback strategies is not supported.

  In the duplicate write strategy, each intervention operation on the cache is accompanied by a writing of the same data in the main memory In a deferred write strategy, the cache is updated during the operation d write but actual main memory is updated

  when the line is disconnected from the cache.

  The CDC cache controller portion produces independent control signals for asynchronous static random access memory (SRAM) groups. SRAM devices are desirable for use in cache systems because of their high access speed to data It is desirable to use asynchronous SRAMs due to their lower cost In addition, since the groups are not interleaved and are controlled independently, the same controller can be used to support various cache sizes In order to obtain operation with zero waiting state, by means of non-interleaved groups of SRAMs, the cache controller correlates the control signals applied to the SRAM groups with the system clock. It is recalled that the CDC is

  used to derive the system clock signal.

  Figure 5 is a block diagram of the functionality of the cache controller. As mentioned above, the CDC produces timing for the system clock. As noted in Figure 5, a 2 X 501 clock signal is produced on the CDC. 510 o it is converted to a 1 X signal by a 2 X to 1 X converter 504 Means for converting a 2 X clock signal to a 1 X clock signal are known in the art Any of these well known means can be used The signal from the converter 504 is then produced on a delay equalizer element 505 The delay equalizer element 505 introduces the prescribed delays in order to create a 1 X 502 clock signal which includes delays zero with respect to cache control signals 507 The 1 X clock signal is then

  applied on a microprocessor 503.

  The clock signal 2 X is used to drive control signals 507 for the cache memory 506 The clock signal 2 X is applied to a means for generating the cache control signal 508 The means for generating the control signal cache 508 generates cache control signals The output of the cache control signal generation means 508 is then applied to a delay equalizer 509 The delay equalizer 509 is used to correct an asymmetry of transmitted control signals output from the cache control signal generating means

508.

  Although the presently particular embodiment of the present invention uses a 2 X clock signal to drive the cache control signal generation means 508, it will be apparent to those skilled in the art that it is possible to use other clock signals of different frequencies The key point is that the cache control signals are zero delay from the system clock This key point is called correlated clock pattern The way in which the correlated clock diagram is made in the embodiment

  currently specific is the subject of a discussion below.

  Correlated clock scheme The correlated clock scheme ensures a correction of the asymmetry which can occur in relation to the emission at the output of control signals outside the CDC This asymmetry occurs due to inherent delays resulting from the

  circuit of the various control signals passing through the CDC chip.

  In order to improve the performance, these asymmetries must be corrected. By means of the correction of these asymmetries, a timing of signals can be controlled more precisely. By virtue of this precise control and by means of timing of the control signals d By a 2 X clock, a delay of zero in providing a system clock signal and the cache controller signal is obtained. The correlated clock diagram has several constraints This includes: 1 The generation of the system clock is performed on

the chip.

  2 The delay between any input and resulting output on an integrated circuit chip can vary widely as a result of the manufacturing process, the

  operating temperature and voltage.

  3 All input signal / output signal channels located on the same chip show the same variations due to the manufacturing process, the temperature of the

operation and voltage.

  4 The output signals which share the common or similar circuits and which are derived from a common input signal have identical delay characteristics and a minimum asymmetry with respect to each other This asymmetry results from small process variations, temperature and voltage because intrinsic circuit delays "follow" each other in the given circuits. By using constraints, the circuit channels of the control signals are modified in order to eliminate the asymmetry when supplying the control signals. The asymmetry is undesirable since it causes timing delays, which requires the introduction of 'waiting states.

  Standby states degrade system performance.

  A correlation of the timing signals of the presently particular embodiment has been obtained through iterations of timing simulations and the introduction of gate delays in the particular circuit lanes First, the control signal which has the longest delay is determined When this signal is determined, the circuit path for other control signals can be extended as required This extension can be achieved for example by introducing pairs of reversers in the control signal circuit These means are illustrated above in FIG. 5 as equalizing elements

late 505 and 509.

  Address order prediction Address order prediction produces burst data cache mode transfer Note that transfer burst mode is a feature of the Intel i 486 family of microprocessors. Essentially, this mode achieves a rapid transfer of data on the basis of a produced address It should be noted that in known implementations, the device must always read the address of all the data

  which it must access from the address bus.

  Ideally, the burst mode of operation uses 5 clock cycles, two to get the first data and each of the following data produced in the next cycle. A problem with supporting a burst mode transfer is that an address produced by the CPU can delay the time necessary to read or write the data A prediction of the address order eliminates the need to consult each address A prediction is made on the basis of an observation of the reasons for addressing data to the using the Intel i 486 system These are the second and third lower order address bits (ie A 2 and A 3) of the first address which are examined This is due to the fact that the AO bits and Ai are ignored by the microprocessors of the presently particular embodiment (for example Intel 486) for the purpose of cache line addressing For the particular values of A 2 and of A 3, a first address pattern corresponds to spondant is identified This correspondence is as follows

00 = O

01 = 4

= 8

  1 i = C Remember that the cache is addressed as double word lines (i.e. 4 bytes). Thus, the first double word is at line address locations 0, the second double word is at line address locations 4, the third double word is at line address location 8 and the fourth double word is at line address locations C. From the first identified address, the corresponding sequence next address is obtained

0 4 8 C

4 O C 8

8 C O 4

C 8 4 O

  These sequences are obtained from the fact that a memory address can occur at any point on the cache line. The appropriate data are then accessed in accordance with the appropriate address sequence and are

  produced for each subsequent processor cycle.

Timing diagrams

  Descriptions of timing diagrams of various

  hidden operations follow They are not intended to be exhaustive but only representative of the operations of the code system It should be noted that in order to completely convey the sequence of operations, signals not generated in the cache controller have been included Furthermore, all the signals intended for the cache controller are shown but they may not be used for a particular operation Again,

  this is proposed for the sake of presenting a description

  complete. FIG. 6 is a timing diagram for a level two cache intervention read, with zero standby state The level two cache intervention reads are handled in the same way depending on whether the level two cache is in a duplicate or delayed write The cycle is initialized by ADS # 601 and it is ended by BRDY # 602 The ADS # 601 signal is produced by the processor while the BRDY # 602 signal is generated by the interface part of CDC CPU (as shown in figure 2) It should be noted that the signal BRDY # 602 is used for burst mode accesses A label comparison is completed before the falling edge of the clock cycle T 2 603 in order to determine whether or not it is a cache intervention or a lack of cache If it is a cache intervention, the signal BRDY # 602 is generated in the middle of the clock cycle T 2, on the falling edge of signal CLK 1 604, and it is sampled by the CPU at the end of the clock cycle T 2 603 The following DWORDS during the burst reading are sampled at the end of a consecutive clock cycle in order to complete the burst reading according to the clock cycles 2 -1-1-1 During level two cache intervention readings, the label, valid and modified bits corresponding to the DRAMs contained in the cache memory which are read remain unchanged. The signal CALE 605 is used to lock the address of CPUs in external transparent locking devices The lower address bits CA (3: 2) 606 are controlled directly by the CDC using the

  prediction of the order of addresses described above.

  FIG. 7 is a time diagram of a level two cache intervention write with zero waiting state in the double level two write mode. The cycle is initialized by ADS # 701 and it ends with zero state. waiting due to a write record at the DPU (from which data is then written to the DRAM memory) and the signal RDY # 704 is sent back to the CPU during the clock cycle T 2 702 As in the case of intervention reading, the label comparison is completed before the falling edge of the clock cycle T 2 701 and it is used to determine whether or not the CWE signals l 3: 0 l # 703 must be activated during the T 2 clock cycle 702 If this is an intervention, CWE l 3: O l # are produced during the second half of the T 2 clock cycle and the level two cache line is updated at the same time as that at which it is recorded in the DPU The CDC then initializes a DRAM write cycle which is completed shortly after clock cycles using the address recorded in the CDC and the data recorded in the DPU (the timing of the write cycle of

DRAM is not shown).

  FIG. 8 is a timing diagram of a level two cache intervention writing with zero waiting state in the level two deferred writing mode. The cycle is very similar to the case of the level two duplicate writing. except that the CDC does not initialize a DRAM write cycle immediately. The new data is written in the level two cache line and the modified bit corresponding to this line is marked with "DIRTY" to indicate that the data are different from the data contained in the DRAM DIRTYD 801 and DWE # 802 signals are used for this purpose The DWE # 802 signal has the same timing as CWE l 3: 0 l # 803 signals in that it cannot be produced before the intervention / lack of cache information is valid and in that it must also be abandoned before the end of the cycle with zero waiting state No data is recorded in the DPU

for this type of cycle.

  As it appears from the timing diagrams presented above, the cache control signals must be precisely aligned with the CLK 1 system signal. Although this is not shown, the cache control signals are triggered in relation to the 2 X clock signal applied to the CDC By means of this clock as well as the intimate signal correlation described above, operation with zero state

waiting can be obtained.

  So a system memory cache with zero wait state

  which uses non-interleaved groups of SRAM has been described.

ANNEX A

HIDDEN DRAM CONTROLLER SIGNALS

Host CPU interface Sicinals

Type Name Description

  spindle / Sig nal CPURST Output The reset signal of the CPU forces the CPU to start an execution for a known state The CPURST signal is applied each time the PWROK signal is at a low level or the CPURST signal is validated via the register TRC When the CDC is programmed for a type of CPU other than a higher class processor, this synchronous signal is also applied each time the signal SRESET # is active or a cut cycle is detected The CDC ensures at least in use a CPURST signal pulse of a width of 1 but however, a requirement of pulse width of reset to initialization of startup of 1 millisecond for the CPU must be satisfied by the inactive duration of the

PWROK signal.

Enter exit

  Al 31 2 l are the address lines of the CPU.

  Al 31 2 l as well as BEl 3: O l # of byte validation define the physical area of the

  memory or input / output space accessed.

  Al 31: 4 l are used to drive addresses in the CPU and in the secondary cache in order to perform cache listening (interrogation) cycles Al 3: 2 l are not used by the CPU during listening cycles but however, they are driven at a low level by the CDC instead

  that these signals be allowed to float.

  BEl 3: O l # Input Byte validation signals indicate active bytes during read and write cycles BE 3 # applies to Dl 31: 24 l, BE 2 # applies to Dl 23: 16 l, BE 1 # applies to Dl 15: 8 l and BEO # applies to

Dl 7: O l.

Al 31: 2 l

HLOCK #

  PLOCK entry # | Input The bus lock signal indicates that the current CPU bus cycle is locked HLOCK #, controlled by the CPU, becomes normally active during the first clock of the first bus cycle locked and normally becomes inactive during the last clock of the last cycle locked HLOCK # becomes active for

  read-modify operations

  write Locked operations are a combination of one or more read cycles followed by one or more write cycles. For the higher class processor, before a locked cycle is generated, the higher class processor checks if the line is in an M state If this is the case, the higher class processor performs a delayed write then applies

  the cycle locked on the external bus.

  The pseudo-lock signal indicates that the current CPU bus transaction requires more than one bus cycle to complete. Examples of these operations are long floating (64 bit) read and write, table descriptor reads segments (64 bits) and lazy read and write cycles of higher class processor cache line (256 bits) The signal PLOCK # is made active until the addresses for the last bus cycle of the

transaction are piloted.

  The memory / input-output, data / command and write / read lines are primary bus cycle definition signals.The following table describes the

bus cycles.

M / 10 D / C #

  low low low low high high high high low low high high low low high high WR_ # Bus cycle initialized low Interrupt acknowledgment high Stop special cycle low Read 1/0 high Write 1/0 low Code read high Reserved low Read memory top ADS memory write # Input The address input indicates that a valid bus cycle definition, byte validations and addresses are available on

their corresponding pins.

  RDY # Input The ready output with no burst indicates

  that the current bus cycle has ended.

  RDY # indicates that the system presented valid data to the CPU in response to a read or that the system accepted data from the CPU in response

to a writing.

  M / 10 # D / C # W / R # Input Input Input BRDY # Input The output ready with burst performs the same function during a burst cycle as RDY #

  performs during a non-burst cycle.

  BRDY # indicates that the system has presented valid data in response to a read or that the system has accepted

  data in response to a write.

  BOFF # Output The interrupt output signal with resume point forces the CPU to float its bus for the next clock The CPU remains in a bus hold state until BOFF # is negative BOFF # is used to end a CPU cycle when the system resource being accessed is not readily available and there is a deadlock event If a bus cycle is taking place when BOFF # is produced, the cycle is restarted by the CPU from the point where it

is interrupted.

  For the higher class processor, if a modified delayed line write due to an external listening is pending in the processor, it is output when BOFF # is made negative but before the interrupted cycle is restarted. Output The address maintenance output signal forces the CPU to float its address bus during the next clock The CDC applies this signal in preparation for carrying out a cache invalidation (i 4865 X, i 487 SX, i 486 DX, i 486 DX 2) or cache interrogation cycles (higher class processor) The CDC always controls the address on the host bus starting from the third clock on which AHOLD is applied and it continues to control addresses until AHOLD is

made negative.

  EADS # Output This signal indicates that a valid external address has been driven on the CPU address lines This address will be used to perform an internal cache invalidation

  or a cache interrogation cycle.

  KEN # Output The cache enable output signal is used to indicate whether or not the current cycle can be hidden in the internal CPU cache (primary or

first level).

  PWT Input The double page write input signal indicates that the current memory cycle can be hidden in the secondary cache if it is enabled in the mode.

duplicate writing.

  AHOLD PCD / Input The page cache invalidation input pin, when active, indicates that the current cycle cannot be hidden in the secondary cache during a cache line filling operation When PCD is applied, the link is not hidden in Ll or L 2. HITM # Input The modified cache intervention / DIRTYQ input pin indicates that an intervention on a

  modified data cache has occurred.

  HITM # is sampled two clocks

after EADS # is applied.

  PCD / Input The cache pin is active simultaneously CACHE # on the first ADS # until the first transfer When filling lines, the functionality of the CACHE # signal is identical to that of the PCD signal CACHE # is applied for each line half-filling cache During write-back cycles, CACHE # is applied only during the first half of line filling The start of a write-back cycle is identified only by ADS #, W / R # and CACHE # together The beginning of 'Listening writeback is identified by ADS #, W / R #, CACHE # and HITM # which are activated together. INV Output The invalidation output signal specifies / DWE which end state (invalid or shared) a cache line transiently undergoes until the possibility of a cache intervention during a CPU interrogation cycle. Output The initialization signal forces the CPU to

  start an execution for a known state.

  The internal state of the processor is the same as the state after RESET except that the internal caches, the machine check registers and the floating point registers retain the values they had before INIT INIT is applied by the CDC each once SRESET # is sampled as active and a cut-off cycle is detected or a hot reset sequence is initiated via the TRC register The CDC ensures a minimum pulse width of 4 clocks for the

INIT signal.

  Level 2 Cache control interface

Type Name Description

  pin / LCAl signal 3: 2 l Output Signals l 3: 2 l cache address generate the burst sequence required by the

  HCAl 3: 2 l CPU during secondary cache accesses.

  The CDC locks the burst address that begins and internally generates the following word addresses for the entire cache line These signals are correlated to the clock A separate set of CAl 3: 2 l signals is produced for the group lower and for the upper group so as to maintain the captive loading constant on

LCAl 3: 2 l and HCAl 3:21.

  INIT CC 51 # Output The lower group cache chip selection output signals indicate that the lower cache data group is

  selected for the current cache operation.

  Cache size Address space for active LCCS #

64K 0-32K

128 K 0-128 K

256 K 0-128 K

512 K 0-512 K

  CC 52 # Output The top group cache chip selection output signals indicate which cache data group is selected for the current cache operation The selected secondary cache dimension defines the address range in which

  these signals are controlled in the active state.

  Cache size Address space for active LCCS #

64K 32K-64K

128 K not active

256 K 128 K-256 K

  512 K not active CWEl 3: 0 l Output The cache write validation output signals provide a significant capacity for writing bytes to the secondary cache during cache line fills or cache write operations. COE # Output The cache output validation output signal is used to carry out the read cycles from the cache data SRAMs This signal is connected to the output validation pins of the data SRAMs

of cache.

  CALE Output The cache address lock enable output signal provides the proper control timing for the locks that create the CAl 18: 4 l cache address bus from the

  Al 18 host CPU address bus: 4 l.

  TWE # Output The label write enable signal is connected to the label SRAM write enable pin (WE #) TWE # is active during CPU read failure cycles when the

cache is updated.

  TOE # Output The label output validation signal controls the output validation pin of the label SRAMs When active, the label address and the valid bits are controlled in the CDC This signal is normally active and it is piloted in the inactive state only during an update

etiquette day.

  VALID Entry / The valid signal indicates the validity of the Exit data in the SRAM of cache data on a line by line basis VALID is used together with the address of label to make the decision intervention / failure of cache by the CDC S ' it is sampled at a low level during a CPU memory read cycle, the data is not valid in the cache During an invalidation cycle, the VALID signal is forced to a low level, which indicates that the data is not not valid. When VALID is sampled at O during the rising edge of the PWROK signal, then the CDC enters the test mode defined by the lines TAl 7: 4 l When VALID is sampled at a high level during the rising edge of the PWROK signal, the CDC

  enters normal operating mode.

  DIRTYD Output The modification input output signal indicates whether or not the data contained in the secondary cache is marked as modified. This signal is connected to the data input of the modified SRAM. HITM # Output The modification output signal indicates / DIRTYQ whether or not the data contained in the secondary cache is marked as modified This signal is connected to the

  modified SRAM data output.

  INV Output The modified bit write / DWE # validation output signal becomes active when the CPU performs a WRITE (write) cycle in the secondary delayed write cache This signal is connected to the WE # input of the

SRAM changed.

  The label address signals are directly connected to the label SRAM data bus The following table defines the relation which binds a label address and a CPU address according to the size of the secondary cache This mapping is produced by the CDC on the basis of

  dimensional configuration of the cache.

* TAl cache size 7: 0 l corresponds to 64 K-bytes Al 23:16 l 128 K-bytes Al 24:17 l 256 K-bytes Al 25:18 l 512 K-bytes Al 26:19 l These pins are also used as inputs to define connection options and CDC test modes. The TAl signal levels 7: 4 l are sampled during the rising edge of the

  PWROK signal to define the test mode.

  Refer to section 5 "Testability

  Considerations "for a description of

  test modes supported by the CDC Similarly, the TAl 2: 0 l signal levels are sampled during the rising edge of the PWROK signal to define the connection options described below: Siagnal TAl 1 connection options: 0 l Speed of the Host CPU, TA 2 bits

HCSl register 1: 0 l.

  Cache read / write write wait state, bit SCC l 2 TAl 7: 0 l Input / Output DRAM command interface

Type Name Description

  pin / EMAO signal, Output The OMAO multiplexed DRAM address bus, Output produces MAl 10: 1 row address information Column output for DRAMs External buffering is required Two signals constitute the address lines least significant multiplexed DRAMs, one for the even word (EMAO) and one for the word

odd (OAMO).

  RASl 3: 0 l # Output Each row address synchronization output signal corresponds to an eight-byte DRAM row These signals are used to lock the row addresses on EMAO, OMAO and on the MAl bus 10: 1 l in DRAMs These signals control the DRAMs directly without

any external buffers.

  CASl 7: 0 l # Output The column address synchronization output signals are used to lock the column addresses on EMAO, OMAO and on the MAl bus 10: 1 l in DRAM CASl 7: 0 l # corresponds to Byte lines 7: 0 of the two-way interleaved DRAM network with a width of eight bytes These signals drive the DRAMs directly without any external buffers. WE # / Output The write enable output signal MR / W # is externally buffered to drive the write enable inputs

(WE #) DRAM.

  Resetting the PCI bus to the original state forces each device's PCI interfaces to a known state All of the three CDC states of its bidirectional, open-collector PCI signals drive REQ # signals

  and MEMACK # in their inactive states.

  PCIRST is controlled during start-up and when an electrical action reset sequence is initiated via the TRC register. PCI address signals When the CDC plays the role of master on the PCI bus, the ADl 31: 0 l signals are in the output mode, during the first PCI clock period of a local bus ADl 31: 0 cycle. l contain a physical address During following clocks, the lines ADl 31: 0 l are put in floating state by the CDC When the CDC plays the role of target on the PCI bus, the signals ADl 31: 0 l contain the address during the first clock and during subsequent data clocks but the data channel for the cycles initialized PCI to the CDC does not cross the CDC ADl 31: 0 l Input / Output C / BEl 3: 0 l # Input / Output Bus control and byte enable signals that are multiplexed on the same pins During the address phase of a transaction, C / BEl 3: 0 l # defines the bus command during the phase, C / BEl 3: 0 l # are used as byte validations Byte validations determine which byte channels s have meaningful data carriers PCI local bus command encoding and command types

are listed below.

  C / BEl 3: 0 l # Command type Interruption acknowledgment Special cycle Read I / O Write I / O Reserved Reserved Read memory Write memory Write Reserved Reserved Configuration Write configuration Reserved Write and disable memory Read long memory Write recordable memory FRAME # Input Cycle sequence is an output when the

  CDC output plays the role of master on the PCI bus.

FRAME # is piloted by the CDC so

  indicate the start and duration of an access.

  FRAME # is applied to indicate that a bus transaction is starting While FRAME # is applied, data transfers continue When FRAME # is no longer applied, the transaction is in the final data phase FRAME # is an entry when the CDC plays the role of PCI slave When the CDC plays the role of target on the PCI bus, it locks the C / BEl signals 3: 0 l and ADl 31: 0 l on the clock front on which it samples FRAME # in active state. TRDY # Target Entry / Loan is an entry when CDC is playing

  Exit the master role on the PCI bus.

  The application of TRDY # indicates the target action capacity to complete the current data phase of the transaction For read cycles, TRDY # indicates that the target has piloted valid read data on the PCI local bus For a write cycle, TRDY # indicates that the target is prepared to accept write data from the PCI bus TRDY # is an output when the CDC acts as a PCI slave. IRDY # Input / Initiator ready is an output when CDC Output plays the role of PCI MASTER The application of IRDY # indicates the master capacity of the current PCI bus to complete the current data phase of the transaction For read cycles, IRDY # indicates that the PCI master is prepared to accept the read data on the next rising edge of the PCI clock For a write cycle, IRDY # indicates that the master has controlled

  valid write data on the PCI bus.

  IRDY # is an entry when the CDC plays the

PCI slave role.

  LOCK # Entry / Lock indicates an exclusive Exit bus operation and may require multiple transactions to complete When LOCK # is applied, non-transitions

exclusive can take place.

  The authorization to start a transaction on the PCI local bus does not guarantee the command of the LOCK # signal The command of LOCK # is obtained under its own protocol in conjunction with the GNT # signal It is possible that different agents use the PCI local bus while a single master remains the owner of the signal

LOCK #.

  STOP # Input / Stop indicates that the current bus master must immediately exit its current local bus cycle during the next clock edge

  and must release the local bus command.

  Stop # is used for logout, retry, and shutdown sequences

premature on the PCI bus.

  REQ # Request Output indicates that the PCI local bus arbitrates that the CDC wishes to use the PCI bus. GNT # Authorization Entry indicates that access to the bus

local PCI has been authorized by the CDC.

  PAR Input / Parity is controlled by the CDC when it plays the PCI master role output during address and data phases for write cycles and during the address phase for a read cycle When the CDC plays the role of PCI slave, a parity is controlled by the CDC for the data phase for a PCI read cycle The parity is

  even parity on ASl 31: 0 l and C / BEl 3: 0 l.

The CDC does not perform any

parity check.

SERR #

Collec-

  open output pin System error signal, when driven by the CDC, indicates that either parity errors on a DRAM or on a cache have occurred or that a CDC has received a target premature interrupt The CDC receives the parity error indication from the DPU (DPUPE #), qualifies it with the type of cycle and if there is a parity error, it is signaled by the signal SERR # SERR # is also pulsed if the CDC receives a target premature outage on a cycle

PCI initialized by the CDC.

  DEVSEL # Input / Device selection, when active, indicates Output that a PCI slave device has decoded its

  address as target of current access.

  The DEVSEL # CDC drives based on the DRAM address range that is accessed by a PCI master. As an input, it indicates whether or not any device on the

bus has been selected.

  FLSHREQ Input The justification request signal instructs the CDC to justify its write buffers registered CPU to PCI and to invalidate any other recording in these buffers as long as the signal FLSHREQ # remains active The CDC gives acknowledgment of receipt of the end of the write buffer justification operation by applying the MEMACK # signal This signal is controlled by the expansion bus bridge and is used to avoid deadlock conditions on the

PCI bus.

  MEMREQ # Input The memory request signal instructs the CDC to justify its host vis-à-vis the DRAM and its host vis-à-vis the PCI registered write buffers and to keep the host CPU under address blocking (AHOLD) as long as the MEMREQ # signal remains active The CDC gives acknowledgment of receipt of the end of the justification operations by applying the MEMACK # signal This signal is controlled by the expansion bus bridge and it is used to produce an access latency minimum

  during ISA DRAM master cycles.

  MEMACK # Exit The memory acknowledgment signal indicates the end of the operations requested by FLSHREQ signals #

and / or MEMREQ # active.

DPU command interface

Type Name Description

  pin / DPUPE # signal Input The DPU parity error signal indicates that a DRAM or cache data parity error occurred during a DPUPE # data read operation is active for a period of a clock from the clock edge at which read data is sampled by the master CPU or PCI A parity error on any of the four bytes

  is indicated as active DPUPE #.

  PCI data parity signal is input to CDC During PCI read cycles from memory or during CPU write to PCI, the DPU generates even parity for PCI data before this information to the CDC by the intermediate of the PCIDP pin The CDC combines this data parity information with the BEl 3: l # and

  generates PCI parity, i.e. the PAR signal.

  The host bus signal on memory / PCI is the source selection / distension signal of

  data for the DPU host interface.

  HM / P #, when at a low level, indicates that data must be read or written on the PCI bus When this signal is at a high level, the data is read or written in the memory This signal, with the HSTB # and HW / R # signals, controls the locking of data in the host recording buffers and the selection of data from memory or from

PCI read buffers.

  HM / P # Input Output HW / R # Output The write / read signal on the host bus is used to distinguish between read and write cycles of the host CPU HW / R #, when it is at a low level, indicates a read cycle for the host CPU When this signal is at a high level, it indicates a write cycle for the host CPU This signal as well as the HM / P # and HSTB # signals control the locking of the data in the buffers host registration and data selection in

PCI memory read buffers.

  HSTB # Output The host bus data sampling signal is used to control the latching of data in the host record buffers during write cycles and to select data from memory or buffers.

  PCI reading during read cycles.

  When this signal is applied during a write cycle, the appropriate record buffer lockout is enabled on the rising edge of CLK 1 if selected

by HM / P #.

  During a read cycle, HSTB # is applied during the rising edge of CLK 1 to select one of two read flip-flops. PM / H # PCI bus output for memory / host signal is the source / destination selected for the PCI interface of the PM / H # CPU, when it is low, indicates that the data

  must be read or written by the host bus.

  When this signal is at a high level, the data is read or written in the memory This signal as well as the PSTB # and PW / R # signals control the locking of the data in the PCI recording buffers and the selection of the data in the memory read buffers or host record buffers. PW / R # Output PCI bus write / read signal is used to distinguish between

  PCI write and read cycles.

  PW / R #, when at a low level, indicates a PCI read cycle When this signal is at a high level, it indicates a PCI write cycle This signal as well as figures PM / H # and PSTB # control locking of data in PCI record buffers and selection of data in memory read buffers or host record buffers. PSTB # 1 Output MH / P # Output The PCI bus data sampling signal is used to control the locking of data in the PCI recording buffers during write cycles and to select data in the memory read buffers or in the host recording buffers during read cycles When this signal is active during a write cycle, the locking of the appropriate recording buffers is validated on the rising clock edge During a read cycle, PSTB # in the active state causes selection of read data

  appropriate on the increasing clock face.

  When PSTB # is disabled, no changes are made to the lock command or to the

  selected reading data.

  Memory bus for host / PCI signal is the source / destination of data selected for a memory interface of the MH / P # DPU, when it is at a low level, indicates that data must be read or written by the bus PCI When this signal is at a high level, the data is read or written by the host bus During memory read cycles, this signal as well as the signal MSTB # control the locking of the data in the memory read buffer During cycles memory write, MH / P #, MR / W # and MSTB # signals select either host CPU buffers or buffers

PCI registration.

  WE # / Output The memory bus read / write signal is MR / W # used to distinguish between read and write cycles MR / W #, when at a low level, indicates a write cycle memory When this signal is at a high level, it indicates a memory read cycle This signal as well as the signal MSTB # control the locking of the data in the memory read buffers and the selection of the data in

  host or PCI registration buffers.

  MSTB # Output The memory bus data sampling signal is used to control the locking of data in the memory read buffers during read cycles and to select data in the host buffers or PCI record buffers during write cycles When this signal is active during a memory read cycle, the locking of the appropriate read buffer is validated. During a memory write cycle, the data of the appropriate record buffer are selected as determined by the

  MH / P # signal and are controlled on the MD bus.

  When MSTB # is disabled, no changes are made to the read buffer command or to the selection of record buffer data. Reset and clock signals

Type Name Description

  pin / PWROK signal Input The power supply input forces all internal registers and all machines in their faulty state This input is asynchronous but it must meet the establishment and maintenance specifications for recognition during any SRESET specification clock # Input Software reset input forces all internal CDC machines to their failing state; however, the contents of the configuration registers remain unmodified This entry is asynchronous but it must meet specifications for establishment and maintenance for recognition during

  of any specific clock.

  CLK 2 Input The 2 X clock input is internally halved to generate CPU, DPU and PCI device clocks and is produced from six clock output signals (CLK 1 A-CLK 1 F) A CMOS level clock signal that operates at twice the operating speed of the

  CDC must be produced on this signal.

  CLK 1 Input Clock input 1 X produces the fundamental timing and internal operating frequency for the CDC This signal is typically connected as feedback from one of the six clock output pins of the CDC (CLK 1 A-CLK 1 F) The CDC operates at clock frequencies of 25 or 33 M Hz Most of the external timing parameters are specified relative to the increasing or decreasing edge of CLK 1 Maximum asymmetry between

  the clocks of CDC and CPU is worth 1 ns.

  Maximum clock asymmetry between

CDC and PCI agents are worth 2 ns.

  CLK 1 A Output These six clock output signals 1 X CLK 1 F constitute the clock reference for the system's CPU, DPU and PCI devices. The CDC divides the clock produced on CLK 2 by two to generate these signals. CLK 1 input signal must be connected to one of these signals, preferably the one used

for the CPU clock.

Claims (10)

  1 computer system characterized in that comprises: a) a processor unit comprising a cache E first internal level; b) a system random access memory (206) c) one or more data input devices d) one or more data output devices e) a system clock generation means (202) f) a second level cache (207) comprising: one or more groups of CA memories that are asynchronous; a cache controller (202) comprising independent control means for said or for each of said groups of asynchronous cache memories; and means for generating control signals on said or each of said groups of asynchronous cache memories so that they are correlated to said system clock signal.   2 computer system according to claim 1, characterized in that said cache controller (202) is further constituted by means for predicting a read address   following from a first reading address produced.   3 Cache system characterized in that it comprises a) one or more groups of non-interlaced cache memory means (202); b) system clock generation means for generating a system clock signal; c) means (LCA) for correlating control signals to said one or more groups of cache memory means with said system clock signal; and d) means (BRDY) for generating burst data from said one or more groups of non-interleaved cache means. 4 cache system according to claim 3, characterized in that said group or groups of non-interlaced cache memory means are constituted by   dynamic asynchronous static random access memory devices.   Cache system according to claim 4, characterized in that said system clock generation means is further constituted by means making it possible to generate a 1 X clock signal from a 2 X clock signal. 6 Cache system according to Claim 5, characterized in that the said means for correlating control signals to the said group or groups of cache memory means with the said system clock signal consists of: a first control signal having an intrinsic delay greater than that of a second control signal; and delay means (505) for delaying said first control signal so that the delay of said first control signal is equal to the delay of said second control signal. 7 cache system according to claim 6, characterized in that said delay means is further constituted by an even number of reversers inserted in the path   circuit of said first control signal.   8 cache system according to claim 5, characterized in that said means for producing the burst data from said group or groups of non-interleaved cache memory means consists of: a) means for predicting following addresses from 'a first address produced; and b) means for generating data from said next predicted addresses during clock signal cycles consecutive system.   9 cache system according to claim 8, characterized in that said means for predicting subsequent addresses from a first produced address is further constituted by: a) means for extracting a plurality of bits from said first address produced; and b) means for identifying a predetermined sequence of addresses associated with the content of said plurality of extracted bits. 10 A method of producing cache control signals in a cache subsystem, characterized in that it comprises the steps of: a) generation of a clock signal IX from a clock signal 2 X; b) producing said 1 X clock signal as a system clock; c) producing processor control signals based on said 1 X clock signal; d) production of said 2 X clock signal on a cache controller; and e) generating control signals from said cache controller so that there is a delay of zero with respect to said system clock and with respect to said processor control signals.   A method for producing cache control signals according to claim 10, characterized in that said step of producing control signals from said cache controller so that there is a delay to zero with respect to said clock system and with respect to said processor control signals is further constituted by the steps of: a) identifying a first control signal which has an intrinsic delay greater than that of a second control signal; b) delaying the production of said first control signal so that it has a delay equal to that of said second control signal; and c) production of said first control signal and said second control signal on the basis of said 2 X clock signal. 12 Method according to claim 10, characterized in that it further comprises the steps of: a) identification of a request to read a burst b) identification of a plurality of subsequent addresses from a first address produced; and c) generating control signals to read data from said first produced address and from said following plurality of addresses.   13 Cache controller characterized in that it comprises a) a reception means for receiving a 2 X clock signal; b) means for generating a 1 X clock signal from said 2 X clock signal and for producing said 1 X clock signal as a system clock signal; and c) means for producing cache controller signals delaying zero with respect to said signal system clock produced.   14 cache controller according to claim 13, characterized in that said means for producing cache controller signals having a delay to zero with respect to said produced system clock signal is further constituted by a delay means inserted in the channel cache control signal circuit having delays shorter than the   circuit path of other cache control signals.   15 cache controller according to claim 14, characterized in that said delay means is constituted by a even number of inverters.   16 Cache controller according to claim 13, further characterized in that it is constituted by a means making it possible to produce a plurality of data in response to a request to read a burst, constituted by: a) a means for identifying a request for burst reading; b) means for predicting a plurality of subsequent addresses from a first produced address; and c) means for producing said next address upon   consecutive system clock cycles.   17 Cache controller according to claim 16, characterized in that said means for predicting a plurality of subsequent addresses from a first address produced is further constituted by: a) means for extracting a plurality of bits from said first address produced; and b) means for identifying a predetermined sequence of addresses associated with the content of said plurality of extracted bits.